Lin corrections after successful lin mcal tests

diff --git a/arch/ppc/mpc55xx/drivers/LinFlex.c b/arch/ppc/mpc55xx/drivers/LinFlex.c
index 0ac472f83abcbab0b72f1e0b0101e54e22a8891f..bc284bcc662767ccca3caaf6fd69a7b02e6aabd1 100644 (file)
--- a/arch/ppc/mpc55xx/drivers/LinFlex.c
+++ b/arch/ppc/mpc55xx/drivers/LinFlex.c
@@ -34,10 +34,8 @@
 static Lin_DriverStatusType LinDriverStatus = LIN_UNINIT;\r
 \r
 static Lin_StatusType LinChannelStatus[LIN_CONTROLLER_CNT];\r
-static Lin_StatusType LinChannelOrderedStatus[LIN_CONTROLLER_CNT];\r
 \r
 /* static buffers, holds one frame at a time */\r
-static uint8 LinBufTx[LIN_CONTROLLER_CNT][LIN_MAX_MSG_LENGTH];\r
 static uint8 LinBufRx[LIN_CONTROLLER_CNT][LIN_MAX_MSG_LENGTH];\r
 \r
 typedef volatile union {\r
@@ -197,7 +195,6 @@ void Lin_Init( const Lin_ConfigType* Config )
                /* LIN171: On entering the state LIN_INIT, the Lin module shall set each channel into\r
                 * state LIN_CH_UNINIT. */\r
                LinChannelStatus[i] = LIN_CH_UNINIT;\r
-               LinChannelOrderedStatus[i]=LIN_CH_OPERATIONAL;\r
        }\r
 \r
        /* LIN146: LIN_UNINIT -> LIN_INIT: The Lin module shall transition from LIN_UNINIT\r
@@ -245,8 +242,9 @@ void Lin_InitChannel(  uint8 Channel,   const Lin_ChannelConfigType* Config )
 \r
        /* configure and enable channel */\r
        LINFLEXHw->LINCR1.B.INIT = 1; /* Go to init mode */\r
+       LINFLEXHw->LINCR1.R = 1; /* Clear all */\r
        LINFLEXHw->LINCR1.B.MBL = 3; /* 13 bit synch */\r
-       LINFLEXHw->LINCR1.B.MME = 3; /* Master mode */\r
+       LINFLEXHw->LINCR1.B.MME = 1; /* Master mode */\r
        LINFLEXHw->LINCR1.B.CCD = 0;\r
        LINFLEXHw->LINCR1.B.CFD = 0;\r
        LINFLEXHw->LINCR1.B.LASE = 0;\r
@@ -347,7 +345,7 @@ Std_ReturnType Lin_SendHeader(  uint8 Channel,  Lin_PduType* PduInfoPtr )
        LINFLEXHw->BIDR.B.DFL = PduInfoPtr->DI - 1;\r
 \r
        /* Id */\r
-       LINFLEXHw->BIDR.B.ID = PduInfoPtr->Pid & 0x7f; /* Without parity bit */\r
+       LINFLEXHw->BIDR.B.ID = PduInfoPtr->Pid; /* Without parity bit */\r
 \r
        /* Direction */\r
        if (PduInfoPtr->Drc == LIN_MASTER_RESPONSE)\r
@@ -421,14 +419,13 @@ Std_ReturnType Lin_GoToSleep(  uint8 Channel )
        VALIDATE_W_RV( (Channel < LIN_CONTROLLER_CNT), LIN_GO_TO_SLEEP_SERVICE_ID, LIN_E_INVALID_CHANNEL, E_NOT_OK);\r
        VALIDATE_W_RV( (LinChannelStatus[Channel] != LIN_CH_SLEEP), LIN_GO_TO_SLEEP_SERVICE_ID, LIN_E_STATE_TRANSITION, E_NOT_OK);\r
 \r
-       if (LinChannelOrderedStatus[Channel]!=LIN_CH_SLEEP){\r
-               LinChannelOrderedStatus[Channel]=LIN_CH_SLEEP;\r
+       LINFLEXHw->LINCR1.B.SLEEP = 1;\r
 \r
-               LINFLEXHw->LINCR1.B.SLEEP = 1;\r
+       LINFLEXHw->LINIER.B.WUIE = 1; /* enable wake-up irq */\r
 \r
-               LINFLEXHw->LINIER.B.WUIE = 1; /* enable wake-up irq */\r
-       }\r
-       return E_OK;\r
+    LinChannelStatus[Channel]=LIN_CH_SLEEP;\r
+\r
+    return E_OK;\r
 }\r
 \r
 Std_ReturnType Lin_GoToSleepInternal(  uint8 Channel )\r
@@ -459,8 +456,45 @@ Std_ReturnType Lin_WakeUp( uint8 Channel )
        return E_OK;\r
 }\r
 \r
+static void CopyToBuffer(uint8 *buf, volatile struct LINFLEX_tag * LINFLEXHw)\r
+{\r
+       for(int i = 0; i < 8;i++)\r
+       {\r
+               /* convenient with freescale reg file */\r
+               switch(i)\r
+               {\r
+               case 0:\r
+                        buf[0] = LINFLEXHw->BDRL.B.DATA0;\r
+                       break;\r
+               case 1:\r
+                        buf[1] = LINFLEXHw->BDRL.B.DATA1;\r
+                       break;\r
+               case 2:\r
+                        buf[2] = LINFLEXHw->BDRL.B.DATA2;\r
+                       break;\r
+               case 3:\r
+                        buf[3] = LINFLEXHw->BDRL.B.DATA3;\r
+                       break;\r
+               case 4:\r
+                        buf[4] = LINFLEXHw->BDRM.B.DATA4;\r
+                       break;\r
+               case 5:\r
+                        buf[5] = LINFLEXHw->BDRM.B.DATA5;\r
+                       break;\r
+               case 6:\r
+                        buf[6] = LINFLEXHw->BDRM.B.DATA6;\r
+                       break;\r
+               case 7:\r
+                        buf[7] = LINFLEXHw->BDRM.B.DATA7;\r
+                       break;\r
+               }\r
+       }\r
+}\r
+\r
 Lin_StatusType Lin_GetStatus( uint8 Channel, uint8** Lin_SduPtr )\r
 {\r
+       volatile struct LINFLEX_tag * LINFLEXHw = LINFLEX(Channel);\r
+\r
        VALIDATE_W_RV( (LinDriverStatus != LIN_UNINIT), LIN_GETSTATUS_SERVICE_ID, LIN_E_UNINIT, LIN_NOT_OK);\r
        VALIDATE_W_RV( (LinChannelStatus[Channel] != LIN_CH_UNINIT), LIN_GETSTATUS_SERVICE_ID, LIN_E_CHANNEL_UNINIT, LIN_NOT_OK);\r
        VALIDATE_W_RV( (Channel < LIN_CONTROLLER_CNT), LIN_GETSTATUS_SERVICE_ID, LIN_E_INVALID_CHANNEL, LIN_NOT_OK);\r
@@ -471,6 +505,7 @@ Lin_StatusType Lin_GetStatus( uint8 Channel, uint8** Lin_SduPtr )
        Lin_StatusType res = LinChannelStatus[Channel];\r
        /* We can only check for valid sdu ptr when LIN_RX_OK */\r
        if(LinChannelStatus[Channel] == LIN_RX_OK || LinChannelStatus[Channel] == LIN_RX_ERROR){\r
+               CopyToBuffer(LinBufRx[Channel], LINFLEXHw);\r
                *Lin_SduPtr = LinBufRx[Channel];\r
                if(LinChannelStatus[Channel] == LIN_RX_ERROR){\r
                        ResyncDriver(Channel);\r

diff --git a/arch/ppc/mpc55xx/drivers/Mcu.c b/arch/ppc/mpc55xx/drivers/Mcu.c
index 305c590c8a98d5689c093193eab2d22157ff0b06..43349616eae096cd5beeb6e2246bdc0c5565ec18 100644 (file)
--- a/arch/ppc/mpc55xx/drivers/Mcu.c
+++ b/arch/ppc/mpc55xx/drivers/Mcu.c
@@ -451,6 +451,10 @@ Std_ReturnType Mcu_InitClock(const Mcu_ClockType ClockSetting)
     while (ME.GS.B.S_MTRANS) {}\r
     /* Verify RUN0 is the current mode */\r
     while(ME.GS.B.S_CURRENTMODE != 4) {}\r
+\r
+    CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
+    CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
+    CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
 #elif defined(CFG_MPC5606S)\r
     // Write pll parameters.\r
     CGM.FMPLL[0].CR.B.IDF = clockSettingsPtr->Pll1;\r
@@ -486,6 +490,10 @@ Std_ReturnType Mcu_InitClock(const Mcu_ClockType ClockSetting)
     /* Verify RUN0 is the current mode */\r
     while(ME.GS.B.S_CURRENTMODE != 4) {}\r
 \r
+    CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
+    CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
+    CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
+\r
  #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
     // Partially following the steps in MPC5567 RM..\r
     FMPLL.SYNCR.B.DEPTH        = 0;\r