#include "Det.h"\r
#include "Cpu.h"\r
#include <string.h>\r
+#include "../kernel/core_cr4.h"\r
\r
-GIO_RegisterType *GPIO_ports[] = { GIO_PORTA_BASE, GIO_PORTB_BASE };\r
+GIO_RegisterType *GPIO_ports[] = { GIO_PORTA_BASE, GIO_PORTB_BASE, GIO_HET_PORT1_BASE };\r
\r
#define DIO_GET_PORT_FROM_CHANNEL_ID(_channelId) (_channelId >> 8)\r
#define DIO_GET_BIT_FROM_CHANNEL_ID(_channelId) (1 << (_channelId & 0x1F))\r
VALIDATE_CHANNEL(channelId, DIO_WRITECHANNEL_ID);\r
\r
Dio_PortType port = DIO_GET_PORT_FROM_CHANNEL_ID(channelId);\r
- uint16 bit = DIO_GET_BIT_FROM_CHANNEL_ID(channelId);\r
+ uint32 bit = DIO_GET_BIT_FROM_CHANNEL_ID(channelId);\r
\r
if (!( GPIO_ports[port]->DIR & bit)) { // This is an input channel.\r
goto cleanup;\r
#endif\r
\r
\r
-#define CORE_CPUID_CORTEX_M3 0x411FC231UL\r
+#define CORE_MIDR_CORTEX_R4 0x411FC141UL // c0, Main ID Register\r
+\r
\r
typedef struct {\r
uint32 lossOfLockCnt;\r
\r
\r
\r
-\r
-\r
-\r
/**\r
* Type that holds all global data for Mcu\r
*/\r
\r
\r
\r
-/* Haven't found any ID accessable from memory.\r
- * There is the DBGMCU_IDCODE (0xe0042000) found in RM0041 but it\r
- * you can't read from that address..\r
- */\r
+// see tech.ref.manual for Debug Reference Register\r
#if 0\r
cpu_info_t cpu_info_list[] = {\r
{\r
*/\r
core_info_t core_info_list[] = {\r
{\r
- .name = "CORE_ARM_CORTEX_M3",\r
- .pvr = CORE_CPUID_CORTEX_M3,\r
+ .name = "CORE_ARM_CORTEX_R4",\r
+ .pvr = CORE_MIDR_CORTEX_R4,\r
},\r
};\r
\r
/** - Setup pll control register 1:\r
* - Setup reset on oscillator slip\r
* - Setup bypass on pll slip\r
+ * - Setup Pll output clock divider\r
* - Setup reset on oscillator fail\r
- * - Setup Pll output clock divider\r
* - Setup reference clock divider\r
* - Setup Pll multiplier*\r
+ *\r
*/\r
systemREG1->PLLCTL1 =\r
(MCU_RESET_ON_SLIP << MCU_RESET_ON_SLIP_OFFSET)\r
| (((clockSettingsPtr->Pll2 - 1) * 256) << MCU_PLLMUL_OFFSET)\r
| ((clockSettingsPtr->Pll4 - 1) << MCU_PLLDIV_OFFSET);\r
\r
-\r
/** Setup PLLCTL2\r
* - Setup internal Pll output divider\r
* - Enable/Disable frequency modulation (NOT USED)\r
* - Setup bandwidth adjustment (NOT USED)\r
* - Setup spreading amount (NOT USED)\r
*/\r
- systemREG1->PLLCTL2 =\r
+ /*systemREG1->PLLCTL2 =\r
(MCU_FM_ENABLE << MCU_FM_ENABLE_OFFSET)\r
| (MCU_SPREADING_RATE << MCU_SPREADING_RATE_OFFSET)\r
| (MCU_BWADJ << MCU_BWADJ_OFFSET)\r
| (MCU_SPREADING_AMOUNT << MCU_SPREADING_AMOUT_OFFSET)\r
- | ((clockSettingsPtr->Pll3 - 1) << MCU_ODPLL_OFFSET);\r
+ | ((clockSettingsPtr->Pll3 - 1) << MCU_ODPLL_OFFSET);*/\r
+\r
+ systemREG1->PLLCTL2 = 0x00000000U\r
+ | (255U << 22U)\r
+ | (7U << 12U)\r
+ | ((2U - 1U)<< 9U)\r
+ | 61U;\r
+\r
+ /** @b Initialize @b Pll2: */\r
+\r
+ /** - Setup pll2 control register :\r
+ * - setup Pll output clock divider to max before Lock\r
+ * - Setup reference clock divider\r
+ * - Setup internal Pll output divider\r
+ * - Setup Pll multiplier\r
+ */\r
+ systemREG2->PLLCTL3 = ((2U - 1U) << 29U)\r
+ | ((0x1F)<< 24U)\r
+ | ((6U - 1U)<< 16U)\r
+ | ((135U - 1U) << 8U);\r
+\r
+ /** - Enable PLL(s) to start up or Lock */\r
+ systemREG1->CSDIS = 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000008U\r
+ | 0x00000080U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U;\r
+\r
\r
/** - Wait for until clocks are locked */\r
while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) ;\r
while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) ;\r
\r
/** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */\r
- systemREG1->GHVSRC = (SYS_PLL << 24U) // Selectes PLL clock (clock source 1) as wakeup clock source.\r
+ systemREG1->GHVSRC = (SYS_PLL << 24U) // Selectes PLL clock (clock source 1) as wakeup clock source. (Use main oscillator as wake up source for GHV CLK)\r
| (SYS_PLL << 16U) // Select PLL clock (clock source 1) as wakeup when GCLK is off as clock source.\r
| SYS_PLL; // Select PLL clock (clock source 1) as current clock source.\r
\r
+ /** - Disable Peripherals before peripheral powerup*/\r
+ systemREG1->PENA = 0U;\r
+\r
/** - Power-up clocks to all peripharals */\r
pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;\r
pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;\r
\r
#define PORT_NOT_CONFIGURED 0x00000000\r
\r
-#define PORT_0_BASE ((Port_RegisterType *)0xFFF7BC30)\r
-#define PORT_1_BASE ((Port_RegisterType *)0xFFF7BC50)\r
-#define PORT_2_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
+#define PORT_0_BASE ((Port_RegisterType *)0xFFF7BC30) // GIO Emulation B register\r
+#define PORT_1_BASE ((Port_RegisterType *)0xFFF7BC50) // GIO Pull Select Register A ??\r
+#define PORT_2_BASE ((Port_RegisterType *)0xFFF7B848) // N2HET1\r
#define PORT_3_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
#define PORT_4_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
#define PORT_5_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
#define PORT_6_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
#define PORT_7_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
-#define PORT_8_BASE ((Port_RegisterType *)0xFFF7DDE0)\r
-#define PORT_9_BASE ((Port_RegisterType *)0xFFF7DFE0)\r
-#define PORT_10_BASE ((Port_RegisterType *)0xFFF7E1E0)\r
+#define PORT_8_BASE ((Port_RegisterType *)0xFFF7DDE0) // DCAN1 TX IO Control Register\r
+#define PORT_9_BASE ((Port_RegisterType *)0xFFF7DFE0) // DCAN2 TX IO Control Register\r
+#define PORT_10_BASE ((Port_RegisterType *)0xFFF7E1E0) // DCAN3 TX IO Control Register\r
#define PORT_NUMBER_OF_PORTS 11\r
\r
static Port_RegisterType * const Port_Base[] =\r
// Bring GIO register out of reset.\r
gioREG->GCR0 = 1;\r
\r
+ /* Hack to connect N2HET1[27] (function 2) to pin A9 */\r
+ *(volatile uint32*)0xFFFFEB10 &= ~0xFF000000;\r
+ *(volatile uint32*)0xFFFFEB10 |= ~0x04000000;\r
+\r
for (uint16 i = 0; i < PORT_NUMBER_OF_PINS; i++) {\r
Port_RefreshPin(i);\r
}\r
\r
#define GIO_PORTA_BASE ((GIO_RegisterType *)0xFFF7BC34)\r
#define GIO_PORTB_BASE ((GIO_RegisterType *)0xFFF7BC54)\r
-\r
+#define GIO_HET_PORT1_BASE ((GIO_RegisterType *)0xFFF7B84CU)\r
\r
/** @def gioREG\r
* @brief GIO Register Frame Pointer\r
/* System level configuration\r
This mainly involves setting instruction mode for exceptions and interrupts.\r
*/\r
- mrc p15,0,r11,c1,c0,0 /* Read current system configuration */\r
+ mrc p15,0,r11,c1,c0,0 /* Read current system configuration */ /* read System Control Register (SCTLR) */\r
mov r12, #0x40000000 /* Set THUMB instruction set mode for interrupts and exceptions */\r
orr r12, r12, r11\r
- mcr p15,0,r12,c1,c0,0 /* Write new configuration */\r
+ mcr p15,0,r12,c1,c0,0 /* Write new configuration */ /* write SCTLR */\r
\r
\r
/* Initialize stack pointers.\r
#ifndef DIO_CFG_H_\r
#define DIO_CFG_H_\r
#include "Port.h"\r
+#include "Std_Types.h" /** @req DIO131 */\r
\r
#define DIO_VERSION_INFO_API STD_OFF\r
#define DIO_DEV_ERROR_DETECT STD_OFF\r
\r
intvecs(R) : ORIGIN = 0x0000000, LENGTH = 0x60\r
-flash(R) : ORIGIN = 0x00000060, LENGTH = 2M\r
-ram(RW) : ORIGIN = 0x08000000, LENGTH = 160K\r
+flash(R) : ORIGIN = 0x00000060, LENGTH = 3M\r
+ram(RW) : ORIGIN = 0x08000000, LENGTH = 256K\r
#define DIO_H_
#include "Modules.h"
-#include "Std_Types.h" /** @req DIO131 */
+#include "Std_Types.h"
+
// API Service ID's
#define DIO_READCHANNEL_ID 0x00
typedef uint32 Dio_LevelType;
-typedef uint16 Dio_PortLevelType;
+typedef uint32 Dio_PortLevelType;
#endif
projects / arc.git / commitdiff