* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+/* ----------------------------[information]----------------------------------*/\r
+/*\r
+ * Author: ?\r
+ *\r
+ * Part of Release:\r
+ * ?\r
+ *\r
+ * Description:\r
+ * Implements the Watchdog Driver module\r
+ *\r
+ * Support:\r
+ * General Have Support\r
+ * -------------------------------------------\r
+ * WDG_DEV_ERROR_DETECT N\r
+ * WDG_DISABLE_ALLOWED N\r
+ * WdgIndex Y\r
+ * WDG_TRIGGER_LOCATION Y\r
+ * WdgVersionInfoApi N\r
+ *\r
+ * Implementation Notes:\r
+ * MPC5516\r
+ * SWT: driven by SIU_SYSCLK.SWTCLKSEL (here System Clock, can be 16Mhz IRC)\r
+ * - SWTCR.SE=1. Enabled by default. Override with RCHW.\r
+ * - RCHW (WTE bit, 0-disabled, 1-enabled) (This area is read by BAM)\r
+ * OnChip\r
+ * - BookE, disabled by default. SPR_TCR.WRC!=0 enables watchdog\r
+ */\r
+\r
#include "mpc55xx.h"\r
#include "Wdg.h"\r
#include "Mcu.h"\r
static const Wdg_ConfigType *configWdgPtr;\r
static const Wdg_SettingsType *modeWdgConfig;\r
\r
+#if defined(CFG_MPC5516)\r
\r
+#define SWTCR_SWRI(_x) ((_x)<<5)\r
+#define SWTCR_SWT(_x) (_x)\r
+#define SWTCR_SWE (1<<7)\r
+#endif\r
\r
-void StartWatchdog(void)\r
+void StartWatchdog(uint32 timeout_in_ms)\r
{\r
#if defined(CFG_MPC5567)\r
- ECSM.SWTCR.R = 0x00D8;;\r
+ (void)timeout_in_ms;\r
+ ECSM.SWTCR.R = 0x00D8;\r
#elif defined(CFG_MPC560X) || defined(CFG_MPC5668)\r
+ (void)timeout_in_ms;\r
SWT.CR.R = 0x8000011B;\r
+#elif defined(CFG_MPC5516)\r
+ /* We running on system clock, ie SIU_SYSCLK.SWTCLKSEL, so get the value */\r
+\r
+ /* The timeout is 2^x, so get best possible value\r
+ * Table for 80Mhz\r
+ * ------------------\r
+ * 2^9 = 512 = 6.4 uS\r
+ * 2^15 = 400 uS\r
+ * 2^20 = 13 mS\r
+ * 2^28 = 3.3 S\r
+ * 2^31 = 26,84 S\r
+ *\r
+ * Formula:\r
+ * 1/clock * 2^n = tmo_in_s\r
+ * 2^n = tmo_in_s * clock -> n = log2(tmo_in_s * clock) = log2(tmo_in_ms * clock / 1000 )\r
+ * */\r
+ uint32 swtVal = ilog2( McuE_GetSystemClock()/1000 * timeout_in_ms );\r
+#if defined(CFG_WDG_TEST)\r
+ MCM.SWTCR.R = (SWTCR_SWE + SWTCR_SWRI(WDG_SWRI_VAL) + swtVal);\r
#else\r
- MCM.SWTCR.R = 0x00D8;\r
+ MCM.SWTCR.R = (SWTCR_SWE + SWTCR_SWRI(2) + swtVal);\r
#endif\r
\r
+#else\r
+ MCM.SWTCR.R = 0x00D8;\r
+#endif\r
}\r
\r
- void StopWatchdog(void)\r
- {\r
- #if defined(CFG_MPC5567)\r
+/**\r
+ * Disable the watchdog\r
+ */\r
+void StopWatchdog(void)\r
+{\r
+#if defined(CFG_MPC5567)\r
ECSM.SWTCR.R = 0x0059;;\r
- #elif defined(CFG_MPC560X) || defined(CFG_MPC5668)\r
+#elif defined(CFG_MPC560X) || defined(CFG_MPC5668)\r
SWT.SR.R = 0x0000c520; /* Write keys to clear soft lock bit */\r
SWT.SR.R = 0x0000d928;\r
SWT.CR.R = 0x8000010A;\r
- #else\r
- MCM.SWTCR.R = 0x0059;\r
- #endif\r
- }\r
+#elif defined(CFG_MPC5516)\r
+ MCM.SWTCR.B.SWE = 0x0; /* Disable the watchdog */\r
+#else\r
+ MCM.SWTCR.R = 0x0059;\r
+#endif\r
+}\r
\r
void Wdg_Init (const Wdg_ConfigType* ConfigPtr)\r
{\r
StopWatchdog(); // must be stopped in order to change TO\r
SWT.TO.R = modeWdgConfig->ReloadValue;\r
#endif\r
- StartWatchdog();\r
+ StartWatchdog(modeWdgConfig->ReloadValue);\r
}\r
else\r
{\r
#elif defined(CFG_MPC560X)\r
SWT.SR.R = 0x0000A602;\r
SWT.SR.R = 0x0000B480;\r
+#elif defined(CFG_MPC5516)\r
+ MCM.SWTSR.R = 0x55;\r
+ MCM.SWTSR.R = 0xAA;\r
#else\r
MCM.SWTSR.R = 0x55;\r
MCM.SWTSR.R = 0xAA;\r