ADC_InitStructure.ADC_NbrOfChannel = ConfigPtr->groupConfigPtr->numberOfChannels;\r
ADC_Init(ADC1, &ADC_InitStructure);\r
\r
- for (group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ for (group = 0; group < ConfigPtr->nbrOfGroups; group++)\r
{\r
/* ADC307. */\r
ConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+\r
+/* In order to support multiple hw units we need to match group to a certain hw controller.\r
+ * We handle this in a very simple way i.e. group 0-99 -> hwUnitId 0, group 100-199 -> hwUnitId 1 etc.*\r
+ */\r
+\r
/* ----------------------------[includes]------------------------------------*/\r
\r
#include <assert.h>\r
#define ADC_WD_INT ADC_A_WD\r
#endif\r
\r
+#define GET_HW_CONTROLLER(_controller) \\r
+ ((struct ADC_tag *)(0xFFE00000 + 0x4000*(_controller)))\r
\r
+#define GET_HWUNITID_FROM_GROUP(_group) (_group / NOF_GROUP_PER_CONTROLLER)\r
\r
/* ----------------------------[private macro]-------------------------------*/\r
/* ----------------------------[private typedef]-----------------------------*/\r
\r
/* static variable declarations */\r
static Adc_StateType adcState = ADC_UNINIT;\r
-static const Adc_ConfigType *AdcConfigPtr; /* Pointer to configuration structure. */\r
+static const Adc_ConfigType *AdcGlobalConfigPtr; /* Pointer to configuration structure. */\r
\r
/* ----------------------------[private functions]---------------------------*/\r
\r
/* Function prototypes. */\r
-static void Adc_ConfigureADC (const Adc_ConfigType *ConfigPtr);\r
-static void Adc_ConfigureADCInterrupts (void);\r
-void Adc_GroupConversionComplete (Adc_GroupType group);\r
+static void Adc_ConfigureADC (const Adc_ConfigType *AdcConfigPtr);\r
+static void Adc_ConfigureADCInterrupts (const Adc_ConfigType *AdcConfigPtr);\r
+void Adc_GroupConversionComplete (Adc_GroupType group, const Adc_ConfigType *AdcConfigPtr, volatile struct ADC_tag *hwPtr);\r
+\r
+static const Adc_ConfigType * Adc_GetControllerConfigPtrFromHwUnitId(int unit)\r
+{\r
+ const Adc_ConfigType *AdcConfigPtr = NULL;\r
\r
+ for (int configId = 0; configId < ADC_ARC_CTRL_CONFIG_CNT; configId++) {\r
+ if(unit == AdcGlobalConfigPtr[configId].hwConfigPtr->hwUnitId){\r
+ AdcConfigPtr = &AdcGlobalConfigPtr[configId];\r
+ break;\r
+ }\r
+ }\r
\r
+ return AdcConfigPtr;\r
+}\r
+\r
+static const Adc_ConfigType * Adc_GetControllerConfigPtrFromGroupId(Adc_GroupType group)\r
+{\r
+ return Adc_GetControllerConfigPtrFromHwUnitId(GET_HWUNITID_FROM_GROUP(group));\r
+}\r
/* ----------------------------[public functions]----------------------------*/\r
\r
#if (ADC_DEINIT_API == STD_ON)\r
void Adc_DeInit ()\r
{\r
- if (E_OK == Adc_CheckDeInit(adcState, AdcConfigPtr))\r
- {\r
- for(Adc_GroupType group = (Adc_GroupType)ADC_GROUP0; group < AdcConfigPtr->nbrOfGroups; group++)\r
- {\r
- /* Set group status to idle. */\r
- AdcConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
- }\r
+ volatile struct ADC_tag *hwPtr;\r
\r
- /* Disable DMA transfer*/\r
-#ifndef CFG_MPC5604B\r
- ADC_0.DMAE.B.DMAEN = 0;\r
-#endif\r
- /* Power down ADC */\r
- ADC_0.MCR.R = 0x0001;\r
+ for (int configId = 0; configId < ADC_ARC_CTRL_CONFIG_CNT; configId++) {\r
+ hwPtr = GET_HW_CONTROLLER(AdcGlobalConfigPtr[configId].hwConfigPtr->hwUnitId);\r
+ const Adc_ConfigType *AdcConfigPtr = &AdcGlobalConfigPtr[configId];\r
\r
- /* Disable all interrupt*/\r
- ADC_0.IMR.R = 0;\r
+ if (E_OK == Adc_CheckDeInit(adcState, AdcConfigPtr))\r
+ {\r
+ for(Adc_GroupType group = (Adc_GroupType)0; group < AdcConfigPtr->nbrOfGroups; group++)\r
+ {\r
+ /* Set group status to idle. */\r
+ AdcConfigPtr->groupConfigPtr[group/NOF_GROUP_PER_CONTROLLER/NOF_GROUP_PER_CONTROLLER].status->groupStatus = ADC_IDLE;\r
+ }\r
\r
- /* Clean internal status. */\r
- AdcConfigPtr = (Adc_ConfigType *)NULL;\r
- adcState = ADC_UNINIT;\r
- }\r
+ /* Disable DMA transfer*/\r
+ #ifndef CFG_MPC5604B\r
+ hwPtr->DMAE.B.DMAEN = 0;\r
+ #endif\r
+ /* Power down ADC */\r
+ hwPtr->MCR.R = 0x0001;\r
+\r
+ /* Disable all interrupt*/\r
+ hwPtr->IMR.R = 0;\r
+ }\r
+ }\r
+ /* Clean internal status. */\r
+ AdcGlobalConfigPtr = (Adc_ConfigType *)NULL;\r
+ adcState = ADC_UNINIT;\r
}\r
#endif\r
\r
{\r
if (E_OK == Adc_CheckInit(adcState, ConfigPtr))\r
{\r
- /* First of all, store the location of the configuration data. */\r
- AdcConfigPtr = ConfigPtr;\r
+ /* First of all, store the location of the global configuration data. */\r
+ AdcGlobalConfigPtr = ConfigPtr;\r
\r
- /* Enable ADC. */\r
- Adc_ConfigureADC(ConfigPtr);\r
+ for (int configId = 0; configId < ADC_ARC_CTRL_CONFIG_CNT; configId++)\r
+ {\r
+ const Adc_ConfigType *AdcConfigPtr = &AdcGlobalConfigPtr[configId];\r
+\r
+ /* Enable ADC. */\r
+ Adc_ConfigureADC(AdcConfigPtr);\r
\r
- Adc_ConfigureADCInterrupts();\r
+ Adc_ConfigureADCInterrupts(AdcConfigPtr);\r
+ }\r
\r
- /* Move on to INIT state. */\r
- adcState = ADC_INIT;\r
+ /* Move on to INIT state. */\r
+ adcState = ADC_INIT;\r
}\r
}\r
\r
{\r
Std_ReturnType returnValue = E_NOT_OK;\r
\r
+ const Adc_ConfigType *AdcConfigPtr = Adc_GetControllerConfigPtrFromGroupId(group);\r
+\r
/* Check for development errors. */\r
if (E_OK == Adc_CheckSetupResultBuffer (adcState, AdcConfigPtr, group))\r
{\r
- AdcConfigPtr->groupConfigPtr[group].status->resultBufferPtr = bufferPtr;\r
+ AdcConfigPtr->groupConfigPtr[group/NOF_GROUP_PER_CONTROLLER/NOF_GROUP_PER_CONTROLLER].status->resultBufferPtr = bufferPtr;\r
\r
returnValue = E_OK;\r
}\r
\r
Adc_StreamNumSampleType Adc_GetStreamLastPointer(Adc_GroupType group, Adc_ValueGroupType** PtrToSamplePtr)\r
{\r
+ const Adc_ConfigType *AdcConfigPtr = Adc_GetControllerConfigPtrFromGroupId(group);\r
+\r
Adc_StreamNumSampleType nofSample = 0;\r
- Adc_GroupDefType *groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group];\r
+ Adc_GroupDefType *groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER];\r
\r
/** @req ADC216 */\r
/* Check for development errors. */\r
{\r
Std_ReturnType returnValue = E_OK;\r
uint8_t channel;\r
- Adc_GroupDefType *groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group];\r
+ const Adc_ConfigType *AdcConfigPtr = Adc_GetControllerConfigPtrFromGroupId(group);\r
+ Adc_GroupDefType *groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER];\r
\r
if (E_OK == Adc_CheckReadGroup (adcState, AdcConfigPtr, group))\r
{\r
}\r
#endif\r
\r
-void Adc_GroupConversionComplete (Adc_GroupType group)\r
+void Adc_GroupConversionComplete (Adc_GroupType group, const Adc_ConfigType *AdcConfigPtr, volatile struct ADC_tag *hwPtr)\r
{\r
- Adc_GroupDefType *adcGroup = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group];\r
+ Adc_GroupDefType *adcGroup = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER];\r
\r
if(ADC_ACCESS_MODE_SINGLE == adcGroup->accessMode )\r
{\r
adcGroup->status->groupStatus = ADC_STREAM_COMPLETED;\r
\r
/* Disable trigger normal conversions for ADC0 */\r
- ADC_0.MCR.B.NSTART=0;\r
+ hwPtr->MCR.B.NSTART=0;\r
\r
/* Call notification if enabled. */\r
#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)\r
Dma_ConfigureDestinationAddress((uint32_t)adcGroup->status->currResultBufPtr, adcGroup->dmaResultChannel);\r
#endif\r
\r
- ADC_0.IMR.B.MSKECH = 1;\r
- ADC_0.MCR.B.NSTART=1;\r
+ hwPtr->IMR.B.MSKECH = 1;\r
+ hwPtr->MCR.B.NSTART=1;\r
}\r
else\r
{\r
adcGroup->status->groupStatus = ADC_STREAM_COMPLETED;\r
\r
/* Disable trigger normal conversions for ADC0 */\r
- ADC_0.MCR.B.NSTART=0;\r
+ hwPtr->MCR.B.NSTART=0;\r
\r
/* Call notification if enabled. */\r
#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)\r
#endif\r
adcGroup->status->groupStatus = ADC_COMPLETED;\r
\r
- ADC_0.IMR.B.MSKECH = 1;\r
- ADC_0.MCR.B.NSTART=1;\r
+ hwPtr->IMR.B.MSKECH = 1;\r
+ hwPtr->MCR.B.NSTART=1;\r
}\r
else\r
{\r
/* Sample completed. */\r
\r
/* Disable trigger normal conversions for ADC*/\r
- ADC_0.MCR.B.NSTART=0;\r
+ hwPtr->MCR.B.NSTART=0;\r
\r
adcGroup->status->groupStatus = ADC_STREAM_COMPLETED;\r
/* Call notification if enabled. */\r
}\r
}\r
}\r
-void Adc_Group0ConversionComplete (void)\r
+\r
+void Adc_Group0ConversionComplete (int unit)\r
{\r
+ volatile struct ADC_tag *hwPtr = GET_HW_CONTROLLER(unit);\r
+ const Adc_ConfigType *AdcConfigPtr = Adc_GetControllerConfigPtrFromHwUnitId(unit);\r
+\r
/* Clear ECH Flag and disable interruput */\r
- ADC_0.ISR.B.ECH = 1;\r
- ADC_0.IMR.B.MSKECH = 0;\r
+ hwPtr->ISR.B.ECH = 1;\r
+ hwPtr->IMR.B.MSKECH = 0;\r
\r
// Check which group is busy, only one is allowed to be busy at a time in a hw unit\r
for (int group = 0; group < ADC_NBR_OF_GROUPS; group++)\r
{\r
- if((AdcConfigPtr->groupConfigPtr[group].status->groupStatus == ADC_BUSY) ||\r
- (AdcConfigPtr->groupConfigPtr[group].status->groupStatus == ADC_COMPLETED))\r
+ if((AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->groupStatus == ADC_BUSY) ||\r
+ (AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->groupStatus == ADC_COMPLETED))\r
{\r
#if !defined (ADC_USES_DMA)\r
/* Copy to result buffer */\r
- for(uint8 index=0; index < AdcConfigPtr->groupConfigPtr[group].numberOfChannels; index++)\r
+ for(uint8 index=0; index < AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].numberOfChannels; index++)\r
{\r
#if defined(CFG_MPC5606S)\r
- AdcConfigPtr->groupConfigPtr[group].status->currResultBufPtr[index] = ADC_0.CDR[32+AdcConfigPtr->groupConfigPtr[group].channelList[index]].B.CDATA;\r
+ AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->currResultBufPtr[index] = hwPtr->CDR[32+AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].channelList[index]].B.CDATA;\r
#else\r
- AdcConfigPtr->groupConfigPtr[group].status->currResultBufPtr[index] = ADC_0.CDR[AdcConfigPtr->groupConfigPtr[group].channelList[index]].B.CDATA;\r
+ AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->currResultBufPtr[index] = hwPtr->CDR[AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].channelList[index]].B.CDATA;\r
#endif\r
}\r
#endif\r
\r
- Adc_GroupConversionComplete((Adc_GroupType)group);\r
+ Adc_GroupConversionComplete((Adc_GroupType)group, AdcConfigPtr, hwPtr);\r
break;\r
}\r
}\r
}\r
\r
+static void Adc_Group0ConversionComplete_ADC0(void){\r
+ Adc_Group0ConversionComplete(ADC_CTRL_0);\r
+}\r
+\r
+static void Adc_Group0ConversionComplete_ADC1(void){\r
+ Adc_Group0ConversionComplete(ADC_CTRL_1);\r
+}\r
+\r
void Adc_WatchdogError (void){\r
}\r
void Adc_ADCError (void){\r
}\r
\r
-static void Adc_ConfigureADC (const Adc_ConfigType *ConfigPtr)\r
+static void Adc_ConfigureADC (const Adc_ConfigType *AdcConfigPtr)\r
{\r
+ volatile struct ADC_tag *hwPtr = GET_HW_CONTROLLER(AdcConfigPtr->hwConfigPtr->hwUnitId);\r
+\r
/* Set ADC CLOCK */\r
- ADC_0.MCR.B.ADCLKSEL = ConfigPtr->hwConfigPtr->adcPrescale;\r
+ hwPtr->MCR.B.ADCLKSEL = AdcConfigPtr->hwConfigPtr->adcPrescale;\r
\r
- ADC_0.DSDR.B.DSD = 254;\r
+ hwPtr->DSDR.B.DSD = 254;\r
\r
/* Power on ADC */\r
- ADC_0.MCR.B.PWDN = 0;\r
+ hwPtr->MCR.B.PWDN = 0;\r
\r
#if defined(ADC_USES_DMA)\r
/* Enable DMA. */\r
- ADC_0.DMAE.B.DMAEN = 1;\r
+ hwPtr->DMAE.B.DMAEN = 1;\r
#endif\r
}\r
\r
-void Adc_ConfigureADCInterrupts (void)\r
+void Adc_ConfigureADCInterrupts (const Adc_ConfigType *AdcConfigPtr)\r
{\r
- ISR_INSTALL_ISR2( "Adc_Err", Adc_ADCError, ADC_ER_INT, 2, 0 );\r
- ISR_INSTALL_ISR2( "Adc_Grp", Adc_Group0ConversionComplete, ADC_EOC_INT, 2, 0 );\r
- ISR_INSTALL_ISR2( "Adc_Wdg", Adc_WatchdogError, ADC_WD_INT, 2, 0 );\r
+ if(AdcConfigPtr->hwConfigPtr->hwUnitId == 0)\r
+ {\r
+ ISR_INSTALL_ISR2( "Adc_Err", Adc_ADCError, ADC0_ER_INT, 2, 0 );\r
+ ISR_INSTALL_ISR2( "Adc_Grp", Adc_Group0ConversionComplete_ADC0, ADC0_EOC_INT, 2, 0 );\r
+ ISR_INSTALL_ISR2( "Adc_Wdg", Adc_WatchdogError, ADC0_WD_INT, 2, 0 );\r
+ }\r
+ else if(AdcConfigPtr->hwConfigPtr->hwUnitId == 1)\r
+ {\r
+ ISR_INSTALL_ISR2( "Adc_Err", Adc_ADCError, ADC1_ER_INT, 2, 0 );\r
+ ISR_INSTALL_ISR2( "Adc_Grp", Adc_Group0ConversionComplete_ADC1, ADC1_EOC_INT, 2, 0 );\r
+ ISR_INSTALL_ISR2( "Adc_Wdg", Adc_WatchdogError, ADC1_WD_INT, 2, 0 );\r
+ }\r
+ else\r
+ {\r
+ assert(0);\r
+ }\r
}\r
\r
#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)\r
void Adc_StartGroupConversion (Adc_GroupType group)\r
{\r
- Adc_GroupDefType *groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group];\r
+ const Adc_ConfigType *AdcConfigPtr = Adc_GetControllerConfigPtrFromGroupId(group);\r
+ volatile struct ADC_tag *hwPtr = GET_HW_CONTROLLER(AdcConfigPtr->hwConfigPtr->hwUnitId);\r
+\r
+ Adc_GroupDefType *groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER];\r
\r
/* Run development error check. */\r
if (E_OK == Adc_CheckStartGroupConversion (adcState, AdcConfigPtr, group))\r
{\r
/* Disable trigger normal conversions for ADC0 */\r
- ADC_0.MCR.B.NSTART = 0;\r
+ hwPtr->MCR.B.NSTART = 0;\r
\r
/* Set group state to BUSY. */\r
groupPtr->status->groupStatus = ADC_BUSY;\r
if( groupPtr->accessMode == ADC_ACCESS_MODE_STREAMING)\r
{\r
/* Set conversion mode. */\r
- ADC_0.MCR.B.MODE = ADC_CONV_MODE_ONESHOT;\r
+ hwPtr->MCR.B.MODE = ADC_CONV_MODE_ONESHOT;\r
}\r
else\r
{\r
/* Set conversion mode. */\r
- ADC_0.MCR.B.MODE = groupPtr->conversionMode;\r
+ hwPtr->MCR.B.MODE = groupPtr->conversionMode;\r
}\r
\r
/* Enable Overwrite*/\r
- ADC_0.MCR.B.OWREN = 1;\r
+ hwPtr->MCR.B.OWREN = 1;\r
\r
/* Set Conversion Time. */\r
#if defined(CFG_MPC5606S)\r
uint32 groupChannelIdMask = 0;\r
\r
- ADC_0.CTR[1].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
- ADC_0.CTR[1].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
- ADC_0.CTR[1].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
+ hwPtr->CTR[1].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
+ hwPtr->CTR[1].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
+ hwPtr->CTR[1].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
\r
for(uint8 i =0; i < groupPtr->numberOfChannels; i++)\r
{\r
}\r
\r
#if defined(ADC_USES_DMA)\r
- ADC_0.DMAE.R = 0x01;\r
+ hwPtr->DMAE.R = 0x01;\r
/* Enable DMA Transfer */\r
- ADC_0.DMAR[1].R = groupChannelIdMask;\r
+ hwPtr->DMAR[1].R = groupChannelIdMask;\r
Dma_StartChannel(DMA_ADC_GROUP0_RESULT_CHANNEL); /* Enable EDMA channel for ADC */\r
#endif\r
\r
/* Enable Normal conversion */\r
- ADC_0.NCMR[1].R = groupChannelIdMask;\r
+ hwPtr->NCMR[1].R = groupChannelIdMask;\r
\r
/* Enable Channel Interrupt */\r
- ADC_0.CIMR[1].R = groupChannelIdMask;\r
+ hwPtr->CIMR[1].R = groupChannelIdMask;\r
\r
#else\r
uint32 groupChannelIdMask[3] = {0,0,0};\r
\r
- ADC_0.CTR[0].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
- ADC_0.CTR[0].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
- ADC_0.CTR[0].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
- ADC_0.CTR[1].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
- ADC_0.CTR[1].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
- ADC_0.CTR[1].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
- ADC_0.CTR[2].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
- ADC_0.CTR[2].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
- ADC_0.CTR[2].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
+ hwPtr->CTR[0].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
+ hwPtr->CTR[0].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
+ hwPtr->CTR[0].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
+ hwPtr->CTR[1].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
+ hwPtr->CTR[1].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
+ hwPtr->CTR[1].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
+// hwPtr->CTR[2].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
+// hwPtr->CTR[2].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
+// hwPtr->CTR[2].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
\r
for(uint8 i =0; i < groupPtr->numberOfChannels; i++)\r
{\r
}\r
\r
/* Enable Normal conversion */\r
- ADC_0.NCMR[0].R = groupChannelIdMask[0];\r
- ADC_0.NCMR[1].R = groupChannelIdMask[1];\r
- ADC_0.NCMR[2].R = groupChannelIdMask[2];\r
+ hwPtr->NCMR[0].R = groupChannelIdMask[0];\r
+ hwPtr->NCMR[1].R = groupChannelIdMask[1];\r
+// hwPtr->NCMR[2].R = groupChannelIdMask[2];\r
\r
/* Enable Channel Interrupt */\r
- ADC_0.CIMR[0].R = groupChannelIdMask[0];\r
- ADC_0.CIMR[1].R = groupChannelIdMask[1];\r
- ADC_0.CIMR[2].R = groupChannelIdMask[2];\r
+ hwPtr->CIMR[0].R = groupChannelIdMask[0];\r
+ hwPtr->CIMR[1].R = groupChannelIdMask[1];\r
+// hwPtr->CIMR[2].R = groupChannelIdMask[2];\r
#endif\r
/* Clear interrupts */\r
- ADC_0.ISR.B.ECH = 1;\r
+ hwPtr->ISR.B.ECH = 1;\r
/* Enable ECH interrupt */\r
- ADC_0.IMR.B.MSKECH = 1;\r
+ hwPtr->IMR.B.MSKECH = 1;\r
\r
/* Trigger normal conversions for ADC0 */\r
- ADC_0.MCR.B.NSTART = 1;\r
+ hwPtr->MCR.B.NSTART = 1;\r
}\r
else\r
{\r
\r
void Adc_StopGroupConversion (Adc_GroupType group)\r
{\r
+ const Adc_ConfigType *AdcConfigPtr = Adc_GetControllerConfigPtrFromGroupId(group);\r
+ volatile struct ADC_tag *hwPtr = GET_HW_CONTROLLER(AdcConfigPtr->hwConfigPtr->hwUnitId);\r
+\r
if (E_OK == Adc_CheckStopGroupConversion (adcState, AdcConfigPtr, group))\r
{\r
/* Disable trigger normal conversions for ADC0 */\r
- ADC_0.MCR.B.NSTART = 0;\r
+ hwPtr->MCR.B.NSTART = 0;\r
\r
/* Set group state to IDLE. */\r
- AdcConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
+ AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->groupStatus = ADC_IDLE;\r
\r
/* Disable group notification if enabled. */\r
- if(1 == AdcConfigPtr->groupConfigPtr[group].status->notifictionEnable){\r
+ if(1 == AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->notifictionEnable){\r
Adc_DisableGroupNotification (group);\r
}\r
}\r
#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)\r
void Adc_EnableGroupNotification (Adc_GroupType group)\r
{\r
- Adc_EnableInternalGroupNotification(adcState, AdcConfigPtr, group);\r
+ Adc_EnableInternalGroupNotification(adcState, Adc_GetControllerConfigPtrFromGroupId(group), group);\r
}\r
\r
void Adc_DisableGroupNotification (Adc_GroupType group)\r
{\r
- Adc_InternalDisableGroupNotification(adcState, AdcConfigPtr, group);\r
+ Adc_InternalDisableGroupNotification(adcState, Adc_GetControllerConfigPtrFromGroupId(group), group);\r
}\r
#endif\r
\r
Adc_StatusType Adc_GetGroupStatus (Adc_GroupType group)\r
{\r
- return Adc_InternalGetGroupStatus(adcState, AdcConfigPtr, group);\r
+ return Adc_InternalGetGroupStatus(adcState, Adc_GetControllerConfigPtrFromGroupId(group), group);\r
}\r
\r
}\r
\r
/* Stop all DMA channels connected to EQADC. */\r
- for (group = ADC_GROUP0; group < AdcConfigPtr->nbrOfGroups; group++)\r
+ for (group = 0; group < AdcConfigPtr->nbrOfGroups; group++)\r
{\r
Dma_StopChannel (AdcConfigPtr->groupConfigPtr [group].dmaCommandChannel);\r
Dma_StopChannel (AdcConfigPtr->groupConfigPtr [group].dmaResultChannel);\r
AdcConfigPtr = ConfigPtr;\r
\r
/* Start configuring the eQADC queues. */\r
- for (group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ for (group = 0; group < ConfigPtr->nbrOfGroups; group++)\r
{\r
/* Loop through all channels and make the command queue. */\r
for (channel = 0; channel < ConfigPtr->groupConfigPtr[group].numberOfChannels; channel++)\r
Adc_EQADCCalibrationSequence ();\r
\r
/* Configure DMA channels. */\r
- for (group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ for (group = 0; group < ConfigPtr->nbrOfGroups; group++)\r
{\r
/* ADC307. */\r
ConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
}\r
\r
/* Start DMA channels. */\r
- for (group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ for (group = 0; group < ConfigPtr->nbrOfGroups; group++)\r
{\r
/* Invalidate queues. */\r
EQADC.CFCR[group].B.CFINV = 1;\r
/* Disable time stamp timer. */\r
Adc_WriteEQADCRegister (ADC0_TSCR, 0);\r
\r
- for (group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ for (group = 0; group < ConfigPtr->nbrOfGroups; group++)\r
{\r
/* Enable eDMA requests for commands and results. */\r
EQADC.IDCR[group].B.CFFS = 1;\r
{\r
Adc_GroupType group;\r
ISR_INSTALL_ISR2( "Adc_Err", Adc_EQADCError, EQADC_FISR_OVER, 2, 0);\r
- for (group = ADC_GROUP0; group < AdcConfigPtr->nbrOfGroups; group++)\r
+ for (group = 0; group < AdcConfigPtr->nbrOfGroups; group++)\r
{\r
/* Enable end of queue, queue overflow/underflow interrupts. Clear corresponding flags. */\r
EQADC.FISR[group].B.RFOF = 1;\r
{\r
Can_Isr(CAN_CTRL_B);\r
}\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5567) || defined(CFG_MPC5668) || defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5567) || defined(CFG_MPC5668) || defined(CFG_MPC560XB)\r
void Can_C_Isr( void ) {Can_Isr(CAN_CTRL_C);}\r
void Can_D_Isr( void ) {Can_Isr(CAN_CTRL_D);}\r
void Can_E_Isr( void ) {Can_Isr(CAN_CTRL_E);}\r
#endif\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC560XB)\r
void Can_F_Isr( void ) {Can_Isr(CAN_CTRL_F);}\r
#endif\r
\r
{\r
Can_Err(CAN_CTRL_B);\r
}\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5567) || defined(CFG_MPC5668) || defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5567) || defined(CFG_MPC5668) || defined(CFG_MPC560XB)\r
void Can_C_Err( void ) {Can_Err(CAN_CTRL_C);}\r
void Can_D_Err( void ) {Can_Err(CAN_CTRL_D);}\r
void Can_E_Err( void ) {Can_Err(CAN_CTRL_E);}\r
#endif\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC560XB)\r
void Can_F_Err( void ) {Can_Err(CAN_CTRL_F);}\r
#endif\r
\r
{\r
Can_BusOff(CAN_CTRL_B);\r
}\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5567) || defined(CFG_MPC5668) || defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5567) || defined(CFG_MPC5668) || defined(CFG_MPC560XB)\r
void Can_C_BusOff( void ) {Can_BusOff(CAN_CTRL_C);}\r
void Can_D_BusOff( void ) {Can_BusOff(CAN_CTRL_D);}\r
void Can_E_BusOff( void ) {Can_BusOff(CAN_CTRL_E);}\r
#endif\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC560XB)\r
void Can_F_BusOff( void ) {Can_BusOff(CAN_CTRL_F);}\r
#endif\r
//-------------------------------------------------------------------\r
ISR_INSTALL_ISR2( "Can", Can_B_Isr, FLEXCAN_1_BUF_32_63, 2, 0 );\r
}\r
break;\r
- #if defined(CFG_MPC5604B)\r
+ #if defined(CFG_MPC560XB)\r
case CAN_CTRL_C:\r
if(cfgCtrlPtr->Can_Arc_Flags & CAN_CTRL_BUSOFF_PROCESSING_INTERRUPT){\r
ISR_INSTALL_ISR2( "Can", Can_C_BusOff, FLEXCAN_2_ESR_BOFF_INT, 2, 0);\r
canHw->BUF[mbNr].ID.B.STD_ID = pduInfo->id;\r
}\r
\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S) || defined(CFG_MPC5604B) || defined(CFG_MPC5668)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S) || defined(CFG_MPC560XB) || defined(CFG_MPC5668)\r
canHw->BUF[mbNr].ID.B.PRIO = 1; // Set Local Priority\r
#endif\r
\r
#if !defined(CFG_MPC5606S)\r
GPT_ISR( 4 )\r
GPT_ISR( 5 )\r
-#if !defined(CFG_MPC5604B)\r
+#if !defined(CFG_MPC560XB)\r
GPT_ISR( 6 )\r
GPT_ISR( 7 )\r
GPT_ISR( 8 )\r
#if defined(CFG_MPC560X)\r
#if defined(CFG_MPC5606S)\r
#define GPT_CHANNEL_PIT_LAST GPT_CHANNEL_PIT_3\r
- #elif defined(CFG_MPC5604B)\r
+ #elif defined(CFG_MPC560XB)\r
#define GPT_CHANNEL_PIT_LAST GPT_CHANNEL_PIT_5\r
#endif\r
#else\r
#if !defined(CFG_MPC5606S)\r
case 4: ISR_INSTALL_ISR2( "Gpt_4", Gpt_Isr_Channel4, PIT_INT4, 2, 0 ); break;\r
case 5: ISR_INSTALL_ISR2( "Gpt_5", Gpt_Isr_Channel5, PIT_INT5, 2, 0 ); break;\r
-#if !defined(CFG_MPC5604B)\r
+#if !defined(CFG_MPC560XB)\r
case 6: ISR_INSTALL_ISR2( "Gpt_6", Gpt_Isr_Channel6, PIT_PITFLG_PIT6, 2, 0 ); break;\r
case 7: ISR_INSTALL_ISR2( "Gpt_7", Gpt_Isr_Channel7, PIT_PITFLG_PIT7, 2, 0 ); break;\r
case 8: ISR_INSTALL_ISR2( "Gpt_8", Gpt_Isr_Channel8, PIT_PITFLG_PIT8, 2, 0 );break;\r
static void LinInterruptTxB(){LinInterruptTx(LIN_CTRL_B);}\r
static void LinInterruptErrB(){LinInterruptErr(LIN_CTRL_B);}\r
\r
-#if defined (CFG_MPC5604B)\r
+#if defined (CFG_MPC560XB)\r
static void LinInterruptRxC(){LinInterruptRx(LIN_CTRL_C);}\r
static void LinInterruptTxC(){LinInterruptTx(LIN_CTRL_C);}\r
static void LinInterruptErrC(){LinInterruptErr(LIN_CTRL_C);}\r
ISR_INSTALL_ISR2("LinIsrTxB", LinInterruptTxB, (IrqType)(LINFLEX_1_TXI),LIN_PRIO, 0);\r
ISR_INSTALL_ISR2("LinIsrErrB", LinInterruptErrB, (IrqType)(LINFLEX_1_ERR),LIN_PRIO, 0);\r
break;\r
-#if defined (CFG_MPC5604B)\r
+#if defined (CFG_MPC560XB)\r
case 2:\r
ISR_INSTALL_ISR2("LinIsrRxC", LinInterruptRxC, (IrqType)(LINFLEX_2_RXI),LIN_PRIO, 0);\r
ISR_INSTALL_ISR2("LinIsrTxC", LinInterruptTxC, (IrqType)(LINFLEX_2_TXI),LIN_PRIO, 0);\r
--- /dev/null
+/**************************************************************************** \r
+ * PROJECT : MPC5606B\r
+ * \r
+ * FILE : MPC5606BC_0.09.h\r
+ * \r
+ * DESCRIPTION : This is the header file describing the register\r
+ * set for MPC5606B\r
+ * \r
+ * COPYRIGHT :(c) 2011, Freescale \r
+ * \r
+ * VERSION : 0.09 \r
+ * DATE : 01.09.2011 \r
+ * AUTHOR : b06320\r
+ * HISTORY : Based Upon Bolero 1.5M; Version 0.06 header file\r
+ * Updated and corrected errors present on MPC5607B_2.1.h\r
+ * \r
+ * \r
+*\r
+* Example instantiation and use: \r
+* \r
+* <MODULE>.<REGISTER>.B.<BIT> = 1; \r
+* <MODULE>.<REGISTER>.R = 0x10000000;\r
+\r
+*****************************************************************************/\r
+\r
+#ifndef _JDP_H_\r
+#define _JDP_H_\r
+\r
+#include "Compiler.h"\r
+#include "typedefs.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#ifdef __MWERKS__\r
+#pragma push\r
+#pragma ANSI_strict off\r
+#endif\r
+\r
+//#define CUT2\r
+/****************************************************************************/\r
+/* MODULE : ADC0 */\r
+/****************************************************************************/\r
+#include "ip_adc_mpc56xx.h"\r
+\r
+#if 0\r
+struct ADC0_tag {\r
+\r
+ union { /* ADC0 Main Configuration Register (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t OWREN:1;\r
+ vuint32_t WLSIDE:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t:4;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t:1;\r
+ vuint32_t JTRGEN:1;\r
+ vuint32_t JEDGE:1;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:2;\r
+ vuint32_t CTUEN:1;\r
+ vuint32_t:8;\r
+ vuint32_t ADCLKSEL:1;\r
+ vuint32_t ABORTCHAIN:1;\r
+ vuint32_t ABORT:1;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:4; \r
+ vuint32_t PWDN:1; \r
+ } B;\r
+ } MCR; \r
+ \r
+ union { /* ADC0 Main Status Register (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:7;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t JABORT:1;\r
+ vuint32_t:2;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:3;\r
+ vuint32_t CTUSTART:1;\r
+ vuint32_t CHADDR:7;\r
+ vuint32_t:3;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:2; \r
+ vuint32_t ADCSTATUS:3;\r
+ } B;\r
+ } MSR; \r
+ \r
+ vuint8_t ADC0_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */\r
+ \r
+ union { /* ADC0 Interrupt Status (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t EOCTU:1;\r
+ vuint32_t JEOC:1;\r
+ vuint32_t JECH:1;\r
+ vuint32_t EOC:1;\r
+ vuint32_t ECH:1;\r
+ } B;\r
+ } ISR; \r
+ \r
+ \r
+ union { /* ADC0 Channel Pending 0 (Base+0x0014) */\r
+ vuint32_t R; /* (For precision channels) */\r
+ struct {\r
+ vuint32_t EOC_CH31:1;\r
+ vuint32_t EOC_CH30:1;\r
+ vuint32_t EOC_CH29:1;\r
+ vuint32_t EOC_CH28:1;\r
+ vuint32_t EOC_CH27:1;\r
+ vuint32_t EOC_CH26:1;\r
+ vuint32_t EOC_CH25:1;\r
+ vuint32_t EOC_CH24:1;\r
+ vuint32_t EOC_CH23:1;\r
+ vuint32_t EOC_CH22:1;\r
+ vuint32_t EOC_CH21:1;\r
+ vuint32_t EOC_CH20:1;\r
+ vuint32_t EOC_CH19:1;\r
+ vuint32_t EOC_CH18:1;\r
+ vuint32_t EOC_CH17:1;\r
+ vuint32_t EOC_CH16:1;\r
+ vuint32_t EOC_CH15:1;\r
+ vuint32_t EOC_CH14:1;\r
+ vuint32_t EOC_CH13:1;\r
+ vuint32_t EOC_CH12:1;\r
+ vuint32_t EOC_CH11:1;\r
+ vuint32_t EOC_CH10:1;\r
+ vuint32_t EOC_CH9:1;\r
+ vuint32_t EOC_CH8:1;\r
+ vuint32_t EOC_CH7:1;\r
+ vuint32_t EOC_CH6:1;\r
+ vuint32_t EOC_CH5:1;\r
+ vuint32_t EOC_CH4:1;\r
+ vuint32_t EOC_CH3:1;\r
+ vuint32_t EOC_CH2:1;\r
+ vuint32_t EOC_CH1:1;\r
+ vuint32_t EOC_CH0:1;\r
+ } B;\r
+ } CEOCFR0; \r
+ \r
+ \r
+ union { /* ADC0 Channel Pending Register 1 (Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EOC_CH63:1;\r
+ vuint32_t EOC_CH62:1;\r
+ vuint32_t EOC_CH61:1;\r
+ vuint32_t EOC_CH60:1;\r
+ vuint32_t EOC_CH59:1;\r
+ vuint32_t EOC_CH58:1;\r
+ vuint32_t EOC_CH57:1;\r
+ vuint32_t EOC_CH56:1;\r
+ vuint32_t EOC_CH55:1;\r
+ vuint32_t EOC_CH54:1;\r
+ vuint32_t EOC_CH53:1;\r
+ vuint32_t EOC_CH52:1;\r
+ vuint32_t EOC_CH51:1;\r
+ vuint32_t EOC_CH50:1;\r
+ vuint32_t EOC_CH49:1;\r
+ vuint32_t EOC_CH48:1;\r
+ vuint32_t EOC_CH47:1;\r
+ vuint32_t EOC_CH46:1;\r
+ vuint32_t EOC_CH45:1;\r
+ vuint32_t EOC_CH44:1;\r
+ vuint32_t EOC_CH43:1;\r
+ vuint32_t EOC_CH42:1;\r
+ vuint32_t EOC_CH41:1;\r
+ vuint32_t EOC_CH40:1;\r
+ vuint32_t EOC_CH39:1;\r
+ vuint32_t EOC_CH38:1;\r
+ vuint32_t EOC_CH37:1;\r
+ vuint32_t EOC_CH36:1;\r
+ vuint32_t EOC_CH35:1;\r
+ vuint32_t EOC_CH34:1;\r
+ vuint32_t EOC_CH33:1;\r
+ vuint32_t EOC_CH32:1;\r
+ } B;\r
+ } CEOCFR1; \r
+ \r
+ union { /* ADC0 Channel Pending 2 (Base+0x001C) */\r
+ vuint32_t R; /* (For external mux'd Channels) */\r
+ struct {\r
+ vuint32_t EOC_CH95:1;\r
+ vuint32_t EOC_CH94:1;\r
+ vuint32_t EOC_CH93:1;\r
+ vuint32_t EOC_CH92:1;\r
+ vuint32_t EOC_CH91:1;\r
+ vuint32_t EOC_CH90:1;\r
+ vuint32_t EOC_CH89:1;\r
+ vuint32_t EOC_CH88:1;\r
+ vuint32_t EOC_CH87:1;\r
+ vuint32_t EOC_CH86:1;\r
+ vuint32_t EOC_CH85:1;\r
+ vuint32_t EOC_CH84:1;\r
+ vuint32_t EOC_CH83:1;\r
+ vuint32_t EOC_CH82:1;\r
+ vuint32_t EOC_CH81:1;\r
+ vuint32_t EOC_CH80:1;\r
+ vuint32_t EOC_CH79:1;\r
+ vuint32_t EOC_CH78:1;\r
+ vuint32_t EOC_CH77:1;\r
+ vuint32_t EOC_CH76:1;\r
+ vuint32_t EOC_CH75:1;\r
+ vuint32_t EOC_CH74:1;\r
+ vuint32_t EOC_CH73:1;\r
+ vuint32_t EOC_CH72:1;\r
+ vuint32_t EOC_CH71:1;\r
+ vuint32_t EOC_CH70:1;\r
+ vuint32_t EOC_CH69:1;\r
+ vuint32_t EOC_CH68:1;\r
+ vuint32_t EOC_CH67:1;\r
+ vuint32_t EOC_CH66:1;\r
+ vuint32_t EOC_CH65:1;\r
+ vuint32_t EOC_CH64:1;\r
+ } B;\r
+ } CE0CFR2; \r
+ \r
+\r
+ union { /* ADC0 Interrupt Mask (Base+0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t MSKEOCTU:1;\r
+ vuint32_t MSKJEOC:1;\r
+ vuint32_t MSKJECH:1;\r
+ vuint32_t MSKEOC:1;\r
+ vuint32_t MSKECH:1; \r
+ } B;\r
+ } IMR; \r
+ \r
+\r
+\r
+ union { /* ADC0 Channel Interrupt Mask 0 (Base+0x0024) */\r
+ vuint32_t R; /* (For Precision Channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t CIM15:1;\r
+ vuint32_t CIM14:1;\r
+ vuint32_t CIM13:1;\r
+ vuint32_t CIM12:1;\r
+ vuint32_t CIM11:1;\r
+ vuint32_t CIM10:1;\r
+ vuint32_t CIM9:1;\r
+ vuint32_t CIM8:1;\r
+ vuint32_t CIM7:1;\r
+ vuint32_t CIM6:1;\r
+ vuint32_t CIM5:1;\r
+ vuint32_t CIM4:1;\r
+ vuint32_t CIM3:1;\r
+ vuint32_t CIM2:1;\r
+ vuint32_t CIM1:1;\r
+ vuint32_t CIM0:1;\r
+ } B;\r
+ } CIMR0;\r
+\r
+ union { /* ADC0 Channel Interrupt Mask 1 (+0x0028) */\r
+ vuint32_t R; /* (For Standard Channels) */ \r
+ struct {\r
+ vuint32_t CIM63:1;\r
+ vuint32_t CIM62:1;\r
+ vuint32_t CIM61:1;\r
+ vuint32_t CIM60:1;\r
+ vuint32_t CIM59:1;\r
+ vuint32_t CIM58:1;\r
+ vuint32_t CIM57:1;\r
+ vuint32_t CIM56:1;\r
+ vuint32_t CIM55:1;\r
+ vuint32_t CIM54:1;\r
+ vuint32_t CIM53:1;\r
+ vuint32_t CIM52:1;\r
+ vuint32_t CIM51:1;\r
+ vuint32_t CIM50:1;\r
+ vuint32_t CIM49:1;\r
+ vuint32_t CIM48:1;\r
+ vuint32_t CIM47:1;\r
+ vuint32_t CIM46:1;\r
+ vuint32_t CIM45:1;\r
+ vuint32_t CIM44:1;\r
+ vuint32_t CIM43:1;\r
+ vuint32_t CIM42:1;\r
+ vuint32_t CIM41:1;\r
+ vuint32_t CIM40:1;\r
+ vuint32_t CIM39:1;\r
+ vuint32_t CIM38:1;\r
+ vuint32_t CIM37:1;\r
+ vuint32_t CIM36:1;\r
+ vuint32_t CIM35:1;\r
+ vuint32_t CIM34:1;\r
+ vuint32_t CIM33:1;\r
+ vuint32_t CIM32:1;\r
+ } B;\r
+ } CIMR1;\r
+\r
+ union { /* ADC0 Channel Interrupt Mask 2 (+0x002C) */\r
+ vuint32_t R; /* (For PExternal Mux'd Channels) */ \r
+ struct {\r
+ vuint32_t CIM95:1;\r
+ vuint32_t CIM94:1;\r
+ vuint32_t CIM93:1;\r
+ vuint32_t CIM92:1;\r
+ vuint32_t CIM91:1;\r
+ vuint32_t CIM90:1;\r
+ vuint32_t CIM89:1;\r
+ vuint32_t CIM88:1;\r
+ vuint32_t CIM87:1;\r
+ vuint32_t CIM86:1;\r
+ vuint32_t CIM85:1;\r
+ vuint32_t CIM84:1;\r
+ vuint32_t CIM83:1;\r
+ vuint32_t CIM82:1;\r
+ vuint32_t CIM81:1;\r
+ vuint32_t CIM80:1;\r
+ vuint32_t CIM79:1;\r
+ vuint32_t CIM78:1;\r
+ vuint32_t CIM77:1;\r
+ vuint32_t CIM76:1;\r
+ vuint32_t CIM75:1;\r
+ vuint32_t CIM74:1;\r
+ vuint32_t CIM73:1;\r
+ vuint32_t CIM72:1;\r
+ vuint32_t CIM71:1;\r
+ vuint32_t CIM70:1;\r
+ vuint32_t CIM69:1;\r
+ vuint32_t CIM68:1;\r
+ vuint32_t CIM67:1;\r
+ vuint32_t CIM66:1;\r
+ vuint32_t CIM65:1;\r
+ vuint32_t CIM64:1;\r
+ } B;\r
+ } CIMR2; \r
+\r
+ union { /* ADC0 Watchdog Threshold Interrupt Status (+0x0030)*/\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:20;\r
+ vuint32_t WDG5H:1; \r
+ vuint32_t WDG5L:1; \r
+ vuint32_t WDG4H:1; \r
+ vuint32_t WDG4L:1; \r
+ vuint32_t WDG3H:1; \r
+ vuint32_t WDG3L:1; \r
+ vuint32_t WDG2H:1; \r
+ vuint32_t WDG2L:1; \r
+ vuint32_t WDG1H:1;\r
+ vuint32_t WDG1L:1; \r
+ vuint32_t WDG0H:1; \r
+ vuint32_t WDG0L:1; \r
+ } B; \r
+ } WTISR; \r
+ \r
+ union { /* ADC0 Watchdog Threshold Interrupt Mask (+0x0034) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:20;\r
+ vuint32_t MSKWDG5H:1; \r
+ vuint32_t MSKWDG5L:1; \r
+ vuint32_t MSKWDG4H:1; \r
+ vuint32_t MSKWDG4L:1;\r
+ vuint32_t MSKWDG3H:1; \r
+ vuint32_t MSKWDG2H:1; \r
+ vuint32_t MSKWDG1H:1; \r
+ vuint32_t MSKWDG0H:1; \r
+ vuint32_t MSKWDG3L:1; \r
+ vuint32_t MSKWDG2L:1; \r
+ vuint32_t MSKWDG1L:1; \r
+ vuint32_t MSKWDG0L:1; \r
+ } B; \r
+ } WTIMR; \r
+\r
+ vuint8_t ADC0_reserved1[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */\r
+ \r
+ union { /* ADC0 DMA Enable (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:30;\r
+ vuint32_t DCLR:1;\r
+ vuint32_t DMAEN:1;\r
+ } B;\r
+ } DMAE; \r
+ \r
+ union { /* ADC0 DMA Channel Select 0 (Base+0x0044) */\r
+ vuint32_t R; /* (for precision channels) */\r
+ struct { \r
+ vuint32_t:16;\r
+ vuint32_t DMA15:1;\r
+ vuint32_t DMA14:1;\r
+ vuint32_t DMA13:1;\r
+ vuint32_t DMA12:1;\r
+ vuint32_t DMA11:1;\r
+ vuint32_t DMA10:1;\r
+ vuint32_t DMA9:1;\r
+ vuint32_t DMA8:1;\r
+ vuint32_t DMA7:1;\r
+ vuint32_t DMA6:1;\r
+ vuint32_t DMA5:1;\r
+ vuint32_t DMA4:1;\r
+ vuint32_t DMA3:1;\r
+ vuint32_t DMA2:1;\r
+ vuint32_t DMA1:1;\r
+ vuint32_t DMA0:1;\r
+ } B;\r
+ } DMAR0; \r
+ \r
+ union { /* ADC0 DMA Channel Select 1 (Base+0x0048) */\r
+ vuint32_t R; /* (for standard channels) */ \r
+ struct {\r
+ vuint32_t DMA63:1;\r
+ vuint32_t DMA62:1;\r
+ vuint32_t DMA61:1;\r
+ vuint32_t DMA60:1;\r
+ vuint32_t DMA59:1;\r
+ vuint32_t DMA58:1;\r
+ vuint32_t DMA57:1;\r
+ vuint32_t DMA56:1;\r
+ vuint32_t DMA55:1;\r
+ vuint32_t DMA54:1;\r
+ vuint32_t DMA53:1;\r
+ vuint32_t DMA52:1;\r
+ vuint32_t DMA51:1;\r
+ vuint32_t DMA50:1;\r
+ vuint32_t DMA49:1;\r
+ vuint32_t DMA48:1;\r
+ vuint32_t DMA47:1;\r
+ vuint32_t DMA46:1;\r
+ vuint32_t DMA45:1;\r
+ vuint32_t DMA44:1;\r
+ vuint32_t DMA43:1;\r
+ vuint32_t DMA42:1;\r
+ vuint32_t DMA41:1;\r
+ vuint32_t DMA40:1;\r
+ vuint32_t DMA39:1;\r
+ vuint32_t DMA38:1;\r
+ vuint32_t DMA37:1;\r
+ vuint32_t DMA36:1;\r
+ vuint32_t DMA35:1;\r
+ vuint32_t DMA34:1;\r
+ vuint32_t DMA33:1;\r
+ vuint32_t DMA32:1;\r
+ } B;\r
+ } DMAR1;\r
+\r
+ union { /* ADC0 DMA Channel Select 2 (Base+0x004C) */\r
+ vuint32_t R; /* (for external mux'd channels) */ \r
+ struct {\r
+ vuint32_t DMA95:1;\r
+ vuint32_t DMA94:1;\r
+ vuint32_t DMA93:1;\r
+ vuint32_t DMA92:1;\r
+ vuint32_t DMA91:1;\r
+ vuint32_t DMA90:1;\r
+ vuint32_t DMA89:1;\r
+ vuint32_t DMA88:1;\r
+ vuint32_t DMA87:1;\r
+ vuint32_t DMA86:1;\r
+ vuint32_t DMA85:1;\r
+ vuint32_t DMA84:1;\r
+ vuint32_t DMA83:1;\r
+ vuint32_t DMA82:1;\r
+ vuint32_t DMA81:1;\r
+ vuint32_t DMA80:1;\r
+ vuint32_t DMA79:1;\r
+ vuint32_t DMA78:1;\r
+ vuint32_t DMA77:1;\r
+ vuint32_t DMA76:1;\r
+ vuint32_t DMA75:1;\r
+ vuint32_t DMA74:1;\r
+ vuint32_t DMA73:1;\r
+ vuint32_t DMA72:1;\r
+ vuint32_t DMA71:1;\r
+ vuint32_t DMA70:1;\r
+ vuint32_t DMA69:1;\r
+ vuint32_t DMA68:1;\r
+ vuint32_t DMA67:1;\r
+ vuint32_t DMA66:1;\r
+ vuint32_t DMA65:1;\r
+ vuint32_t DMA64:1;\r
+ } B;\r
+ } DMAR2; \r
+\r
+ vuint8_t ADC0_reserved2[16]; /* Reserved 16 bytes (Base+0x0050-0x005F) */\r
+ \r
+\r
+ /*Note the threshold registers are split [0..3] then [4..5]. For this \r
+ reason thay are NOT implemented as an array in order to maintain \r
+ concistency through all THRHLR registers */ \r
+\r
+ union { /* ADC0 Threshold 0 (Base+0x0060) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR0;\r
+\r
+ union { /* ADC0 Threshold 1 (Base+0x0064) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR1;\r
+\r
+ union { /* ADC0 Threshold 2 (Base+0x0068) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR2;\r
+\r
+ union { /* ADC0 Threshold 3 (Base+0x006C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR3; \r
+ \r
+\r
+ vuint8_t ADC0_reserved3[16]; /* Reserved 16 bytes (Base+0x0070-0x007F) */\r
+ \r
+ union { /* ADC0 Presampling Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:25;\r
+ vuint32_t PREVAL2:2;\r
+ vuint32_t PREVAL1:2;\r
+ vuint32_t PREVAL0:2;\r
+ vuint32_t PRECONV:1; \r
+ } B;\r
+ } PSCR; \r
+\r
+ \r
+ union { /* ADC0 Presampling 0 (Base+0x0084) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t PRES31:1;\r
+ vuint32_t PRES30:1;\r
+ vuint32_t PRES29:1;\r
+ vuint32_t PRES28:1;\r
+ vuint32_t PRES27:1;\r
+ vuint32_t PRES26:1;\r
+ vuint32_t PRES25:1;\r
+ vuint32_t PRES24:1;\r
+ vuint32_t PRES23:1;\r
+ vuint32_t PRES22:1;\r
+ vuint32_t PRES21:1;\r
+ vuint32_t PRES20:1;\r
+ vuint32_t PRES19:1;\r
+ vuint32_t PRES18:1;\r
+ vuint32_t PRES17:1;\r
+ vuint32_t PRES16:1;\r
+ vuint32_t PRES15:1;\r
+ vuint32_t PRES14:1;\r
+ vuint32_t PRES13:1;\r
+ vuint32_t PRES12:1;\r
+ vuint32_t PRES11:1;\r
+ vuint32_t PRES10:1;\r
+ vuint32_t PRES9:1;\r
+ vuint32_t PRES8:1;\r
+ vuint32_t PRES7:1;\r
+ vuint32_t PRES6:1;\r
+ vuint32_t PRES5:1;\r
+ vuint32_t PRES4:1;\r
+ vuint32_t PRES3:1;\r
+ vuint32_t PRES2:1;\r
+ vuint32_t PRES1:1;\r
+ vuint32_t PRES0:1;\r
+ } B;\r
+ } PSR0; \r
+ \r
+ union { /* ADC0 Presampling 1 (Base+0x0088) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t PRES63:1;\r
+ vuint32_t PRES62:1;\r
+ vuint32_t PRES61:1;\r
+ vuint32_t PRES60:1;\r
+ vuint32_t PRES59:1;\r
+ vuint32_t PRES58:1;\r
+ vuint32_t PRES57:1;\r
+ vuint32_t PRES56:1;\r
+ vuint32_t PRES55:1;\r
+ vuint32_t PRES54:1;\r
+ vuint32_t PRES53:1;\r
+ vuint32_t PRES52:1;\r
+ vuint32_t PRES51:1;\r
+ vuint32_t PRES50:1;\r
+ vuint32_t PRES49:1;\r
+ vuint32_t PRES48:1;\r
+ vuint32_t PRES47:1;\r
+ vuint32_t PRES46:1;\r
+ vuint32_t PRES45:1;\r
+ vuint32_t PRES44:1;\r
+ vuint32_t PRES43:1;\r
+ vuint32_t PRES42:1;\r
+ vuint32_t PRES41:1;\r
+ vuint32_t PRES40:1;\r
+ vuint32_t PRES39:1;\r
+ vuint32_t PRES38:1;\r
+ vuint32_t PRES37:1;\r
+ vuint32_t PRES36:1;\r
+ vuint32_t PRES35:1;\r
+ vuint32_t PRES34:1;\r
+ vuint32_t PRES33:1;\r
+ vuint32_t PRES32:1;\r
+ } B;\r
+ } PSR1;\r
+\r
+ union { /* ADC0 Presampling 2 (Base+0x008C) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t PRES95:1;\r
+ vuint32_t PRES94:1;\r
+ vuint32_t PRES93:1;\r
+ vuint32_t PRES92:1;\r
+ vuint32_t PRES91:1;\r
+ vuint32_t PRES90:1;\r
+ vuint32_t PRES89:1;\r
+ vuint32_t PRES88:1;\r
+ vuint32_t PRES87:1;\r
+ vuint32_t PRES86:1;\r
+ vuint32_t PRES85:1;\r
+ vuint32_t PRES84:1;\r
+ vuint32_t PRES83:1;\r
+ vuint32_t PRES82:1;\r
+ vuint32_t PRES81:1;\r
+ vuint32_t PRES80:1;\r
+ vuint32_t PRES79:1;\r
+ vuint32_t PRES78:1;\r
+ vuint32_t PRES77:1;\r
+ vuint32_t PRES76:1;\r
+ vuint32_t PRES75:1;\r
+ vuint32_t PRES74:1;\r
+ vuint32_t PRES73:1;\r
+ vuint32_t PRES72:1;\r
+ vuint32_t PRES71:1;\r
+ vuint32_t PRES70:1;\r
+ vuint32_t PRES69:1;\r
+ vuint32_t PRES68:1;\r
+ vuint32_t PRES67:1;\r
+ vuint32_t PRES66:1;\r
+ vuint32_t PRES65:1;\r
+ vuint32_t PRES64:1;\r
+ } B;\r
+ } PSR2; \r
+\r
+ vuint8_t ADC0_reserved4[4]; /* Reserved 4 bytes (Base+0x0090-0x0093) */\r
+ \r
+ \r
+\r
+ /* Note the following CTR registers are NOT implemented as an array to */\r
+ /* try and maintain some concistency through the header file */\r
+ /* (The registers are however identical) */\r
+\r
+ union { /* ADC0 Conversion Timing 0 (Base+0x0094) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR0;\r
+\r
+ union { /* ADC0 Conversion Timing 1 (Base+0x0098) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR1;\r
+\r
+ union { /* ADC0 Conversion Timing 2 (Base+0x009C) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR2; \r
+\r
+ vuint8_t ADC0_reserved5[4]; /* Reserved 4 bytes (Base+0x00A0-0x00A3) */\r
+ \r
+\r
+union { /* ADC0 Normal Conversion Mask 0 (Base+0x00A4) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } NCMR0;\r
+\r
+ union { /* ADC0 Normal Conversion Mask 1 (Base+0x00A8) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CH59:1;\r
+ vuint32_t CH58:1;\r
+ vuint32_t CH57:1;\r
+ vuint32_t CH56:1;\r
+ vuint32_t CH55:1;\r
+ vuint32_t CH54:1;\r
+ vuint32_t CH53:1;\r
+ vuint32_t CH52:1;\r
+ vuint32_t CH51:1;\r
+ vuint32_t CH50:1;\r
+ vuint32_t CH49:1;\r
+ vuint32_t CH48:1;\r
+ vuint32_t CH47:1;\r
+ vuint32_t CH46:1;\r
+ vuint32_t CH45:1;\r
+ vuint32_t CH44:1;\r
+ vuint32_t CH43:1;\r
+ vuint32_t CH42:1;\r
+ vuint32_t CH41:1;\r
+ vuint32_t CH40:1;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } NCMR1;\r
+\r
+ union { /* ADC0 Normal Conversion Mask 2 (Base+0x00AC) */\r
+ vuint32_t R; /* (For external mux'd channels) */ \r
+ struct {\r
+ vuint32_t CH95:1;\r
+ vuint32_t CH94:1;\r
+ vuint32_t CH93:1;\r
+ vuint32_t CH92:1;\r
+ vuint32_t CH91:1;\r
+ vuint32_t CH90:1;\r
+ vuint32_t CH89:1;\r
+ vuint32_t CH88:1;\r
+ vuint32_t CH87:1;\r
+ vuint32_t CH86:1;\r
+ vuint32_t CH85:1;\r
+ vuint32_t CH84:1;\r
+ vuint32_t CH83:1;\r
+ vuint32_t CH82:1;\r
+ vuint32_t CH81:1;\r
+ vuint32_t CH80:1;\r
+ vuint32_t CH79:1;\r
+ vuint32_t CH78:1;\r
+ vuint32_t CH77:1;\r
+ vuint32_t CH76:1;\r
+ vuint32_t CH75:1;\r
+ vuint32_t CH74:1;\r
+ vuint32_t CH73:1;\r
+ vuint32_t CH72:1;\r
+ vuint32_t CH71:1;\r
+ vuint32_t CH70:1;\r
+ vuint32_t CH69:1;\r
+ vuint32_t CH68:1;\r
+ vuint32_t CH67:1;\r
+ vuint32_t CH66:1;\r
+ vuint32_t CH65:1;\r
+ vuint32_t CH64:1;\r
+ } B;\r
+ } NCMR2; \r
+\r
+vuint8_t ADC0_reserved6[4]; /* Reserved 4 bytes (Base+0x00B0-0x00B3) */\r
+\r
+ \r
+ union { /* ADC0 Injected Conversion Mask0 (Base+0x00B4) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } JCMR0;\r
+\r
+ union { /* ADC0 Injected Conversion Mask1 (Base+0x00B8) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CH59:1;\r
+ vuint32_t CH58:1;\r
+ vuint32_t CH57:1;\r
+ vuint32_t CH56:1;\r
+ vuint32_t CH55:1;\r
+ vuint32_t CH54:1;\r
+ vuint32_t CH53:1;\r
+ vuint32_t CH52:1;\r
+ vuint32_t CH51:1;\r
+ vuint32_t CH50:1;\r
+ vuint32_t CH49:1;\r
+ vuint32_t CH48:1;\r
+ vuint32_t CH47:1;\r
+ vuint32_t CH46:1;\r
+ vuint32_t CH45:1;\r
+ vuint32_t CH44:1;\r
+ vuint32_t CH43:1;\r
+ vuint32_t CH42:1;\r
+ vuint32_t CH41:1;\r
+ vuint32_t CH40:1;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } JCMR1;\r
+\r
+ union { /* ADC0 Injected Conversion Mask2 (Base+0x00BC) */\r
+ vuint32_t R; /* (external mux'd channels) */ \r
+ struct {\r
+ vuint32_t CH95:1;\r
+ vuint32_t CH94:1;\r
+ vuint32_t CH93:1;\r
+ vuint32_t CH92:1;\r
+ vuint32_t CH91:1;\r
+ vuint32_t CH90:1;\r
+ vuint32_t CH89:1;\r
+ vuint32_t CH88:1;\r
+ vuint32_t CH87:1;\r
+ vuint32_t CH86:1;\r
+ vuint32_t CH85:1;\r
+ vuint32_t CH84:1;\r
+ vuint32_t CH83:1;\r
+ vuint32_t CH82:1;\r
+ vuint32_t CH81:1;\r
+ vuint32_t CH80:1;\r
+ vuint32_t CH79:1;\r
+ vuint32_t CH78:1;\r
+ vuint32_t CH77:1;\r
+ vuint32_t CH76:1;\r
+ vuint32_t CH75:1;\r
+ vuint32_t CH74:1;\r
+ vuint32_t CH73:1;\r
+ vuint32_t CH72:1;\r
+ vuint32_t CH71:1;\r
+ vuint32_t CH70:1;\r
+ vuint32_t CH69:1;\r
+ vuint32_t CH68:1;\r
+ vuint32_t CH67:1;\r
+ vuint32_t CH66:1;\r
+ vuint32_t CH65:1;\r
+ vuint32_t CH64:1;\r
+ } B;\r
+ } JCMR2;\r
+ \r
+ \r
+ vuint8_t ADC0_reserved7[4]; /* Reserved 4 bytes (Base+0x00C0-0x00C3) */\r
+ \r
+ union { /* ADC0 Decode Signals Delay (Base+0x00C4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t DSD:12;\r
+ } B;\r
+ } DSDR; \r
+ \r
+ union { /* ADC0 Power-Down exit Delay (Base+0x00C8) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t PDED:8;\r
+ } B;\r
+ } PDEDR; \r
+\r
+ \r
+ vuint8_t ADC0_reserved8[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */\r
+ \r
+ union { /* ADC0 Channel 0-95 Data (Base+0x0100-0x027C) */\r
+ vuint32_t R; /* Note CDR[16..31] and CDR[60..63] are reserved */\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t VALID:1;\r
+ vuint32_t OVERW:1;\r
+ vuint32_t RESULT:2;\r
+ vuint32_t:6;\r
+ vuint32_t CDATA:10;\r
+ } B;\r
+ } CDR[96]; \r
+ \r
+ union { /* ADC0 Threshold 4 (Base+0x0280) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR4;\r
+\r
+ union { /* ADC0 Threshold 5 (Base+0x0284) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR5;\r
+ \r
+ vuint8_t ADC0_reserved9[40]; /* Reserved 40 bytes (Base+0x0288-0x02AF) */\r
+ \r
+ \r
+ union { /* ADC0 Channel Watchdog Select 0 (Base+0x02B0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH7:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH6:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH5:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH4:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH3:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH2:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH1:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH0:3;\r
+ } B;\r
+ } CWSELR0; \r
+ \r
+ union { /* ADC0 Channel Watchdog Select 1 (Base+0x02B4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH15:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH14:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH13:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH12:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH11:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH10:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH9:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH8:3;\r
+ } B;\r
+ } CWSELR1; \r
+ \r
+ vuint8_t ADC0_reserved10[8]; /* Reserved 4 bytes (Base+0x02B8-0x02BF) */ \r
+ \r
+ union { /* ADC0 Channel Watchdog Select 4 (Base+0x02C0) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH39:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH38:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH37:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH36:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH35:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH34:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH33:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH32:3;\r
+ } B;\r
+ } CWSELR4;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 5 (Base+0x02C4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH47:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH46:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH45:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH44:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH43:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH42:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH41:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH40:3;\r
+ } B;\r
+ } CWSELR5;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 6 (Base+0x02C8) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH55:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH54:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH53:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH52:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH51:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH50:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH49:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH48:3;\r
+ } B;\r
+ } CWSELR6;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 7 (Base+0x02CC) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH63:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH62:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH61:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH60:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH59:3;\r
+ vuint32_t:12;\r
+ } B;\r
+ } CWSELR7;\r
+ \r
+ union { /* ADC0 Channel Watchdog Select 8 (Base+0x02D0) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH71:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH70:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH69:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH68:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH67:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH66:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH65:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH64:3;\r
+ } B;\r
+ } CWSELR8;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 9 (Base+0x02D4) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH79:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH78:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH77:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH76:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH75:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH74:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH73:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH72:3;\r
+ } B;\r
+ } CWSELR9;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 10 (Base+0x02D8)*/\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH87:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH86:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH85:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH84:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH83:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH82:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH81:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH80:3;\r
+ } B;\r
+ } CWSELR10;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 11 (Base+0x02DC)*/\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH95:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH94:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH93:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH92:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH91:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH90:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH89:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH88:3;\r
+ } B;\r
+ } CWSELR11;\r
+ \r
+ union { /* ADC0 Channel Watchdog Enable0 (Base++0x02E0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CWEN15:1;\r
+ vuint32_t CWEN14:1;\r
+ vuint32_t CWEN13:1;\r
+ vuint32_t CWEN12:1;\r
+ vuint32_t CWEN11:1;\r
+ vuint32_t CWEN10:1;\r
+ vuint32_t CWEN9:1;\r
+ vuint32_t CWEN8:1;\r
+ vuint32_t CWEN7:1;\r
+ vuint32_t CWEN6:1;\r
+ vuint32_t CWEN5:1;\r
+ vuint32_t CWEN4:1;\r
+ vuint32_t CWEN3:1;\r
+ vuint32_t CWEN2:1;\r
+ vuint32_t CWEN1:1;\r
+ vuint32_t CWEN0:1;\r
+ } B;\r
+ } CWENR0;\r
+\r
+ union { /* ADC0 Channel Watchdog Enable1 (Base++0x02E4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CWEN59:1;\r
+ vuint32_t CWEN58:1;\r
+ vuint32_t CWEN57:1;\r
+ vuint32_t CWEN56:1;\r
+ vuint32_t CWEN55:1;\r
+ vuint32_t CWEN54:1;\r
+ vuint32_t CWEN53:1;\r
+ vuint32_t CWEN52:1;\r
+ vuint32_t CWEN51:1;\r
+ vuint32_t CWEN50:1;\r
+ vuint32_t CWEN49:1;\r
+ vuint32_t CWEN48:1;\r
+ vuint32_t CWEN47:1;\r
+ vuint32_t CWEN46:1;\r
+ vuint32_t CWEN45:1;\r
+ vuint32_t CWEN44:1;\r
+ vuint32_t CWEN43:1;\r
+ vuint32_t CWEN42:1;\r
+ vuint32_t CWEN41:1;\r
+ vuint32_t CWEN40:1;\r
+ vuint32_t CWEN39:1;\r
+ vuint32_t CWEN38:1;\r
+ vuint32_t CWEN37:1;\r
+ vuint32_t CWEN36:1;\r
+ vuint32_t CWEN35:1;\r
+ vuint32_t CWEN34:1;\r
+ vuint32_t CWEN33:1;\r
+ vuint32_t CWEN32:1;\r
+ } B;\r
+ } CWENR1;\r
+\r
+ union { /* ADC0 Channel Watchdog Enable2 (Base++0x02E8) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t CWEN95:1;\r
+ vuint32_t CWEN94:1;\r
+ vuint32_t CWEN93:1;\r
+ vuint32_t CWEN92:1;\r
+ vuint32_t CWEN91:1;\r
+ vuint32_t CWEN90:1;\r
+ vuint32_t CWEN89:1;\r
+ vuint32_t CWEN88:1;\r
+ vuint32_t CWEN87:1;\r
+ vuint32_t CWEN86:1;\r
+ vuint32_t CWEN85:1;\r
+ vuint32_t CWEN84:1;\r
+ vuint32_t CWEN83:1;\r
+ vuint32_t CWEN82:1;\r
+ vuint32_t CWEN81:1;\r
+ vuint32_t CWEN80:1;\r
+ vuint32_t CWEN79:1;\r
+ vuint32_t CWEN78:1;\r
+ vuint32_t CWEN77:1;\r
+ vuint32_t CWEN76:1;\r
+ vuint32_t CWEN75:1;\r
+ vuint32_t CWEN74:1;\r
+ vuint32_t CWEN73:1;\r
+ vuint32_t CWEN72:1;\r
+ vuint32_t CWEN71:1;\r
+ vuint32_t CWEN70:1;\r
+ vuint32_t CWEN69:1;\r
+ vuint32_t CWEN68:1;\r
+ vuint32_t CWEN67:1;\r
+ vuint32_t CWEN66:1;\r
+ vuint32_t CWEN65:1;\r
+ vuint32_t CWEN64:1;\r
+ } B;\r
+ } CWENR2;\r
+\r
+ vuint8_t ADC0_reserved11[4]; /* Reserved 4 bytes (Base+0x02EC-0x02EF) */\r
+ \r
+union { /* ADC0 Watchdog out of range 0 (Base+0x02F0) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t AWORR_CH15:1;\r
+ vuint32_t AWORR_CH14:1;\r
+ vuint32_t AWORR_CH13:1;\r
+ vuint32_t AWORR_CH12:1;\r
+ vuint32_t AWORR_CH11:1;\r
+ vuint32_t AWORR_CH10:1;\r
+ vuint32_t AWORR_CH9:1;\r
+ vuint32_t AWORR_CH8:1;\r
+ vuint32_t AWORR_CH7:1;\r
+ vuint32_t AWORR_CH6:1;\r
+ vuint32_t AWORR_CH5:1;\r
+ vuint32_t AWORR_CH4:1;\r
+ vuint32_t AWORR_CH3:1;\r
+ vuint32_t AWORR_CH2:1;\r
+ vuint32_t AWORR_CH1:1;\r
+ vuint32_t AWORR_CH0:1;\r
+ } B;\r
+ } AWORR0;\r
+\r
+ union { /* ADC0 Watchdog out of range 1 (Base+0x02F4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t AWORR_CH59:1;\r
+ vuint32_t AWORR_CH58:1;\r
+ vuint32_t AWORR_CH57:1;\r
+ vuint32_t AWORR_CH56:1;\r
+ vuint32_t AWORR_CH55:1;\r
+ vuint32_t AWORR_CH54:1;\r
+ vuint32_t AWORR_CH53:1;\r
+ vuint32_t AWORR_CH52:1;\r
+ vuint32_t AWORR_CH51:1;\r
+ vuint32_t AWORR_CH50:1;\r
+ vuint32_t AWORR_CH49:1;\r
+ vuint32_t AWORR_CH48:1;\r
+ vuint32_t AWORR_CH47:1;\r
+ vuint32_t AWORR_CH46:1;\r
+ vuint32_t AWORR_CH45:1;\r
+ vuint32_t AWORR_CH44:1;\r
+ vuint32_t AWORR_CH43:1;\r
+ vuint32_t AWORR_CH42:1;\r
+ vuint32_t AWORR_CH41:1;\r
+ vuint32_t AWORR_CH40:1;\r
+ vuint32_t AWORR_CH39:1;\r
+ vuint32_t AWORR_CH38:1;\r
+ vuint32_t AWORR_CH37:1;\r
+ vuint32_t AWORR_CH36:1;\r
+ vuint32_t AWORR_CH35:1;\r
+ vuint32_t AWORR_CH34:1;\r
+ vuint32_t AWORR_CH33:1;\r
+ vuint32_t AWORR_CH32:1;\r
+ } B;\r
+ } AWORR1;\r
+\r
+ union { /* ADC0 Watchdog out of range 2 (Base+0x02F8) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t AWORR_CH95:1;\r
+ vuint32_t AWORR_CH94:1;\r
+ vuint32_t AWORR_CH93:1;\r
+ vuint32_t AWORR_CH92:1;\r
+ vuint32_t AWORR_CH91:1;\r
+ vuint32_t AWORR_CH90:1;\r
+ vuint32_t AWORR_CH89:1;\r
+ vuint32_t AWORR_CH88:1;\r
+ vuint32_t AWORR_CH87:1;\r
+ vuint32_t AWORR_CH86:1;\r
+ vuint32_t AWORR_CH85:1;\r
+ vuint32_t AWORR_CH84:1;\r
+ vuint32_t AWORR_CH83:1;\r
+ vuint32_t AWORR_CH82:1;\r
+ vuint32_t AWORR_CH81:1;\r
+ vuint32_t AWORR_CH80:1;\r
+ vuint32_t AWORR_CH79:1;\r
+ vuint32_t AWORR_CH78:1;\r
+ vuint32_t AWORR_CH77:1;\r
+ vuint32_t AWORR_CH76:1;\r
+ vuint32_t AWORR_CH75:1;\r
+ vuint32_t AWORR_CH74:1;\r
+ vuint32_t AWORR_CH73:1;\r
+ vuint32_t AWORR_CH72:1;\r
+ vuint32_t AWORR_CH71:1;\r
+ vuint32_t AWORR_CH70:1;\r
+ vuint32_t AWORR_CH69:1;\r
+ vuint32_t AWORR_CH68:1;\r
+ vuint32_t AWORR_CH67:1;\r
+ vuint32_t AWORR_CH66:1;\r
+ vuint32_t AWORR_CH65:1;\r
+ vuint32_t AWORR_CH64:1;\r
+ } B;\r
+ } AWORR2;\r
+\r
+ //vuint8_t ADC0_reserved12[15620]; /* Reserved 15620 bytes (Base+0x02FC-0x3FFF) */ \r
+ \r
+}; /* end of ADC0_tag */ \r
+\r
+/****************************************************************************/\r
+/* MODULE : ADC1 (12 Bit) */\r
+/****************************************************************************/\r
+struct ADC1_tag {\r
+\r
+ union { /* ADC1 Main Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OWREN:1;\r
+ vuint32_t WLSIDE:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t:4;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t:1;\r
+ vuint32_t JTRGEN:1;\r
+ vuint32_t JEDGE:1;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:2;\r
+ vuint32_t CTUEN:1;\r
+ vuint32_t:8;\r
+ vuint32_t ADCLKSEL:1;\r
+ vuint32_t ABORT_CHAIN:1;\r
+ vuint32_t ABORT:1;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:2;\r
+ vuint32_t:2;\r
+ vuint32_t PWDN:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* ADC1 Main Status (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:7;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t JABORT:1;\r
+ vuint32_t:2;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:3;\r
+ vuint32_t CTUSTART:1;\r
+ vuint32_t CHADDR:7;\r
+ vuint32_t:3;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:2;\r
+ vuint32_t ADCSTATUS:3;\r
+ } B;\r
+ } MSR;\r
+\r
+ vuint8_t ADC1_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */\r
+\r
+ union { /* ADC1 Interrupt Status (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t EOCTU:1;\r
+ vuint32_t JEOC:1;\r
+ vuint32_t JECH:1;\r
+ vuint32_t EOC:1;\r
+ vuint32_t ECH:1;\r
+ } B;\r
+ } ISR;\r
+\r
+ union { /* ADC1 Channel Pending 0 (Base+0x0014) */\r
+ vuint32_t R; /* (For precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t EOC_CH15:1;\r
+ vuint32_t EOC_CH14:1;\r
+ vuint32_t EOC_CH13:1;\r
+ vuint32_t EOC_CH12:1;\r
+ vuint32_t EOC_CH11:1;\r
+ vuint32_t EOC_CH10:1;\r
+ vuint32_t EOC_CH9:1;\r
+ vuint32_t EOC_CH8:1;\r
+ vuint32_t EOC_CH7:1;\r
+ vuint32_t EOC_CH6:1;\r
+ vuint32_t EOC_CH5:1;\r
+ vuint32_t EOC_CH4:1;\r
+ vuint32_t EOC_CH3:1;\r
+ vuint32_t EOC_CH2:1;\r
+ vuint32_t EOC_CH1:1;\r
+ vuint32_t EOC_CH0:1;\r
+ } B;\r
+ } CE0CFR0;\r
+\r
+ union { /* ADC1 Channel Pending 1 (Base+0x0018) */\r
+ vuint32_t R; /* (For standard Channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t EOC_CH39:1;\r
+ vuint32_t EOC_CH38:1;\r
+ vuint32_t EOC_CH37:1;\r
+ vuint32_t EOC_CH36:1;\r
+ vuint32_t EOC_CH35:1;\r
+ vuint32_t EOC_CH34:1;\r
+ vuint32_t EOC_CH33:1;\r
+ vuint32_t EOC_CH32:1;\r
+ } B;\r
+ } CE0CFR1;\r
+\r
+ vuint8_t ADC1_reserved1[4]; /* Reserved 4 bytes (Base+0x001C-0x001F) */\r
+\r
+ union { /* ADC1 Interrupt Mask (Base+0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t MSKEOCTU:1;\r
+ vuint32_t MSKJEOC:1;\r
+ vuint32_t MSKJECH:1;\r
+ vuint32_t MSKEOC:1;\r
+ vuint32_t MSKECH:1;\r
+ } B;\r
+ } IMR;\r
+\r
+ union { /* ADC1 Channel Interrupt Mask 0 (Base+0x0024) */\r
+ vuint32_t R; /* (For Precision Channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t CIM15:1;\r
+ vuint32_t CIM14:1;\r
+ vuint32_t CIM13:1;\r
+ vuint32_t CIM12:1;\r
+ vuint32_t CIM11:1;\r
+ vuint32_t CIM10:1;\r
+ vuint32_t CIM9:1;\r
+ vuint32_t CIM8:1;\r
+ vuint32_t CIM7:1;\r
+ vuint32_t CIM6:1;\r
+ vuint32_t CIM5:1;\r
+ vuint32_t CIM4:1;\r
+ vuint32_t CIM3:1;\r
+ vuint32_t CIM2:1;\r
+ vuint32_t CIM1:1;\r
+ vuint32_t CIM0:1;\r
+ } B;\r
+ } CIMR0;\r
+\r
+ union { /* ADC1 Channel Interrupt Mask 1 (+0x0028) */\r
+ vuint32_t R; /* (For Standard Channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CIM39:1;\r
+ vuint32_t CIM38:1;\r
+ vuint32_t CIM37:1;\r
+ vuint32_t CIM36:1;\r
+ vuint32_t CIM35:1;\r
+ vuint32_t CIM34:1;\r
+ vuint32_t CIM33:1;\r
+ vuint32_t CIM32:1;\r
+ } B;\r
+ } CIMR1;\r
+\r
+ vuint8_t ADC1_reserved2[4]; /* Reserved 4 bytes (Base+0x002C-0x002F) */\r
+\r
+ union { /* ADC1 Watchdog Threshold Interrupt Status (+0x0030)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t WDG2H:1;\r
+ vuint32_t WDG2L:1;\r
+ vuint32_t WDG1H:1;\r
+ vuint32_t WDG1L:1;\r
+ vuint32_t WDG0H:1;\r
+ vuint32_t WDG0L:1;\r
+ } B;\r
+ } WTISR;\r
+\r
+ union { /* ADC1 Watchdog Threshold Interrupt Mask (+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t MSKWDG2H:1;\r
+ vuint32_t MSKWDG2L:1;\r
+ vuint32_t MSKWDG1H:1;\r
+ vuint32_t MSKWDG1L:1;\r
+ vuint32_t MSKWDG0H:1;\r
+ vuint32_t MSKWDG0L:1;\r
+ } B;\r
+ } WTIMR;\r
+\r
+ vuint8_t ADC1_reserved3[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */\r
+\r
+ union { /* ADC1 DMA Enable (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t DCLR:1;\r
+ vuint32_t DMAEN:1;\r
+ } B;\r
+ } DMAE;\r
+\r
+ union { /* ADC1 DMA Channel Select 0 (Base+0x0044) */\r
+ vuint32_t R; /* (for precision channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DMA15:1;\r
+ vuint32_t DMA14:1;\r
+ vuint32_t DMA13:1;\r
+ vuint32_t DMA12:1;\r
+ vuint32_t DMA11:1;\r
+ vuint32_t DMA10:1;\r
+ vuint32_t DMA9:1;\r
+ vuint32_t DMA8:1;\r
+ vuint32_t DMA7:1;\r
+ vuint32_t DMA6:1;\r
+ vuint32_t DMA5:1;\r
+ vuint32_t DMA4:1;\r
+ vuint32_t DMA3:1;\r
+ vuint32_t DMA2:1;\r
+ vuint32_t DMA1:1;\r
+ vuint32_t DMA0:1;\r
+ } B;\r
+ } DMAR0;\r
+\r
+ union { /* ADC1 DMA Channel Select 1 (Base+0x0048) */\r
+ vuint32_t R; /* (for standard channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t DMA39:1;\r
+ vuint32_t DMA38:1;\r
+ vuint32_t DMA37:1;\r
+ vuint32_t DMA36:1;\r
+ vuint32_t DMA35:1;\r
+ vuint32_t DMA34:1;\r
+ vuint32_t DMA33:1;\r
+ vuint32_t DMA32:1;\r
+ } B;\r
+ } DMAR1;\r
+\r
+ vuint8_t ADC1_reserved4[20]; /* Reserved 20 bytes (Base+0x004C-0x005F) */\r
+\r
+ /* Note the threshold registers are not implemented as an array for */\r
+ /* concistency with ADC0 header section */\r
+\r
+ union { /* ADC1 Threshold 0 (Base+0x0060) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t THRH:12;\r
+ vuint32_t:4;\r
+ vuint32_t THRL:12;\r
+ } B;\r
+ } THRHLR0;\r
+\r
+ union { /* ADC1 Threshold 1 (Base+0x0064) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t THRH:12;\r
+ vuint32_t:4;\r
+ vuint32_t THRL:12;\r
+ } B;\r
+ } THRHLR1;\r
+\r
+ union { /* ADC1 Threshold 2 (Base+0x0068) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t THRH:12;\r
+ vuint32_t:4;\r
+ vuint32_t THRL:12;\r
+ } B;\r
+ } THRHLR2;\r
+\r
+ vuint8_t ADC1_reserved5[20]; /* Reserved 20 bytes (Base+0x006C-0x007F) */\r
+\r
+ union { /* ADC1 Presampling Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:25;\r
+ vuint32_t PREVAL2:2;\r
+ vuint32_t PREVAL1:2;\r
+ vuint32_t PREVAL0:2;\r
+ vuint32_t PRECONV:1;\r
+ } B;\r
+ } PSCR;\r
+\r
+ union { /* ADC1 Presampling 0 (Base+0x0084) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t PRES15:1;\r
+ vuint32_t PRES14:1;\r
+ vuint32_t PRES13:1;\r
+ vuint32_t PRES12:1;\r
+ vuint32_t PRES11:1;\r
+ vuint32_t PRES10:1;\r
+ vuint32_t PRES9:1;\r
+ vuint32_t PRES8:1;\r
+ vuint32_t PRES7:1;\r
+ vuint32_t PRES6:1;\r
+ vuint32_t PRES5:1;\r
+ vuint32_t PRES4:1;\r
+ vuint32_t PRES3:1;\r
+ vuint32_t PRES2:1;\r
+ vuint32_t PRES1:1;\r
+ vuint32_t PRES0:1;\r
+ } B;\r
+ } PSR0;\r
+\r
+ union { /* ADC1 Presampling 1 (Base+0x0088) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t PRES39:1;\r
+ vuint32_t PRES38:1;\r
+ vuint32_t PRES37:1;\r
+ vuint32_t PRES36:1;\r
+ vuint32_t PRES35:1;\r
+ vuint32_t PRES34:1;\r
+ vuint32_t PRES33:1;\r
+ vuint32_t PRES32:1;\r
+ } B;\r
+ } PSR1;\r
+\r
+ vuint8_t ADC1_reserved6[8]; /* Reserved 8 bytes (Base+0x008C-0x0093) */\r
+\r
+ /* Note the following CTR registers are NOT implemented as an array to */\r
+ /* try and maintain some concistency through the header file */\r
+ /* (The registers are however identical) */\r
+\r
+ union { /* ADC1 Conversion Timing 0 (Base+0x0094) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR0;\r
+\r
+ union { /* ADC1 Conversion Timing 1 (Base+0x0098) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR1;\r
+\r
+ vuint8_t ADC1_reserved7[8]; /* Reserved 8 bytes (Base+0x009C-0x00A3) */\r
+\r
+ union { /* ADC1 Normal Conversion Mask 0 (Base+0x00A4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } NCMR0;\r
+\r
+ union { /* ADC1 Normal Conversion Mask 1 (Base+0x00A8) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } NCMR1;\r
+\r
+ vuint8_t ADC1_reserved8[8]; /* Reserved 8 bytes (Base+0x00AC-0x00B3) */\r
+\r
+ union { /* ADC1 Injected Conversion Mask0 (Base+0x00B4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } JCMR0;\r
+\r
+ union { /* ADC1 Injected Conversion Mask1 (Base+0x00B8) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } JCMR1;\r
+\r
+ vuint8_t ADC1_reserved9[12]; /* Reserved 12 bytes (Base+0x00BC-0x00C7) */\r
+ \r
+ union { /* Power Down Exit Delay Register (base+0x00C8)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24; \r
+ vuint32_t PDED:8;\r
+ } B;\r
+ } PDEDR; \r
+\r
+ vuint8_t ADC1_reserved10[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */ \r
+\r
+ union { /* ADC1 Channel 0-39 Data (Base+0x0100-0x019C) */\r
+ vuint32_t R; /* Note CDR[16..31] are reserved 0x0140-0x017F */\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t VALID:1;\r
+ vuint32_t OVERW:1;\r
+ vuint32_t RESULT:2;\r
+ vuint32_t:4;\r
+ vuint32_t CDATA:12;\r
+ } B;\r
+ } CDR[40];\r
+\r
+ vuint8_t ADC1_reserved11[272]; /* Reserved 252 bytes (Base+0x01A0-0x002AF) */\r
+\r
+ union { /* ADC1 Channel Watchdog Select 0 (Base+0x02B0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH7:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH6:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH5:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH4:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH3:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH2:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH1:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH0:2;\r
+ } B;\r
+ } CWSELR0;\r
+\r
+ union { /* ADC1 Channel Watchdog Select 1 (Base+0x02B4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH15:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH14:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH13:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH12:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH11:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH10:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH9:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH8:2;\r
+ } B;\r
+ } CWSELR1;\r
+\r
+ vuint8_t ADC1_reserved12[8]; /* Reserved 8 bytes (Base+0x02B8-0x02BF) */\r
+\r
+ union { /* ADC1 Channel Watchdog Select 4 (Base+0x02C0) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH39:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH38:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH37:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH36:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH35:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH34:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH33:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH32:2;\r
+ } B;\r
+ } CWSELR4;\r
+\r
+ union { /* ADC1 Channel Watchdog Select 5 (Base+0x02C4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t WSEL_CH44:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH43:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH42:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH41:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH40:2;\r
+ } B;\r
+ } CWSELR5;\r
+\r
+ vuint8_t ADC1_reserved13[24]; /* Reserved 24 bytes (Base+0x02C8-0x02DF) */\r
+\r
+ union { /* ADC1 Channel Watchdog Enable0 (Base+0x02E0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CWEN15:1;\r
+ vuint32_t CWEN14:1;\r
+ vuint32_t CWEN13:1;\r
+ vuint32_t CWEN12:1;\r
+ vuint32_t CWEN11:1;\r
+ vuint32_t CWEN10:1;\r
+ vuint32_t CWEN9:1;\r
+ vuint32_t CWEN8:1;\r
+ vuint32_t CWEN7:1;\r
+ vuint32_t CWEN6:1;\r
+ vuint32_t CWEN5:1;\r
+ vuint32_t CWEN4:1;\r
+ vuint32_t CWEN3:1;\r
+ vuint32_t CWEN2:1;\r
+ vuint32_t CWEN1:1;\r
+ vuint32_t CWEN0:1;\r
+ } B;\r
+ } CWENR0;\r
+\r
+ union { /* ADC1 Channel Watchdog Enable1 (Base++0x02E4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t CWEN39:1;\r
+ vuint32_t CWEN38:1;\r
+ vuint32_t CWEN37:1;\r
+ vuint32_t CWEN36:1;\r
+ vuint32_t CWEN35:1;\r
+ vuint32_t CWEN34:1;\r
+ vuint32_t CWEN33:1;\r
+ vuint32_t CWEN32:1;\r
+ } B;\r
+ } CWENR1;\r
+\r
+ vuint8_t ADC1_reserved14[8]; /* Reserved 8 bytes (Base+0x02E8-0x02EF) */\r
+\r
+ union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t AWORR_CH15:1;\r
+ vuint32_t AWORR_CH14:1;\r
+ vuint32_t AWORR_CH13:1;\r
+ vuint32_t AWORR_CH12:1;\r
+ vuint32_t AWORR_CH11:1;\r
+ vuint32_t AWORR_CH10:1;\r
+ vuint32_t AWORR_CH9:1;\r
+ vuint32_t AWORR_CH8:1;\r
+ vuint32_t AWORR_CH7:1;\r
+ vuint32_t AWORR_CH6:1;\r
+ vuint32_t AWORR_CH5:1;\r
+ vuint32_t AWORR_CH4:1;\r
+ vuint32_t AWORR_CH3:1;\r
+ vuint32_t AWORR_CH2:1;\r
+ vuint32_t AWORR_CH1:1;\r
+ vuint32_t AWORR_CH0:1;\r
+ } B;\r
+ } AWORR0;\r
+\r
+ union { /* ADC1 Watchdog out of range 1 (Base+0x02F4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t AWORR_CH39:1;\r
+ vuint32_t AWORR_CH38:1;\r
+ vuint32_t AWORR_CH37:1;\r
+ vuint32_t AWORR_CH36:1;\r
+ vuint32_t AWORR_CH35:1;\r
+ vuint32_t AWORR_CH34:1;\r
+ vuint32_t AWORR_CH33:1;\r
+ vuint32_t AWORR_CH32:1;\r
+ } B;\r
+ } AWORR1;\r
+\r
+ vuint8_t ADC1_reserved15[8]; /* Reserved 8 bytes (Base+0x02F8-0x02FF) */\r
+\r
+}; /* end of ADC1_tag */ \r
+\r
+#endif //Removed ADC\r
+\r
+/****************************************************************************/\r
+/* MODULE : CANSP */\r
+/****************************************************************************/\r
+ struct CANSP_tag {\r
+ \r
+ union { /* CANSP Control Reg (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RX_COMPLETE:1;\r
+ vuint32_t BUSY:1;\r
+ vuint32_t ACTIVE_CK:1;\r
+ vuint32_t:3;\r
+ vuint32_t MODE:1;\r
+ vuint32_t CAN_RX_SEL:3;\r
+ vuint32_t BRP:5;\r
+ vuint32_t CAN_SMPLR_EN:1;\r
+ } B;\r
+ } CR; \r
+\r
+ union { /* CANSP Sample 0..11 (Base+0x0000-0x0030)*/\r
+ vuint32_t R;\r
+ } SR[12];\r
+\r
+ }; /* end of CANSP_tag */ \r
+/****************************************************************************/\r
+/* MODULE : ECSM */\r
+/****************************************************************************/\r
+struct ECSM_tag{\r
+\r
+ union { /* ECSM Processor Core Type (Base+0x0000) */\r
+ vuint16_t R;\r
+ } PCT;\r
+\r
+ union { /* ECSM Revision (Base+0x0002) */\r
+ vuint16_t R;\r
+ } REV;\r
+\r
+ vuint8_t ECSM_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* ECSM IPS Module Configuration (Base+0x0008) */\r
+ vuint32_t R;\r
+ } IMC;\r
+\r
+ vuint8_t ECSM_reserved1[7]; /* Reserved 7 bytes (Base+0x000C-0x0012) */\r
+\r
+ union { /* ECSM Miscellaneous Wakeup Control (+0x0013) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ENBWCR:1;\r
+ vuint8_t :3;\r
+ vuint8_t PRILVL:4;\r
+ } B;\r
+ } MWCR;\r
+\r
+ vuint8_t ECSM_reserved2[11]; /* Reserved 11 bytes (Base+0x0014-0x001E) */\r
+\r
+ union { /* ECSM Miscellaneous Interrupt (Base+0x001F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t FB0AI:1;\r
+ vuint8_t FB0SI:1;\r
+ vuint8_t FB1AI:1;\r
+ vuint8_t FB1SI:1;\r
+ vuint8_t :4;\r
+ } B;\r
+ } MIR;\r
+\r
+ vuint8_t ECSM_reserved3[4]; /* Reserved 4 bytes (Base+0x0020-0x0023) */\r
+\r
+ union { /*ECSM Miscellaneous User-Defined Control (+0x0024)*/\r
+ vuint32_t R;\r
+ } MUDCR; /* ECSM Miscellaneous User-Defined Control Register */\r
+\r
+ vuint8_t ECSM_reserved4[27]; /* Reserved 27 bytes (Base+0x0028-0x0042) */\r
+\r
+ union { /* ECSM ECC Configuration (Base+0x0043) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :2;\r
+ vuint8_t ER1BR:1;\r
+ vuint8_t EF1BR:1;\r
+ vuint8_t :2;\r
+ vuint8_t ERNCR:1;\r
+ vuint8_t EFNCR:1;\r
+ } B;\r
+ } ECR;\r
+\r
+ vuint8_t ECSM_reserved5[3]; /* Reserved 3 bytes (Base+0x0044-0x0046) */\r
+\r
+ union { /* ECSM ECC Status (Base+0x0047) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :2;\r
+ vuint8_t R1BC:1;\r
+ vuint8_t F1BC:1;\r
+ vuint8_t :2;\r
+ vuint8_t RNCE:1;\r
+ vuint8_t FNCE:1;\r
+ } B;\r
+ } ESR;\r
+\r
+ vuint8_t ECSM_reserved6[2]; /* Reserved 2 bytes (Base+0x0048-0x0049) */\r
+\r
+ union { /* ECSM ECC Error Generation (Base+0x004A) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :2;\r
+ vuint16_t FRC1BI:1;\r
+ vuint16_t FR11BI:1;\r
+ vuint16_t :2;\r
+ vuint16_t FRCNCI:1;\r
+ vuint16_t FR1NCI:1;\r
+ vuint16_t :1;\r
+ vuint16_t ERRBIT:7;\r
+ } B;\r
+ } EEGR;\r
+\r
+ vuint8_t ECSM_reserved7[4]; /* Reserved 4 bytes (Base+0x004C-0x004F) */\r
+\r
+ union { /* ECSM Flash ECC Address(Base+0x0050) */\r
+ vuint32_t R;\r
+ } FEAR;\r
+\r
+ vuint8_t ECSM_reserved8[2]; /* Reserved 2 bytes (Base+0x0054-0x0055) */\r
+\r
+ union { /* ECSM Flash ECC Master Number (Base+0x0056) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :4;\r
+ vuint8_t FEMR:4;\r
+ } B;\r
+ } FEMR;\r
+\r
+ union { /* ECSM Flash ECC Attributes (Base+0x0057) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROTECTION:4;\r
+ } B;\r
+ } FEAT;\r
+\r
+ vuint8_t ECSM_reserved9[4]; /* Reserved 4 bytes (Base+0x0058-0x005B) */\r
+\r
+ union { /* ECSM Flash ECC Data (Base+0x005C) */\r
+ vuint32_t R;\r
+ } FEDR;\r
+\r
+ union { /* ECSM RAM ECC Address (Base+0x0060) */\r
+ vuint32_t R;\r
+ } REAR;\r
+\r
+ vuint8_t ECSM_reserved10[1]; /* Reserved 1 bytes (Base+0x0064) */\r
+\r
+ union { /* ECSM RAM ECC Address (Base+0x0065) */\r
+ vuint8_t R;\r
+ } RESR;\r
+\r
+ union { /* ECSM RAM ECC Master Number (Base+0x0066) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :4;\r
+ vuint8_t REMR:4;\r
+ } B;\r
+ } REMR;\r
+\r
+ union { /* ECSM RAM ECC Attributes (Base+0x0067) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROTECTION:4;\r
+ } B;\r
+ } REAT;\r
+\r
+ vuint8_t ECSM_reserved11[4]; /* Reserved 4 bytes (Base+0x0068-0x006B) */\r
+\r
+ union { /* ECSM RAM ECC Data (Base+0x006C) */\r
+ vuint32_t R;\r
+ } REDR;\r
+\r
+}; /* end of ECSM_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : RTC/API */\r
+/****************************************************************************/\r
+struct RTC_tag{\r
+\r
+ union { /* RTC Supervisor Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SUPV:1;\r
+ vuint32_t :31;\r
+ } B;\r
+ } RTCSUPV ;\r
+\r
+ union { /* RTC Control (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CNTEN:1;\r
+ vuint32_t RTCIE:1;\r
+ vuint32_t FRZEN:1;\r
+ vuint32_t ROVREN:1;\r
+ vuint32_t RTCVAL:12;\r
+ vuint32_t APIEN:1;\r
+ vuint32_t APIIE:1;\r
+ vuint32_t CLKSEL:2;\r
+ vuint32_t DIV512EN:1;\r
+ vuint32_t DIV32EN:1;\r
+ vuint32_t APIVAL:10;\r
+ } B;\r
+ } RTCC;\r
+\r
+ union { /* RTC Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :2;\r
+ vuint32_t RTCF:1;\r
+ vuint32_t :15;\r
+ vuint32_t APIF:1;\r
+ vuint32_t :2;\r
+ vuint32_t ROVRF:1;\r
+ vuint32_t :10;\r
+ } B;\r
+ } RTCS;\r
+\r
+ union { /* RTC Counter (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RTCCNT:32;\r
+ } B;\r
+ } RTCCNT;\r
+\r
+}; /* end of RTC_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : SIU Lite (tagged as SIU for compatibility) */\r
+/****************************************************************************/\r
+struct SIU_tag {\r
+\r
+ vuint8_t SIU_reserved0[4]; /* Reserved 4 Bytes (Base+0x0) */\r
+\r
+ union { /* MCU ID1 (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PARTNUM:16;\r
+ vuint32_t CSP:1;\r
+ vuint32_t PKG:5;\r
+ vuint32_t :2;\r
+ vuint32_t MAJOR_MASK:4;\r
+ vuint32_t MINOR_MASK:4;\r
+ } B;\r
+ } MIDR;\r
+\r
+ union { /* MCU ID2 (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SF:1;\r
+ vuint32_t FLASH_SIZE_1:4;\r
+ vuint32_t FLASH_SIZE_2:4;\r
+ vuint32_t :7;\r
+ vuint32_t PARTNUM:8;\r
+ vuint32_t :3;\r
+ vuint32_t EE:1;\r
+ vuint32_t :3;\r
+ vuint32_t FR:1;\r
+ } B;\r
+ } MIDR2;\r
+\r
+ vuint8_t SIU_reserved1[8]; /* Reserved 8 Bytes (Base+(0x000C--0x0013)) */\r
+\r
+ union { /* Interrupt Status Flag (Base+0x0014)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EIF23:1;\r
+ vuint32_t EIF22:1;\r
+ vuint32_t EIF21:1;\r
+ vuint32_t EIF20:1;\r
+ vuint32_t EIF19:1;\r
+ vuint32_t EIF18:1;\r
+ vuint32_t EIF17:1;\r
+ vuint32_t EIF16:1;\r
+ vuint32_t EIF15:1;\r
+ vuint32_t EIF14:1;\r
+ vuint32_t EIF13:1;\r
+ vuint32_t EIF12:1;\r
+ vuint32_t EIF11:1;\r
+ vuint32_t EIF10:1;\r
+ vuint32_t EIF9:1;\r
+ vuint32_t EIF8:1;\r
+ vuint32_t EIF7:1;\r
+ vuint32_t EIF6:1;\r
+ vuint32_t EIF5:1;\r
+ vuint32_t EIF4:1;\r
+ vuint32_t EIF3:1;\r
+ vuint32_t EIF2:1;\r
+ vuint32_t EIF1:1;\r
+ vuint32_t EIF0:1;\r
+ } B;\r
+ } ISR;\r
+\r
+ union { /* Interrupt Request Enable (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IRE23:1;\r
+ vuint32_t IRE22:1;\r
+ vuint32_t IRE21:1;\r
+ vuint32_t IRE20:1;\r
+ vuint32_t IRE19:1;\r
+ vuint32_t IRE18:1;\r
+ vuint32_t IRE17:1;\r
+ vuint32_t IRE16:1;\r
+ vuint32_t IRE15:1;\r
+ vuint32_t IRE14:1;\r
+ vuint32_t IRE13:1;\r
+ vuint32_t IRE12:1;\r
+ vuint32_t IRE11:1;\r
+ vuint32_t IRE10:1;\r
+ vuint32_t IRE9:1;\r
+ vuint32_t IRE8:1;\r
+ vuint32_t IRE7:1;\r
+ vuint32_t IRE6:1;\r
+ vuint32_t IRE5:1;\r
+ vuint32_t IRE4:1;\r
+ vuint32_t IRE3:1;\r
+ vuint32_t IRE2:1;\r
+ vuint32_t IRE1:1;\r
+ vuint32_t IRE0:1;\r
+ } B;\r
+ } IRER;\r
+\r
+ vuint8_t SIU_reserved2[12]; /* Reserved 12 Bytes (Base+0x001C-0x0027) */\r
+\r
+ union { /* Interrupt Rising-Edge Event Enable (+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IREE23:1;\r
+ vuint32_t IREE22:1;\r
+ vuint32_t IREE21:1;\r
+ vuint32_t IREE20:1;\r
+ vuint32_t IREE19:1;\r
+ vuint32_t IREE18:1;\r
+ vuint32_t IREE17:1;\r
+ vuint32_t IREE16:1;\r
+ vuint32_t IREE15:1;\r
+ vuint32_t IREE14:1;\r
+ vuint32_t IREE13:1;\r
+ vuint32_t IREE12:1;\r
+ vuint32_t IREE11:1;\r
+ vuint32_t IREE10:1;\r
+ vuint32_t IREE9:1;\r
+ vuint32_t IREE8:1;\r
+ vuint32_t IREE7:1;\r
+ vuint32_t IREE6:1;\r
+ vuint32_t IREE5:1;\r
+ vuint32_t IREE4:1;\r
+ vuint32_t IREE3:1;\r
+ vuint32_t IREE2:1;\r
+ vuint32_t IREE1:1;\r
+ vuint32_t IREE0:1;\r
+ } B;\r
+ } IREER;\r
+\r
+ union { /* Interrupt Falling-Edge Event Enable (+0x002C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IFEE23:1;\r
+ vuint32_t IFEE22:1;\r
+ vuint32_t IFEE21:1;\r
+ vuint32_t IFEE20:1;\r
+ vuint32_t IFEE19:1;\r
+ vuint32_t IFEE18:1;\r
+ vuint32_t IFEE17:1;\r
+ vuint32_t IFEE16:1;\r
+ vuint32_t IFEE15:1;\r
+ vuint32_t IFEE14:1;\r
+ vuint32_t IFEE13:1;\r
+ vuint32_t IFEE12:1;\r
+ vuint32_t IFEE11:1;\r
+ vuint32_t IFEE10:1;\r
+ vuint32_t IFEE9:1;\r
+ vuint32_t IFEE8:1;\r
+ vuint32_t IFEE7:1;\r
+ vuint32_t IFEE6:1;\r
+ vuint32_t IFEE5:1;\r
+ vuint32_t IFEE4:1;\r
+ vuint32_t IFEE3:1;\r
+ vuint32_t IFEE2:1;\r
+ vuint32_t IFEE1:1;\r
+ vuint32_t IFEE0:1;\r
+ } B;\r
+ } IFEER;\r
+\r
+ union { /* Interrupt Filter Enable (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IFE23:1;\r
+ vuint32_t IFE22:1;\r
+ vuint32_t IFE21:1;\r
+ vuint32_t IFE20:1;\r
+ vuint32_t IFE19:1;\r
+ vuint32_t IFE18:1;\r
+ vuint32_t IFE17:1;\r
+ vuint32_t IFE16:1;\r
+ vuint32_t IFE15:1;\r
+ vuint32_t IFE14:1;\r
+ vuint32_t IFE13:1;\r
+ vuint32_t IFE12:1;\r
+ vuint32_t IFE11:1;\r
+ vuint32_t IFE10:1;\r
+ vuint32_t IFE9:1;\r
+ vuint32_t IFE8:1;\r
+ vuint32_t IFE7:1;\r
+ vuint32_t IFE6:1;\r
+ vuint32_t IFE5:1;\r
+ vuint32_t IFE4:1;\r
+ vuint32_t IFE3:1;\r
+ vuint32_t IFE2:1;\r
+ vuint32_t IFE1:1;\r
+ vuint32_t IFE0:1;\r
+ } B;\r
+ } IFER;\r
+\r
+ vuint8_t SIU_reserved3[12]; /* Reserved 12 Bytes (Base+0x0034-0x003F) */\r
+\r
+ union { /* Pad Configuration 0..148 (Base+0x0040-0x0168)*/\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:1;\r
+ vuint16_t SMC:1;\r
+ vuint16_t APC:1;\r
+ vuint16_t:1;\r
+ vuint16_t PA:2;\r
+ vuint16_t OBE:1;\r
+ vuint16_t IBE:1;\r
+ vuint16_t:2;\r
+ vuint16_t ODE:1;\r
+ vuint16_t:2;\r
+ vuint16_t SRC:1;\r
+ vuint16_t WPE:1;\r
+ vuint16_t WPS:1;\r
+ } B;\r
+ } PCR[149];\r
+\r
+ vuint8_t SIU_reserved4[918]; /*Reserved 918 Bytes (Base+0x016A-0x04FF) */\r
+\r
+ union { /* Pad Selection for Mux Input (0x0500-0x53C) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :4;\r
+ vuint8_t PADSEL:4;\r
+ } B;\r
+ } PSMI[64];\r
+\r
+ vuint8_t SIU_reserved5[192]; /*Reserved 192 Bytes (Base+0x0540-0x05FF) */\r
+\r
+ union { /* GPIO Pad Data Output (Base+0x0600-0x06A0) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :7;\r
+ vuint8_t PDO:1;\r
+ } B;\r
+ } GPDO[152]; // only 152 GPD0 registers \r
+\r
+ vuint8_t SIU_reserved6[360]; /*Reserved 348 Bytes (Base+0x06A4-0x07FF) */\r
+\r
+ union { /* GPIO Pad Data Input (Base+0x0800-0x08A0) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :7;\r
+ vuint8_t PDI:1;\r
+ } B;\r
+ } GPDI[152]; // only 152 GPD0 registers \r
+\r
+ vuint8_t SIU_reserved7[872]; /*Reserved 860 Bytes (Base+0x08A4-0x0BFF) */\r
+\r
+ union { /* Parallel GPIO Pad Data Out 0-4 (0x0C00-0xC010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PPD0:32;\r
+ } B;\r
+ } PGPDO[5];\r
+\r
+ vuint8_t SIU_reserved8[44]; /* Reserved 44 Bytes (Base+0x0C14-0x0C3F) */\r
+\r
+ union { /* Parallel GPIO Pad Data In 0-4 (0x0C40-0x0C50) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PPDI:32;\r
+ } B;\r
+ } PGPDI[5];\r
+\r
+ vuint8_t SIU_reserved9[44]; /* Reserved 44 Bytes (Base+0x0C54-0x0C7F) */\r
+\r
+ union { /* Masked Parallel GPIO Pad Data Out 0-9 (0x0C80-0x0CA4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MASK:16;\r
+ vuint32_t MPPDO:16;\r
+ } B;\r
+ } MPGPDO[10];\r
+\r
+ vuint8_t SIU_reserved10[856]; /*Reserved 844 Bytes (Base+0x0CA8-0x0FFF)*/\r
+\r
+ union { /* Interrupt Filter Max Counter 0..23 (+0x1000-0x105C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t MAXCNT:4;\r
+ } B;\r
+ } IFMC[24];\r
+\r
+ vuint8_t SIU_reserved11[32]; /* Reserved 32 Bytes (Base+0x1060-0x107F)*/\r
+\r
+ union { /* Interrupt Filter Clock Prescaler (Base+0x1080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t IFCP:4;\r
+ } B;\r
+ } IFCPR;\r
+\r
+ vuint8_t SIU_reserved12[12156]; /* Reserved 12156 Bytes (+0x1084-0x3FFF)*/\r
+\r
+}; /* end of SIU_tag */\r
+/****************************************************************************/\r
+/* MODULE : SSCM */\r
+/****************************************************************************/\r
+struct SSCM_tag{\r
+\r
+ union { /* Status (Base+0x0000) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:4;\r
+ vuint16_t NXEN:1;\r
+ vuint16_t:3;\r
+ vuint16_t BMODE:3;\r
+ vuint16_t :1;\r
+ vuint16_t ABD:1;\r
+ vuint16_t:3;\r
+ } B;\r
+ } STATUS;\r
+\r
+ union { /* System Memory Configuration (Base+0x002) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t PRSZ:5;\r
+ vuint16_t PVLB:1;\r
+ vuint16_t DTSZ:4;\r
+ vuint16_t DVLD:1;\r
+ } B;\r
+ } MEMCONFIG;\r
+\r
+ vuint8_t SSCM_reserved0[2]; /* Reserved 2 bytes (Base+0x0004-0x0005) */\r
+\r
+ union { /* Error Configuration (Base+0x0006) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :14;\r
+ vuint16_t PAE:1;\r
+ vuint16_t RAE:1;\r
+ } B;\r
+ } ERROR;\r
+\r
+ union { /* Debug Status Port (Base+0x0008) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :13;\r
+ vuint16_t DEBUG_MODE:3;\r
+ } B;\r
+ } DEBUGPORT;\r
+\r
+ vuint8_t SSCM_reserved1[2]; /* Reserved 2 bytes (Base+0x000A-0x000B) */\r
+\r
+ union { /* Password Comparison High Word (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PWD_HI:32;\r
+ } B;\r
+ } PWCMPH;\r
+\r
+ union { /* Password Comparison Low Word (Base+0x0010)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PWD_LO:32;\r
+ } B;\r
+ } PWCMPL;\r
+\r
+}; /* end of SSCM_tag */\r
+/****************************************************************************/\r
+/* MODULE : STM */\r
+/****************************************************************************/\r
+ struct STM_CHANNEL_tag{\r
+\r
+ union { /* STM Channel Control 0..3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR;\r
+\r
+ union { /* STM Channel Interrupt 0..3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR;\r
+\r
+ union { /* STM Channel Compare 0..3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CMP:32;\r
+ } B;\r
+ } CMP;\r
+\r
+ vuint8_t STM_CHANNEL_reserved0[4]; /* Reserved 4 bytes between ch reg's */\r
+\r
+ }; /* end of STM_CHANNEL_tag */\r
+\r
+\r
+struct STM_tag{\r
+\r
+ union { /* STM Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CPS:8;\r
+ vuint32_t :6;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* STM Count (Base+0x0004) */\r
+ vuint32_t R;\r
+ } CNT;\r
+\r
+ vuint8_t STM_reserved1[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */\r
+\r
+ struct STM_CHANNEL_tag CH[4]; /*STM Channels 0..3 (Base+0x0010-0x0048) */\r
+\r
+}; /* end of STM_tag */\r
+/****************************************************************************/\r
+/* MODULE : SWT */\r
+/****************************************************************************/\r
+struct SWT_tag{\r
+\r
+ union { /* SWT Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MAP0:1;\r
+ vuint32_t MAP1:1;\r
+ vuint32_t MAP2:1;\r
+ vuint32_t MAP3:1;\r
+ vuint32_t MAP4:1;\r
+ vuint32_t MAP5:1;\r
+ vuint32_t MAP6:1;\r
+ vuint32_t MAP7:1;\r
+ vuint32_t :14;\r
+ vuint32_t KEY:1;\r
+ vuint32_t RIA:1;\r
+ vuint32_t WND:1;\r
+ vuint32_t ITR:1;\r
+ vuint32_t HLK:1;\r
+ vuint32_t SLK:1;\r
+ vuint32_t CSL:1;\r
+ vuint32_t STP:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t WEN:1;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* SWT Interrupt (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } IR;\r
+\r
+ union { /* SWT Time-Out (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t WTO:32;\r
+ } B;\r
+ } TO;\r
+\r
+ union { /* SWT Window (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t WST:32;\r
+ } B;\r
+ } WN;\r
+\r
+ union { /* SWT Service (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t WSC:16;\r
+ } B;\r
+ } SR;\r
+\r
+ union { /* SWT Counter Output (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CNT:32;\r
+ } B;\r
+ } CO;\r
+\r
+}; /* end of SWT_tag */ \r
+/****************************************************************************/\r
+/* MODULE : WKUP */\r
+/****************************************************************************/\r
+struct WKUP_tag{\r
+\r
+ union { /* NMI Status Flag (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NIF0:1; \r
+ vuint32_t NOVF0:1;\r
+ vuint32_t :30;\r
+ } B;\r
+ } NSR;\r
+\r
+ vuint8_t WKUP_reserved0[4]; /* Reserved 4 Bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* NMI Configuration (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NLOCK0:1;\r
+ vuint32_t NDSS0:2;\r
+ vuint32_t NWRE0:1;\r
+ vuint32_t :1;\r
+ vuint32_t NREE0:1;\r
+ vuint32_t NFEE0:1;\r
+ vuint32_t NFE0:1;\r
+ vuint32_t :24;\r
+ } B;\r
+ } NCR;\r
+\r
+ vuint8_t WKUP_reserved1[8]; /* Reserved 8 Bytes (Base+0x000C-0x0013) */\r
+\r
+ union { /* Wakeup/Interrup status flag (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t EIF:29;\r
+ } B;\r
+ } WISR;\r
+\r
+ union { /* Interrupt Request Enable (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t EIRE:29; \r
+ } B;\r
+ } IRER;\r
+\r
+ union { /* Wakeup Request Enable (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t WRE:29;\r
+ } B;\r
+ } WRER;\r
+\r
+ vuint8_t WKUP_reserved2[8]; /* Reserved 8 Bytes (Base+0x0020-0x0027) */\r
+\r
+ union { /* Wakeup/Interrupt Rising-Edge (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IREE:29;\r
+ } B;\r
+ } WIREER;\r
+\r
+ union { /* Wakeup/Interrupt Falling-Edge (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IFEE:29;\r
+ } B;\r
+ } WIFEER;\r
+\r
+ union { /* Wakeup/Interrupt Filter Enable (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IFE:29;\r
+ } B;\r
+ } WIFER;\r
+\r
+ union { /* Wakeup/Interrupt Pullup Enable (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IPUE:29;\r
+ } B;\r
+ } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */\r
+\r
+ vuint8_t WKUP_reserved3[16328]; /* Reserved 16328 (Base+0x0038-0x3FFF) */\r
+\r
+}; /* end of WKUP_tag */\r
+/****************************************************************************/\r
+/* MODULE : LINFLEX */\r
+/****************************************************************************/\r
+struct LINFLEX_tag {\r
+\r
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CCD:1;\r
+ vuint32_t CFD:1;\r
+ vuint32_t LASE:1;\r
+ vuint32_t AWUM:1;\r
+ vuint32_t MBL:4;\r
+ vuint32_t BF:1;\r
+ vuint32_t SFTM:1;\r
+ vuint32_t LBKM:1;\r
+ vuint32_t MME:1;\r
+ vuint32_t SBDT:1;\r
+ vuint32_t RBLM:1;\r
+ vuint32_t SLEEP:1;\r
+ vuint32_t INIT:1;\r
+ } B;\r
+ } LINCR1;\r
+\r
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZIE:1;\r
+ vuint32_t OCIE:1;\r
+ vuint32_t BEIE:1;\r
+ vuint32_t CEIE:1;\r
+ vuint32_t HEIE:1;\r
+ vuint32_t :2;\r
+ vuint32_t FEIE:1;\r
+ vuint32_t BOIE:1;\r
+ vuint32_t LSIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t DBFIE:1;\r
+ vuint32_t DBEIE:1;\r
+ vuint32_t DRIE:1;\r
+ vuint32_t DTIE:1;\r
+ vuint32_t HRIE:1;\r
+ } B;\r
+ } LINIER;\r
+\r
+ union { /* LINFLEX LIN Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t LINS:4;\r
+ vuint32_t:2;\r
+ vuint32_t RMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t RBSY:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t DBFF:1;\r
+ vuint32_t DBEF:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t HRF:1;\r
+ } B;\r
+ } LINSR;\r
+\r
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t BEF:1;\r
+ vuint32_t CEF:1;\r
+ vuint32_t SFEF:1;\r
+ vuint32_t BDEF:1;\r
+ vuint32_t IDPEF:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t:6;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } LINESR;\r
+\r
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:1;\r
+ vuint32_t TDFL:2;\r
+ vuint32_t:1;\r
+ vuint32_t RDFL:2;\r
+ vuint32_t:4;\r
+ vuint32_t RXEN:1;\r
+ vuint32_t TXEN:1;\r
+ vuint32_t OP:1;\r
+ vuint32_t PCE:1;\r
+ vuint32_t WL:1;\r
+ vuint32_t UART:1; \r
+ } B;\r
+ } UARTCR;\r
+\r
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/\r
+ vuint32_t RMB:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t :1;\r
+ vuint32_t TO:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } UARTSR;\r
+\r
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:5;\r
+ vuint32_t LTOM:1;\r
+ vuint32_t IOT:1;\r
+ vuint32_t TOCE:1;\r
+ vuint32_t CNT:8;\r
+ } B;\r
+ } LINTCSR;\r
+\r
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t OC2:8;\r
+ vuint32_t OC1:8;\r
+ } B;\r
+ } LINOCR;\r
+\r
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t RTO:4;\r
+ vuint32_t:1;\r
+ vuint32_t HTO:7;\r
+ } B;\r
+ } LINTOCR;\r
+\r
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIV_F:4;\r
+ } B;\r
+ } LINFBRR;\r
+\r
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t DIV_M:20;\r
+ } B;\r
+ } LINIBRR;\r
+\r
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CF:8;\r
+ } B;\r
+ } LINCFR;\r
+\r
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:17;\r
+ vuint32_t IOBE:1;\r
+ vuint32_t IOPE:1;\r
+ vuint32_t WURQ:1;\r
+ vuint32_t DDRQ:1;\r
+ vuint32_t DTRQ:1;\r
+ vuint32_t ABRQ:1;\r
+ vuint32_t HTRQ:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LINCR2;\r
+\r
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } BIDR;\r
+\r
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA3:8;\r
+ vuint32_t DATA2:8;\r
+ vuint32_t DATA1:8;\r
+ vuint32_t DATA0:8;\r
+ } B;\r
+ } BDRL;\r
+\r
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA7:8;\r
+ vuint32_t DATA6:8;\r
+ vuint32_t DATA5:8;\r
+ vuint32_t DATA4:8;\r
+ } B;\r
+ } BDRM;\r
+\r
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t FACT:8;\r
+ } B;\r
+ } IFER;\r
+\r
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t IFMI:4;\r
+ } B;\r
+ } IFMI;\r
+\r
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t IFM:5;\r
+ } B;\r
+ } IFMR;\r
+\r
+ union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t:3; /* for LINflexD no reseve here*/\r
+ vuint32_t DFL:3; /* Linflex D - this field is 6 bits (0 and 1), Linflex - this field is 3 bits (2-9 B1.5M) (2-7 B1M) */ \r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } IFCR[16];\r
+\r
+ \r
+}; /* end of LINFLEX_tag */\r
+\r
+\r
+/****************************************************************************/\r
+/* MODULE : LINFLEXD0 */\r
+/****************************************************************************/\r
+struct LINFLEXD0_tag {\r
+\r
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CCD:1;\r
+ vuint32_t CFD:1;\r
+ vuint32_t LASE:1;\r
+ vuint32_t AWUM:1;\r
+ vuint32_t MBL:4;\r
+ vuint32_t BF:1;\r
+ vuint32_t SFTM:1;\r
+ vuint32_t LBKM:1;\r
+ vuint32_t MME:1;\r
+ vuint32_t SBDT:1;\r
+ vuint32_t RBLM:1;\r
+ vuint32_t SLEEP:1;\r
+ vuint32_t INIT:1;\r
+ } B;\r
+ } LINCR1;\r
+\r
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZIE:1;\r
+ vuint32_t OCIE:1;\r
+ vuint32_t BEIE:1;\r
+ vuint32_t CEIE:1;\r
+ vuint32_t HEIE:1;\r
+ vuint32_t :2;\r
+ vuint32_t FEIE:1;\r
+ vuint32_t BOIE:1;\r
+ vuint32_t LSIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t DBFIE:1;\r
+ vuint32_t DBEIE:1;\r
+ vuint32_t DRIE:1;\r
+ vuint32_t DTIE:1;\r
+ vuint32_t HRIE:1;\r
+ } B;\r
+ } LINIER;\r
+\r
+ union { /* LINFLEX LIN Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t LINS:4;\r
+ vuint32_t:2;\r
+ vuint32_t RMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t RBSY:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t DBFF:1;\r
+ vuint32_t DBEF:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t HRF:1;\r
+ } B;\r
+ } LINSR;\r
+\r
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t BEF:1;\r
+ vuint32_t CEF:1;\r
+ vuint32_t SFEF:1;\r
+ vuint32_t BDEF:1;\r
+ vuint32_t IDPEF:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t:6;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } LINESR;\r
+\r
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t TDFLTFC:3;\r
+ vuint32_t RDFLTFC:3;\r
+ vuint32_t RFBM:1;\r
+ vuint32_t TFBM:1;\r
+ vuint32_t WL1:1;\r
+ vuint32_t PC1:1;\r
+ vuint32_t RXEN:1;\r
+ vuint32_t TXEN:1;\r
+ vuint32_t PC0:1;\r
+ vuint32_t PCE:1;\r
+ vuint32_t WL0:1;\r
+ vuint32_t UART:1;\r
+ } B;\r
+ } UARTCR;\r
+\r
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/\r
+ vuint32_t RMB:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t :1;\r
+ vuint32_t TO:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } UARTSR;\r
+\r
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:5;\r
+ vuint32_t LTOM:1;\r
+ vuint32_t IOT:1;\r
+ vuint32_t TOCE:1;\r
+ vuint32_t CNT:8;\r
+ } B;\r
+ } LINTCSR;\r
+\r
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t OC2:8;\r
+ vuint32_t OC1:8;\r
+ } B;\r
+ } LINOCR;\r
+\r
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t RTO:4;\r
+ vuint32_t:1;\r
+ vuint32_t HTO:7;\r
+ } B;\r
+ } LINTOCR;\r
+\r
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIV_F:4;\r
+ } B;\r
+ } LINFBRR;\r
+\r
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t DIV_M:20;\r
+ } B;\r
+ } LINIBRR;\r
+\r
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CF:8;\r
+ } B;\r
+ } LINCFR;\r
+\r
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:17;\r
+ vuint32_t IOBE:1;\r
+ vuint32_t IOPE:1;\r
+ vuint32_t WURQ:1;\r
+ vuint32_t DDRQ:1;\r
+ vuint32_t DTRQ:1;\r
+ vuint32_t ABRQ:1;\r
+ vuint32_t HTRQ:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LINCR2;\r
+\r
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } BIDR;\r
+\r
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA3:8;\r
+ vuint32_t DATA2:8;\r
+ vuint32_t DATA1:8;\r
+ vuint32_t DATA0:8;\r
+ } B;\r
+ } BDRL;\r
+\r
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA7:8;\r
+ vuint32_t DATA6:8;\r
+ vuint32_t DATA5:8;\r
+ vuint32_t DATA4:8;\r
+ } B;\r
+ } BDRM;\r
+\r
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t FACT:8;\r
+ } B;\r
+ } IFER;\r
+\r
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t IFMI:4;\r
+ } B;\r
+ } IFMI;\r
+\r
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t IFM:5;\r
+ } B;\r
+ } IFMR;\r
+\r
+ union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } IFCR[16];\r
+\r
+ union { /* LINFLEX Global Counter (+0x008C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t TDFBM:1;\r
+ vuint32_t RDFBM:1;\r
+ vuint32_t TDLIS:1;\r
+ vuint32_t RDLIS:1;\r
+ vuint32_t STOP:1;\r
+ vuint32_t SR:1;\r
+ } B;\r
+ } GCR;\r
+\r
+ union { /* LINFLEX UART preset timeout (+0x0090) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t PTO:12;\r
+ } B;\r
+ } UARTPTO;\r
+\r
+ union { /* LINFLEX UART current timeout (+0x0094) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t CTO:12;\r
+ } B;\r
+ } UARTCTO;\r
+\r
+ union { /* LINFLEX DMA Tx Enable (+0x0098) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DTE15:1;\r
+ vuint32_t DTE14:1;\r
+ vuint32_t DTE13:1;\r
+ vuint32_t DTE12:1;\r
+ vuint32_t DTE11:1;\r
+ vuint32_t DTE10:1;\r
+ vuint32_t DTE9:1;\r
+ vuint32_t DTE8:1;\r
+ vuint32_t DTE7:1;\r
+ vuint32_t DTE6:1;\r
+ vuint32_t DTE5:1;\r
+ vuint32_t DTE4:1;\r
+ vuint32_t DTE3:1;\r
+ vuint32_t DTE2:1;\r
+ vuint32_t DTE1:1;\r
+ vuint32_t DTE0:1;\r
+ } B;\r
+ } DMATXE;\r
+\r
+ union { /* LINFLEX DMA RX Enable (+0x009C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DRE15:1;\r
+ vuint32_t DRE14:1;\r
+ vuint32_t DRE13:1;\r
+ vuint32_t DRE12:1;\r
+ vuint32_t DRE11:1;\r
+ vuint32_t DRE10:1;\r
+ vuint32_t DRE9:1;\r
+ vuint32_t DRE8:1;\r
+ vuint32_t DRE7:1;\r
+ vuint32_t DRE6:1;\r
+ vuint32_t DRE5:1;\r
+ vuint32_t DRE4:1;\r
+ vuint32_t DRE3:1;\r
+ vuint32_t DRE2:1;\r
+ vuint32_t DRE1:1;\r
+ vuint32_t DRE0:1;\r
+ } B;\r
+ } DMARXE;\r
+}; /* end of LINFLEXD0_tag */\r
+/****************************************************************************/\r
+/* MODULE : LINFLEXD1 */\r
+/****************************************************************************/\r
+struct LINFLEXD1_tag {\r
+\r
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CCD:1;\r
+ vuint32_t CFD:1;\r
+ vuint32_t LASE:1;\r
+ vuint32_t AWUM:1;\r
+ vuint32_t MBL:4;\r
+ vuint32_t BF:1;\r
+ vuint32_t SFTM:1;\r
+ vuint32_t LBKM:1;\r
+ vuint32_t MME:1;\r
+ vuint32_t SBDT:1;\r
+ vuint32_t RBLM:1;\r
+ vuint32_t SLEEP:1;\r
+ vuint32_t INIT:1;\r
+ } B;\r
+ } LINCR1;\r
+\r
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZIE:1;\r
+ vuint32_t OCIE:1;\r
+ vuint32_t BEIE:1;\r
+ vuint32_t CEIE:1;\r
+ vuint32_t HEIE:1;\r
+ vuint32_t :2;\r
+ vuint32_t FEIE:1;\r
+ vuint32_t BOIE:1;\r
+ vuint32_t LSIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t DBFIE:1;\r
+ vuint32_t DBEIE:1;\r
+ vuint32_t DRIE:1;\r
+ vuint32_t DTIE:1;\r
+ vuint32_t HRIE:1;\r
+ } B;\r
+ } LINIER;\r
+\r
+ union { /* LINFLEX LIN Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t LINS:4;\r
+ vuint32_t:2;\r
+ vuint32_t RMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t RBSY:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t DBFF:1;\r
+ vuint32_t DBEF:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t HRF:1;\r
+ } B;\r
+ } LINSR;\r
+\r
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t BEF:1;\r
+ vuint32_t CEF:1;\r
+ vuint32_t SFEF:1;\r
+ vuint32_t BDEF:1;\r
+ vuint32_t IDPEF:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t:6;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } LINESR;\r
+\r
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t TDFLTFC:3;\r
+ vuint32_t RDFLTFC:3;\r
+ vuint32_t RFBM:1;\r
+ vuint32_t TFBM:1;\r
+ vuint32_t WL1:1;\r
+ vuint32_t PC1:1;\r
+ vuint32_t RXEN:1;\r
+ vuint32_t TXEN:1;\r
+ vuint32_t PC0:1;\r
+ vuint32_t PCE:1;\r
+ vuint32_t WL0:1;\r
+ vuint32_t UART:1;\r
+ } B;\r
+ } UARTCR;\r
+\r
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/\r
+ vuint32_t RMB:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t:2;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } UARTSR;\r
+\r
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:5;\r
+ vuint32_t LTOM:1;\r
+ vuint32_t IOT:1;\r
+ vuint32_t TOCE:1;\r
+ vuint32_t CNT:8;\r
+ } B;\r
+ } LINTCSR;\r
+\r
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t OC2:8;\r
+ vuint32_t OC1:8;\r
+ } B;\r
+ } LINOCR;\r
+\r
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t RTO:4;\r
+ vuint32_t:1;\r
+ vuint32_t HTO:7;\r
+ } B;\r
+ } LINTOCR;\r
+\r
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIV_F:4;\r
+ } B;\r
+ } LINFBRR;\r
+\r
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t DIV_M:20;\r
+ } B;\r
+ } LINIBRR;\r
+\r
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CF:8;\r
+ } B;\r
+ } LINCFR;\r
+\r
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:17;\r
+ vuint32_t IOBE:1;\r
+ vuint32_t IOPE:1;\r
+ vuint32_t WURQ:1;\r
+ vuint32_t DDRQ:1;\r
+ vuint32_t DTRQ:1;\r
+ vuint32_t ABRQ:1;\r
+ vuint32_t HTRQ:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LINCR2;\r
+\r
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } BIDR;\r
+\r
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA3:8;\r
+ vuint32_t DATA2:8;\r
+ vuint32_t DATA1:8;\r
+ vuint32_t DATA0:8;\r
+ } B;\r
+ } BDRL;\r
+\r
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA7:8;\r
+ vuint32_t DATA6:8;\r
+ vuint32_t DATA5:8;\r
+ vuint32_t DATA4:8;\r
+ } B;\r
+ } BDRM;\r
+\r
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t FACT:8;\r
+ } B;\r
+ } IFER;\r
+\r
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t IFMI:4;\r
+ } B;\r
+ } IFMI;\r
+\r
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t IFM:5;\r
+ } B;\r
+ } IFMR;\r
+\r
+/* No IFCR registers on LinFlexD_1 */\r
+\r
+ union { /* LINFLEX Global Counter (+0x004C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t TDFBM:1;\r
+ vuint32_t RDFBM:1;\r
+ vuint32_t TDLIS:1;\r
+ vuint32_t RDLIS:1;\r
+ vuint32_t STOP:1;\r
+ vuint32_t SR:1;\r
+ } B;\r
+ } GCR;\r
+\r
+ union { /* LINFLEX UART preset timeout (+0x0050) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t PTO:12;\r
+ } B;\r
+ } UARTPTO;\r
+\r
+ union { /* LINFLEX UART current timeout (+0x0054) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t CTO:12;\r
+ } B;\r
+ } UARTCTO;\r
+\r
+ union { /* LINFLEX DMA Tx Enable (+0x0058) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DTE15:1;\r
+ vuint32_t DTE14:1;\r
+ vuint32_t DTE13:1;\r
+ vuint32_t DTE12:1;\r
+ vuint32_t DTE11:1;\r
+ vuint32_t DTE10:1;\r
+ vuint32_t DTE9:1;\r
+ vuint32_t DTE8:1;\r
+ vuint32_t DTE7:1;\r
+ vuint32_t DTE6:1;\r
+ vuint32_t DTE5:1;\r
+ vuint32_t DTE4:1;\r
+ vuint32_t DTE3:1;\r
+ vuint32_t DTE2:1;\r
+ vuint32_t DTE1:1;\r
+ vuint32_t DTE0:1;\r
+ } B;\r
+ } DMATXE;\r
+\r
+ union { /* LINFLEX DMA RX Enable (+0x005C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DRE15:1;\r
+ vuint32_t DRE14:1;\r
+ vuint32_t DRE13:1;\r
+ vuint32_t DRE12:1;\r
+ vuint32_t DRE11:1;\r
+ vuint32_t DRE10:1;\r
+ vuint32_t DRE9:1;\r
+ vuint32_t DRE8:1;\r
+ vuint32_t DRE7:1;\r
+ vuint32_t DRE6:1;\r
+ vuint32_t DRE5:1;\r
+ vuint32_t DRE4:1;\r
+ vuint32_t DRE3:1;\r
+ vuint32_t DRE2:1;\r
+ vuint32_t DRE1:1;\r
+ vuint32_t DRE0:1;\r
+ } B;\r
+ } DMARXE;\r
+}; /* end of LINFLEXD1_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : ME */\r
+/****************************************************************************/\r
+struct ME_tag{\r
+\r
+ union { /* Global Status (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t S_CURRENTMODE:4;\r
+ vuint32_t S_MTRANS:1;\r
+ vuint32_t S_DC:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_MVR:1;\r
+ vuint32_t S_DFLA:2;\r
+ vuint32_t S_CFLA:2;\r
+ vuint32_t :9;\r
+ vuint32_t S_FMPLL:1;\r
+ vuint32_t S_FXOSC:1;\r
+ vuint32_t S_FIRC:1;\r
+ vuint32_t S_SYSCLK:4;\r
+ } B;\r
+ } GS;\r
+\r
+ union { /* Mode Control (Base+0x004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TARGET_MODE:4;\r
+ vuint32_t :12;\r
+ vuint32_t KEY:16;\r
+ } B;\r
+ } MCTL;\r
+\r
+ union { /* Mode Enable (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t :2;\r
+ vuint32_t STANDBY0:1;\r
+ vuint32_t :2;\r
+ vuint32_t STOP0:1;\r
+ vuint32_t :1;\r
+ vuint32_t HALT0:1;\r
+ vuint32_t RUN3:1;\r
+ vuint32_t RUN2:1;\r
+ vuint32_t RUN1:1;\r
+ vuint32_t RUN0:1;\r
+ vuint32_t DRUN:1;\r
+ vuint32_t SAFE:1;\r
+ vuint32_t TEST:1;\r
+ vuint32_t RESET:1;\r
+ } B;\r
+ } MER;\r
+\r
+ union { /* Interrupt Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t I_ICONF:1;\r
+ vuint32_t I_IMODE:1;\r
+ vuint32_t I_SAFE:1;\r
+ vuint32_t I_MTC:1;\r
+ } B;\r
+ } IS;\r
+\r
+ union { /* Interrupt Mask (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t M_ICONF:1;\r
+ vuint32_t M_IMODE:1;\r
+ vuint32_t M_SAFE:1;\r
+ vuint32_t M_MTC:1;\r
+ } B;\r
+ } IM;\r
+\r
+ union { /* Invalid Mode Transition Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :27;\r
+ vuint32_t S_MTI:1;\r
+ vuint32_t S_MRI:1;\r
+ vuint32_t S_DMA:1;\r
+ vuint32_t S_NMA:1;\r
+ vuint32_t S_SEA:1;\r
+ } B;\r
+ } IMTS;\r
+\r
+ union { /* Debug Mode Transition Status (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t MPH_BUSY:1;\r
+ vuint32_t :2;\r
+ vuint32_t PMC_PROG:1;\r
+ vuint32_t CORE_DBG:1;\r
+ vuint32_t :2;\r
+ vuint32_t SMR:1;\r
+ vuint32_t :1;\r
+ vuint32_t FMPLL_SC:1;\r
+ vuint32_t FXOSC_SC:1;\r
+ vuint32_t FIRC_SC:1;\r
+ vuint32_t :1;\r
+ vuint32_t SYSCLK_SW:1;\r
+ vuint32_t DFLASH_SC:1;\r
+ vuint32_t CFLASH_SC:1;\r
+ vuint32_t CDP_PRPH_0_143:1;\r
+ vuint32_t :3;\r
+ vuint32_t CDP_PRPH_96_127:1;\r
+ vuint32_t CDP_PRPH_64_95:1;\r
+ vuint32_t CDP_PRPH_32_63:1;\r
+ vuint32_t CDP_PRPH_0_31:1;\r
+ } B;\r
+ } DMTS;\r
+\r
+ vuint8_t ME_reserved0[4]; /* reserved 4 bytes (Base+0x001C-0x001F) */\r
+\r
+ union { /* Reset Mode Configuration (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } RESET;\r
+\r
+ union { /* Test Mode Configuration (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } TEST;\r
+\r
+ union { /* Safe Mode Configuration (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } SAFE;\r
+\r
+ union { /* DRUN Mode Configuration (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSCON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } DRUN;\r
+\r
+ union { /* RUN 0->4 Mode Configuration (+0x0030-0x003C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } RUN[4];\r
+\r
+ union { /* HALT0 Mode Configuration (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } HALT0;\r
+\r
+ vuint8_t ME_reserved1[4]; /* reserved 4 bytes (Base+0x0044-0x0047) */\r
+\r
+ union { /* STOP0 Mode Configuration (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } STOP0;\r
+\r
+ vuint8_t ME_reserved2[8]; /* reserved 8 bytes (Base+0x004C-0x0053) */\r
+\r
+ union { /* STANDBY0 Mode Configuration (Base+0x0054) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } STANDBY0;\r
+\r
+ vuint8_t ME_reserved3[8]; /* reserved 8 bytes (Base+0x0058-0x005F) */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct { /* Peripheral Status 0 (Base+0x0060) */\r
+ vuint32_t :8;\r
+ vuint32_t S_DMA_CH_MUX:1;\r
+ vuint32_t :1;\r
+ vuint32_t S_FLEXCAN5:1;\r
+ vuint32_t S_FLEXCAN4:1;\r
+ vuint32_t S_FLEXCAN3:1;\r
+ vuint32_t S_FLEXCAN2:1;\r
+ vuint32_t S_FLEXCAN1:1;\r
+ vuint32_t S_FLEXCAN0:1;\r
+ vuint32_t :2;\r
+ vuint32_t :1; /* S_LINFLEX9:1; // not present on B1M */\r
+ vuint32_t :1; /* S_LINFLEX8:1; // not present on B1M */\r
+ vuint32_t :2;\r
+ vuint32_t S_DSPI5:1;\r
+ vuint32_t S_DSPI4:1;\r
+ vuint32_t S_DSPI3:1;\r
+ vuint32_t S_DSPI2:1;\r
+ vuint32_t S_DSPI1:1;\r
+ vuint32_t S_DSPI0:1;\r
+ vuint32_t :4;\r
+ } B;\r
+ } PS0;\r
+\r
+ union { /* Peripheral Status 1 (Base+0x0064)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t S_CANSAMPLER:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_CTUL:1;\r
+ vuint32_t :1;\r
+ vuint32_t S_LINFLEX7:1;\r
+ vuint32_t S_LINFLEX6:1;\r
+ vuint32_t S_LINFLEX5:1;\r
+ vuint32_t S_LINFLEX4:1;\r
+ vuint32_t S_LINFLEX3:1;\r
+ vuint32_t S_LINFLEX2:1;\r
+ vuint32_t S_LINFLEX1:1;\r
+ vuint32_t S_LINFLEX0:1;\r
+ vuint32_t :3;\r
+ vuint32_t S_I2C0:1;\r
+ vuint32_t :10;\r
+ vuint32_t S_ADC1:1;\r
+ vuint32_t S_ADC0:1;\r
+ } B;\r
+ } PS1;\r
+\r
+ union { /* Peripheral Status 2 (Base+0x0068) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t S_PIT_RTI:1;\r
+ vuint32_t S_RTC_API:1;\r
+ vuint32_t :16;\r
+ vuint32_t S_EMIOS1:1;\r
+ vuint32_t S_EMIOS0:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_WKPU:1; \r
+ vuint32_t S_SIUL:1;\r
+ vuint32_t :4;\r
+ } B;\r
+ } PS2;\r
+\r
+ union { /* Peripheral Status 3 (Base+0x006C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :23;\r
+ vuint32_t S_CMU:1;\r
+ vuint32_t :8;\r
+ } B;\r
+ } PS3;\r
+\r
+ vuint8_t ME_reserved4[16]; /* reserved 16 bytes (Base+0x0070-0x007F) */\r
+\r
+ union { /* RUN Peripheral Config 0..7 (+0x0080-009C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t RUN3:1;\r
+ vuint32_t RUN2:1;\r
+ vuint32_t RUN1:1;\r
+ vuint32_t RUN0:1;\r
+ vuint32_t DRUN:1;\r
+ vuint32_t SAFE:1;\r
+ vuint32_t TEST:1;\r
+ vuint32_t RESET:1;\r
+ } B;\r
+ } RUNPC[8];\r
+\r
+ union { /* Low Pwr Periph Config 0..7 (+0x00A0-0x00BC) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :18;\r
+ vuint32_t STANDBY0:1;\r
+ vuint32_t :2;\r
+ vuint32_t STOP0:1;\r
+ vuint32_t :1;\r
+ vuint32_t HALT0:1;\r
+ vuint32_t :8;\r
+ } B;\r
+ } LPPC[8];\r
+\r
+\r
+ /* Note on PCTL registers: There are only some PCTL implemented in */\r
+ /* Bolero 1.5M/1M. In order to make the PCTL easily addressable, these */\r
+ /* are defined as an array (ie ME.PCTL[x].R). This means you have */\r
+ /* to be careful when addressing these registers in order not to */\r
+ /* access a PCTL that is not implemented. Following are available: */\r
+ /* 104, 92, 91, 73, 72, 69, 68, 60, 57, 55, 53, 51, 50, 49,48, */\r
+ /* 44, 33, 32, 23, 21-16, 13, 12, 9-4 */\r
+\r
+ union { /* Peripheral Control 0..143 (+0x00C0-0x014F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t DBG_F:1;\r
+ vuint8_t LP_CFG:3;\r
+ vuint8_t RUN_CFG:3;\r
+ } B;\r
+ } PCTL[105];\r
+\r
+}; /* end of ME_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : CGM */\r
+/****************************************************************************/\r
+struct CGM_tag{\r
+ /*\r
+ The "CGM" has fairly wide coverage and essentially includes everything in\r
+\r
+ chapter 9 of the Bolero Reference Manual:\r
+\r
+ Base Address | Clock Sources\r
+\r
+ ----------------------------- \r
+\r
+ 0xC3FE0000 | FXOSC_CTL\r
+\r
+ 0xC3FE0040 | SXOSC_CTL\r
+\r
+ 0xC3FE0060 | FIRC_CTL\r
+\r
+ 0xC3FE0080 | SIRC_CTL\r
+\r
+ 0xC3FE00A0 | FMPLL\r
+\r
+ 0xC3FE00C0 | CGM Block 1\r
+\r
+ 0xC3FE0100 | CMU \r
+\r
+ 0xC3FE0120 | CGM Block 2\r
+\r
+\r
+\r
+ In this header file, "Base" referrs to the 1st address, 0xC3FE_0000 \r
+\r
+ */\r
+ /* FXOSC - 0xC3FE_0000*/\r
+ union { /* Fast OSC Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OSCBYP:1;\r
+ vuint32_t :7;\r
+ vuint32_t EOCV:8;\r
+ vuint32_t M_OSC:1;\r
+ vuint32_t :2;\r
+ vuint32_t OSCDIV:5;\r
+ vuint32_t I_OSC:1;\r
+ vuint32_t:7;\r
+ } B;\r
+ } FXOSC_CTL;\r
+\r
+\r
+ /* Reserved Space between end of FXOSC and start SXOSC */\r
+ vuint8_t CGM_reserved0[60]; /* Reserved 60 bytes (Base+0x0004-0x003F) */\r
+\r
+\r
+ /* SXOSC - 0xC3FE_0040*/\r
+ union { /* Slow Osc Control (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OSCBYP:1;\r
+ vuint32_t :7;\r
+ vuint32_t EOCV:8;\r
+ vuint32_t M_OSC:1;\r
+ vuint32_t :2;\r
+ vuint32_t OSCDIV:5;\r
+ vuint32_t I_OSC:1;\r
+ vuint32_t :5;\r
+ vuint32_t S_OSC:1;\r
+ vuint32_t OSCON:1;\r
+ } B;\r
+ } SXOSC_CTL;\r
+\r
+\r
+ /* Reserved space between end of SXOSC and start of FIRC */\r
+ vuint8_t CGM_reserved1[28]; /*Reserved 28 bytes (Base+0x0044-0x005F) */\r
+\r
+\r
+ /* FIRC - 0xC3FE_0060 */\r
+ union { /* Fast IRC Control (Base+0x0060) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :10;\r
+ vuint32_t RCTRIM:6;\r
+ vuint32_t :3;\r
+ vuint32_t RCDIV:5;\r
+ vuint32_t :2;\r
+ vuint32_t FIRCON_STDBY:1;\r
+ vuint32_t :5;\r
+ } B;\r
+ } FIRC_CTL;\r
+\r
+\r
+ /* Reserved space between end of FIRC and start of SIRC */\r
+ vuint8_t CGM_reserved2[28]; /*Reserved 28 bytes (Base+0x0064-0x007F) */\r
+\r
+\r
+ /* SIRC - 0xC3FE_0080 */\r
+ union { /* Slow IRC Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :11;\r
+ vuint32_t SIRCTRIM:5;\r
+ vuint32_t :3;\r
+ vuint32_t SIRCDIV:5;\r
+ vuint32_t :3;\r
+ vuint32_t S_SIRC:1;\r
+ vuint32_t :3;\r
+ vuint32_t SIRCON_STDBY:1;\r
+ } B;\r
+ } SIRC_CTL;\r
+\r
+\r
+ /* Reserved space between end of SIRC and start of FMPLL */\r
+ vuint8_t CGM_reserved3[28]; /*Reserved 28 bytes (Base+0x0084-0x009F) */\r
+\r
+\r
+ /* FMPLL - 0xC3FE_00A0 */\r
+ union { /* FMPLL Control (Base+0x00A0) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t IDF:4;\r
+ vuint32_t ODF:2;\r
+ vuint32_t:1;\r
+ vuint32_t NDIV:7;\r
+ vuint32_t:7;\r
+ vuint32_t EN_PLL_SW:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t UNLOCK_ONCE:1;\r
+ vuint32_t:1;\r
+ vuint32_t I_LOCK:1;\r
+ vuint32_t S_LOCK:1;\r
+ vuint32_t PLL_FAIL_MASK:1;\r
+ vuint32_t PLL_FAIL_FLAG:1;\r
+ vuint32_t:1;\r
+ } B;\r
+ } FMPLL_CR;\r
+\r
+ union { /* FMPLL Modulation (Base+0x00A4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t STRB_BYPASS:1;\r
+ vuint32_t :1;\r
+ vuint32_t SPRD_SEL:1;\r
+ vuint32_t MOD_PERIOD:13;\r
+ vuint32_t FM_EN:1;\r
+ vuint32_t INC_STEP:15;\r
+ } B;\r
+ } FMPLL_MR;\r
+\r
+\r
+ /* Reserved space between end of FMPLL and start of CGM Block 1 */\r
+ vuint8_t CGM_reserved4[88]; /*Reserved 88 bytes (Base+0x00A8-0x00FF) */\r
+\r
+ /* CMU - 0xC3FE_0100 */\r
+ union { /* CMU Control Status (Base+0x0100) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t SFM:1;\r
+ vuint32_t :13;\r
+ vuint32_t CLKSEL1:2;\r
+ vuint32_t :5;\r
+ vuint32_t RCDIV:2;\r
+ vuint32_t CME_A:1;\r
+ } B;\r
+ } CMU_CSR;\r
+\r
+ union { /* CMU Frequency Display (Base+0x0104) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :12;\r
+ vuint32_t FD:20;\r
+ } B;\r
+ } CMU_FDR;\r
+\r
+ union { /* CMU High Freq Reference FMPLL (Base+0x0108) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t HFREF:12;\r
+ } B;\r
+ } CMU_HFREFR;\r
+\r
+ union { /* CMU Low Freq Reference FMPLL (Base+0x010C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t LFREF:12;\r
+ } B;\r
+ } CMU_LFREFR;\r
+\r
+ union { /* CMU Interrupt Status (Base+0x0110) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :29;\r
+ vuint32_t FHHI:1; // *_A not present in RM\r
+ vuint32_t FLLI:1; // *_A not present in RM\r
+ vuint32_t OLRI:1;\r
+ } B;\r
+ } CMU_ISR;\r
+\r
+ /* Reserved space where IMR was previously positioned */\r
+ vuint8_t CGM_reserved5[4]; /*Reserved 4 bytes (Base+0x0114-0x0117) */\r
+\r
+ union { /* CMU Measurement Duration (Base+0x0118) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :12;\r
+ vuint32_t MD:20;\r
+ } B;\r
+ } CMU_MDR;\r
+\r
+\r
+ /* Reserved space between end of CMU and start of CGM Block 2 */\r
+ vuint8_t CGM_reserved6[596]; /*Reserved 596 bytes (Base+0x011C-0x036F) */\r
+\r
+ union { /* GCM Output Clock Enable (Base+0x0370) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t EN:1;\r
+ } B;\r
+ } OC_EN;\r
+\r
+ union { /* CGM Output Clock Division Sel (Base+0x0374) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :2;\r
+ vuint32_t SELDIV:2;\r
+ vuint32_t SELCTL:4;\r
+ vuint32_t :24;\r
+ } B;\r
+ } OCDS_SC;\r
+\r
+ union { /* CGM System Clock Select Status (Base+0x0378) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t SELSTAT:4;\r
+ vuint32_t :24;\r
+ } B;\r
+ } SC_SS;\r
+\r
+ union { /* CGM Sys Clk Div Config 0.2 (0x037C-0x037E) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t DE:1;\r
+ vuint8_t :3;\r
+ vuint8_t DIV:4;\r
+ } B;\r
+ } SC_DC[3];\r
+ \r
+ union { /* CGM Aux clock select control register (Base+0x0380) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t SELCTL:4;\r
+ vuint32_t :24;\r
+ } B;\r
+ } AC0_SC;\r
+\r
+ // vuint8_t CGM_reserved7[15489]; /*Reserved 1 byte (Base+0x037F - 0x3FFF) */\r
+\r
+}; /* end of CGM_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : RGM base address - 0xC3FE_4000 */\r
+/****************************************************************************/\r
+struct RGM_tag{\r
+\r
+ union { /* Functional Event Status (Base+0x0000) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t F_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t F_FLASH:1;\r
+ vuint16_t F_LVD45:1;\r
+ vuint16_t F_CMU_FHL:1;\r
+ vuint16_t F_CMU_OLR:1;\r
+ vuint16_t F_FMPLL:1;\r
+ vuint16_t F_CHKSTOP:1;\r
+ vuint16_t F_SOFT:1;\r
+ vuint16_t F_CORE:1;\r
+ vuint16_t F_JTAG:1;\r
+ } B;\r
+ } FES;\r
+\r
+ union { /* Destructive Event Status (Base+0x0002) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t F_POR:1;\r
+ vuint16_t :10;\r
+ vuint16_t F_LVD27_VREG:1;\r
+ vuint16_t F_LVD27:1;\r
+ vuint16_t F_SWT:1;\r
+ vuint16_t F_LVD12_PD1:1;\r
+ vuint16_t F_LVD12_PD0:1;\r
+ } B;\r
+ } DES;\r
+\r
+ union { /* Functional Event Reset Disable (+0x0004) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t D_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t D_FLASH:1;\r
+ vuint16_t D_LVD45:1;\r
+ vuint16_t D_CMU_FHL:1;\r
+ vuint16_t D_CMU_OLR:1;\r
+ vuint16_t D_FMPLL:1;\r
+ vuint16_t D_CHKSTOP:1;\r
+ vuint16_t D_SOFT:1;\r
+ vuint16_t D_CORE:1;\r
+ vuint16_t D_JTAG:1;\r
+ } B;\r
+ } FERD;\r
+\r
+ union { /* Destructive Event Reset Disable (Base+0x0006)*/\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :11;\r
+ vuint16_t D_LVD27_VREG:1;\r
+ vuint16_t D_LVD27:1;\r
+ vuint16_t D_SWT:1;\r
+ vuint16_t D_LVD12_PD1:1;\r
+ vuint16_t D_LVD12_PD0:1;\r
+ } B;\r
+ } DERD;\r
+\r
+ vuint8_t RGM_reserved0[8]; /*Reserved 8 bytes (Base+0x008-0x000F) */\r
+\r
+ union { /* Functional Event Alt Request (Base+0x0010) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t AR_EXR:1;\r
+ vuint16_t:6;\r
+ vuint16_t AR_FLASH:1;\r
+ vuint16_t AR_LVD45:1;\r
+ vuint16_t AR_CMU_FHL:1;\r
+ vuint16_t AR_CMU_OLR:1;\r
+ vuint16_t AR_FMPLL:1;\r
+ vuint16_t AR_CHKSTOP:1;\r
+ vuint16_t AR_SOFT:1;\r
+ vuint16_t AR_CORE:1;\r
+ vuint16_t AR_JTAG:1;\r
+ } B;\r
+ } FEAR;\r
+ \r
+ union { /* Destructive Event Alt Request (Base+0x0012) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:11;\r
+ vuint16_t AR_LVD27_VREG:1;\r
+ vuint16_t AR_LVD27:1;\r
+ vuint16_t AR_SWT:1;\r
+ vuint16_t AR_LVD12_PD1:1;\r
+ vuint16_t AR_LVD12_PD0:1;\r
+ } B;\r
+ } DEAR; /* Destructive Event Alternate Request */\r
+\r
+ vuint8_t RGM_reserved1[4]; /*Reserved 4 bytes (Base+0x0014-0x0017) */\r
+\r
+ union { /* Functional Event Short Sequence (+0x0018) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t SS_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t SS_FLASH:1;\r
+ vuint16_t SS_LVD45:1;\r
+ vuint16_t SS_CMU_FHL:1;\r
+ vuint16_t SS_CMU_OLR:1;\r
+ vuint16_t SS_FMPLL:1;\r
+ vuint16_t SS_CHKSTOP:1;\r
+ vuint16_t SS_SOFT:1;\r
+ vuint16_t SS_CORE:1;\r
+ vuint16_t SS_JTAG:1;\r
+ } B;\r
+ } FESS;\r
+\r
+ union { /* STANDBY reset sequence (Base+0x001A) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :8;\r
+ vuint16_t BOOT_FROM_BKP_RAM:1;\r
+ vuint16_t :7;\r
+ } B;\r
+ } STDBY;\r
+\r
+ union { /* Functional Bidirectional Reset En (+0x001C) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t BE_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t BE_FLASH:1;\r
+ vuint16_t BE_LVD45:1;\r
+ vuint16_t BE_CMU_FHL:1;\r
+ vuint16_t BE_CMU_OLR:1;\r
+ vuint16_t BE_FMPLL:1;\r
+ vuint16_t BE_CHKSTOP:1;\r
+ vuint16_t BE_SOFT:1;\r
+ vuint16_t BE_CORE:1;\r
+ vuint16_t BE_JTAG:1;\r
+ } B;\r
+ } FBRE;\r
+\r
+}; /* end of RGM_tag */\r
+/****************************************************************************/\r
+/* MODULE : PCU (base address 0xC3FE_8000) */\r
+/****************************************************************************/\r
+struct PCU_tag{\r
+\r
+ union { /* PCU Power domain 0-3 config (+0x0000-0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :18;\r
+ vuint32_t STBY0:1;\r
+ vuint32_t :2;\r
+ vuint32_t STOP0:1;\r
+ vuint32_t :1;\r
+ vuint32_t HALT0:1;\r
+ vuint32_t RUN3:1;\r
+ vuint32_t RUN2:1;\r
+ vuint32_t RUN1:1;\r
+ vuint32_t RUN0:1;\r
+ vuint32_t DRUN:1;\r
+ vuint32_t SAFE:1;\r
+ vuint32_t TEST:1;\r
+ vuint32_t RST:1;\r
+ } B;\r
+ } PCONF[4];\r
+\r
+ vuint8_t PCU_reserved0[48]; /* Reserved 48 bytes (Base+0x0010-0x003F) */\r
+\r
+ union { /* PCU Power Domain Status (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t PD3:1;\r
+ vuint32_t PD2:1;\r
+ vuint32_t PD1:1;\r
+ vuint32_t PD0:1;\r
+ } B;\r
+ } PSTAT;\r
+\r
+ vuint8_t PCU_reserved1[60]; /* Reserved 60 bytes (Base+0x0044-0x007F) */\r
+\r
+\r
+ /* Following register is from Voltage Regulators chapter of RM */\r
+\r
+ union { /* PCU Voltage Regulator Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t MASK_LVDHV5:1;\r
+ } B;\r
+ } VREG_CTL; /* Changed from VCTL for consistency with other regs here */\r
+\r
+ }; /* end of PCU_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : CTU Lite(base address - 0xFFE6_4000) */\r
+/****************************************************************************/\r
+struct CTUL_tag{\r
+\r
+ // union { /* CTU Control Status Register (Base+0x0000)NOT PRESENT WITHIN RM*/\r
+ // vuint32_t R;\r
+ // struct {\r
+ // vuint32_t :24;\r
+ // vuint32_t TRGIEN:1;\r
+ // vuint32_t TRGI:1;\r
+ // vuint32_t :6;\r
+ // } B;\r
+ // } CSR;\r
+\r
+ vuint8_t CTU_reserved[48]; /* Reserved 48 bytes (Base+0x0000-0x002F) */\r
+\r
+ union { /* Event Config 0..63 (Base+0x0030-0x012C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t TM:1;\r
+ vuint32_t CLR_FLAG:1;\r
+ vuint32_t :5;\r
+ vuint32_t ADC_SEL:1;\r
+ vuint32_t :1;\r
+ vuint32_t CHANNEL_VALUE:7;\r
+ } B;\r
+ } EVTCFGR[64];\r
+\r
+\r
+}; /* end of CTUL_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : EMIOS (base address - eMIOS0 0xC3FA_0000; eMIOS1 0xC3FA_4000) */\r
+/****************************************************************************/\r
+\r
+struct EMIOS_CHANNEL_tag{\r
+\r
+ union { /* Channel A Data (UCn Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t A:16;\r
+ } B;\r
+ } CADR;\r
+\r
+ union { /* Channel B Data (UCn Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t B:16;\r
+ } B;\r
+ } CBDR;\r
+\r
+ union { /* Channel Counter (UCn Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t C:16;\r
+ } B;\r
+ } CCNTR;\r
+\r
+ union { /* Channel Control (UCn Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FREN:1;\r
+ vuint32_t ODIS:1;\r
+ vuint32_t ODISSL:2;\r
+ vuint32_t UCPRE:2;\r
+ vuint32_t UCPEN:1;\r
+ vuint32_t DMA:1;\r
+ vuint32_t :1;\r
+ vuint32_t IF:4;\r
+ vuint32_t FCK:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t :3;\r
+ vuint32_t FORCMA:1;\r
+ vuint32_t FORCMB:1;\r
+ vuint32_t :1;\r
+ vuint32_t BSL:2;\r
+ vuint32_t EDSEL:1;\r
+ vuint32_t EDPOL:1;\r
+ vuint32_t MODE:7;\r
+ } B;\r
+ } CCR;\r
+\r
+ union { /* Channel Status (UCn Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OVR:1;\r
+ vuint32_t :15;\r
+ vuint32_t OVFL:1;\r
+ vuint32_t :12;\r
+ vuint32_t UCIN:1;\r
+ vuint32_t UCOUT:1;\r
+ vuint32_t FLAG:1;\r
+ } B;\r
+ } CSR;\r
+\r
+ union { /* Alternate Channel A Data (UCn Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t ALTA:16;\r
+ } B;\r
+ } ALTCADR;\r
+\r
+ vuint8_t EMIOS_CHANNEL_reserved0[8]; /* (UCn Base + (0x0018-0x001F) */\r
+\r
+}; /* end of EMIOS_CHANNEL_tag */\r
+\r
+\r
+struct EMIOS_tag{\r
+\r
+ union { /* Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t GTBE:1;\r
+ vuint32_t :1;\r
+ vuint32_t GPREN:1;\r
+ vuint32_t :10;\r
+ vuint32_t GPRE:8;\r
+ vuint32_t :8;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* Global Flag (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t F31:1;\r
+ vuint32_t F30:1;\r
+ vuint32_t F29:1;\r
+ vuint32_t F28:1;\r
+ vuint32_t F27:1;\r
+ vuint32_t F26:1;\r
+ vuint32_t F25:1;\r
+ vuint32_t F24:1;\r
+ vuint32_t F23:1;\r
+ vuint32_t F22:1;\r
+ vuint32_t F21:1;\r
+ vuint32_t F20:1;\r
+ vuint32_t F19:1;\r
+ vuint32_t F18:1;\r
+ vuint32_t F17:1;\r
+ vuint32_t F16:1;\r
+ vuint32_t F15:1;\r
+ vuint32_t F14:1;\r
+ vuint32_t F13:1;\r
+ vuint32_t F12:1;\r
+ vuint32_t F11:1;\r
+ vuint32_t F10:1;\r
+ vuint32_t F9:1;\r
+ vuint32_t F8:1;\r
+ vuint32_t F7:1;\r
+ vuint32_t F6:1;\r
+ vuint32_t F5:1;\r
+ vuint32_t F4:1;\r
+ vuint32_t F3:1;\r
+ vuint32_t F2:1;\r
+ vuint32_t F1:1;\r
+ vuint32_t F0:1;\r
+ } B;\r
+ } GFR;\r
+\r
+ union { /* Output Update Disable (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OU31:1;\r
+ vuint32_t OU30:1;\r
+ vuint32_t OU29:1;\r
+ vuint32_t OU28:1;\r
+ vuint32_t OU27:1;\r
+ vuint32_t OU26:1;\r
+ vuint32_t OU25:1;\r
+ vuint32_t OU24:1;\r
+ vuint32_t OU23:1;\r
+ vuint32_t OU22:1;\r
+ vuint32_t OU21:1;\r
+ vuint32_t OU20:1;\r
+ vuint32_t OU19:1;\r
+ vuint32_t OU18:1;\r
+ vuint32_t OU17:1;\r
+ vuint32_t OU16:1;\r
+ vuint32_t OU15:1;\r
+ vuint32_t OU14:1;\r
+ vuint32_t OU13:1;\r
+ vuint32_t OU12:1;\r
+ vuint32_t OU11:1;\r
+ vuint32_t OU10:1;\r
+ vuint32_t OU9:1;\r
+ vuint32_t OU8:1;\r
+ vuint32_t OU7:1;\r
+ vuint32_t OU6:1;\r
+ vuint32_t OU5:1;\r
+ vuint32_t OU4:1;\r
+ vuint32_t OU3:1;\r
+ vuint32_t OU2:1;\r
+ vuint32_t OU1:1;\r
+ vuint32_t OU0:1;\r
+ } B;\r
+ } OUDR;\r
+\r
+ union { /* Disable Channel (Base+0x000F) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CHDIS31:1;\r
+ vuint32_t CHDIS30:1;\r
+ vuint32_t CHDIS29:1;\r
+ vuint32_t CHDIS28:1;\r
+ vuint32_t CHDIS27:1;\r
+ vuint32_t CHDIS26:1;\r
+ vuint32_t CHDIS25:1;\r
+ vuint32_t CHDIS24:1;\r
+ vuint32_t CHDIS23:1;\r
+ vuint32_t CHDIS22:1;\r
+ vuint32_t CHDIS21:1;\r
+ vuint32_t CHDIS20:1;\r
+ vuint32_t CHDIS19:1;\r
+ vuint32_t CHDIS18:1;\r
+ vuint32_t CHDIS17:1;\r
+ vuint32_t CHDIS16:1;\r
+ vuint32_t CHDIS15:1;\r
+ vuint32_t CHDIS14:1;\r
+ vuint32_t CHDIS13:1;\r
+ vuint32_t CHDIS12:1;\r
+ vuint32_t CHDIS11:1;\r
+ vuint32_t CHDIS10:1;\r
+ vuint32_t CHDIS9:1;\r
+ vuint32_t CHDIS8:1;\r
+ vuint32_t CHDIS7:1;\r
+ vuint32_t CHDIS6:1;\r
+ vuint32_t CHDIS5:1;\r
+ vuint32_t CHDIS4:1;\r
+ vuint32_t CHDIS3:1;\r
+ vuint32_t CHDIS2:1;\r
+ vuint32_t CHDIS1:1;\r
+ vuint32_t CHDIS0:1;\r
+ } B;\r
+ } UCDIS;\r
+\r
+ vuint8_t EMIOS_reserved0[16]; /* Reserved 16 Bytes (Base+0x0010-0x001F) */\r
+\r
+ struct EMIOS_CHANNEL_tag CH[32]; /* Add in 32 unified channels */\r
+\r
+ vuint8_t EMIOS_reserved1[3040]; /* 3040 bytes (Base+0x0420-0x0FFF) */\r
+\r
+}; /* end of EMIOS_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : PIT (base address - 0xC3FF_FFFF) */\r
+/****************************************************************************/\r
+ struct PIT_tag {\r
+\r
+ union { /* PIT Module Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ } B;\r
+ } PITMCR;\r
+\r
+ vuint8_t PIT_reserved0[252]; /* Reserved 252 Bytes (Base+0x0004-0x00FF) */\r
+\r
+ /* PIT Timer Channels 0..7 (Base+0x0100-0x017C) */\r
+ struct {\r
+\r
+ union { /* PIT Timer Load Value (Offset+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSV:32;\r
+ } B;\r
+ } LDVAL;\r
+\r
+ union { /* PIT Current Timer Value (Offset+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TVL:32;\r
+ } B;\r
+ } CVAL;\r
+\r
+ union { /* PIT Timer Control (Offset+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :30;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } TCTRL;\r
+\r
+ union { /* PIT Timer Control (Offset+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } TFLG;\r
+\r
+ }CH[8]; /* End of PIT Timer Channels */\r
+\r
+}; /* end of PIT_tag */\r
+/****************************************************************************/\r
+/* MODULE : I2C (base address - 0xFFE3_0000) */\r
+/****************************************************************************/\r
+struct I2C_tag{\r
+\r
+ union { /* I2C Bus Address (Base+0x0000) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ADR:7;\r
+ vuint8_t :1;\r
+ } B;\r
+ } IBAD;\r
+\r
+ union { /* I2C Bus Frequency Divider (Base+0x0001) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t IBC:8;\r
+ } B;\r
+ } IBFD;\r
+\r
+ union { /* I2C Bus Control (Base+0x0002) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t MDIS:1;\r
+ vuint8_t IBIE:1;\r
+ vuint8_t MS:1; /*different from RM for backward compatiblity MSSL in RM*/ \r
+ vuint8_t TX:1;\r
+ vuint8_t NOACK:1;\r
+ vuint8_t RSTA:1;\r
+ vuint8_t DMAEN:1;\r
+ vuint8_t :1;\r
+ } B;\r
+ } IBCR;\r
+\r
+ union { /* I2C Bus Status (Base+0x0003) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t TCF:1;\r
+ vuint8_t IAAS:1;\r
+ vuint8_t IBB:1;\r
+ vuint8_t IBAL:1;\r
+ vuint8_t :1;\r
+ vuint8_t SRW:1;\r
+ vuint8_t IBIF:1;\r
+ vuint8_t RXAK:1;\r
+ } B;\r
+ } IBSR;\r
+\r
+ union { /* I2C Bus Data I/O (Base+0x0004) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t DATA:8;\r
+ } B;\r
+ } IBDR;\r
+\r
+ union { /* I2C Interrupt Configuration (Base+0x0005) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t BIIE:1;\r
+ vuint8_t :7;\r
+ } B;\r
+ } IBIC;\r
+\r
+ vuint8_t I2C_reserved0[16378]; /* Reserved 16378 (Base+0x0006-0x3FFF) */\r
+\r
+}; /* end of i2c_tag */\r
+/****************************************************************************/\r
+/* MODULE : MPU (base address - 0xFFF1_0000) */\r
+/****************************************************************************/\r
+ struct MPU_tag {\r
+\r
+ union { /* Control/Error Status (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :5;\r
+ vuint32_t SPERR:3;\r
+ vuint32_t:4;\r
+ vuint32_t HRL:4;\r
+ vuint32_t NSP:4;\r
+ vuint32_t NGRD:4;\r
+ vuint32_t :7;\r
+ vuint32_t VLD:1;\r
+ } B;\r
+ } CESR;\r
+\r
+ vuint8_t MPU_reserved0[12]; /* Reserved 12 Bytes (Base+0x0004-0x000F) */\r
+\r
+\r
+ union { /* Error Address Slave Port0 (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR0;\r
+\r
+ union { /* Error Detail Slave Port0 (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EACD:8;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR0;\r
+\r
+\r
+ union { /* Error Address Slave Port1 (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR1;\r
+\r
+ union { /* Error Detail Slave Port1 (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EACD:8;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR1;\r
+\r
+\r
+ union { /* Error Address Slave Port2 (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR2;\r
+\r
+ union { /* Error Detail Slave Port2 (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EACD:8;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR2;\r
+\r
+ vuint8_t MPU_reserved1[984]; /* Reserved 984 Bytes (Base+0x0028-0x03FF) */\r
+\r
+ struct { /* Region Descriptor 0..15 (Base+0x0400-0x0470) */\r
+\r
+ union { /* - Word 0 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SRTADDR:27;\r
+ vuint32_t :5;\r
+ } B;\r
+ } WORD0;\r
+\r
+ union { /* - Word 1 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ENDADDR:27;\r
+ vuint32_t :5;\r
+ } B;\r
+ } WORD1;\r
+\r
+ union { /* - Word 2 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t M7RE:1;\r
+ vuint32_t M7WE:1;\r
+ vuint32_t M6RE:1;\r
+ vuint32_t M6WE:1;\r
+ vuint32_t M5RE:1;\r
+ vuint32_t M5WE:1;\r
+ vuint32_t M4RE:1;\r
+ vuint32_t M4WE:1;\r
+ vuint32_t M3PE:1;\r
+ vuint32_t M3SM:2;\r
+ vuint32_t M3UM:3;\r
+ vuint32_t M2PE:1;\r
+ vuint32_t M2SM:2;\r
+ vuint32_t M2UM:2;\r
+ vuint32_t :7; \r
+ vuint32_t M0PE:1;\r
+ vuint32_t M0SM:2;\r
+ vuint32_t M0UM:3;\r
+ } B;\r
+ } WORD2;\r
+\r
+ union { /* - Word 3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PID:8;\r
+ vuint32_t PIDMASK:8;\r
+ vuint32_t :15;\r
+ vuint32_t VLD:1;\r
+ } B;\r
+ } WORD3;\r
+\r
+ }RGD[8]; /* End of Region Descriptor Structure) */\r
+\r
+ vuint8_t MPU_reserved2[896]; /* Reserved 896 Bytes (Base+0x0480-0x07FF) */\r
+\r
+ union { /* Region Descriptor Alt 0..15 (0x0800-0x081C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t M7RE:1;\r
+ vuint32_t M7WE:1;\r
+ vuint32_t M6RE:1;\r
+ vuint32_t M6WE:1;\r
+ vuint32_t M5RE:1;\r
+ vuint32_t M5WE:1;\r
+ vuint32_t M4RE:1;\r
+ vuint32_t M4WE:1;\r
+ vuint32_t M3PE:1;\r
+ vuint32_t M3SM:2;\r
+ vuint32_t M3UM:3;\r
+ vuint32_t M2PE:1;\r
+ vuint32_t M2SM:2;\r
+ vuint32_t M2UM:2;\r
+ vuint32_t :7; \r
+ vuint32_t M0PE:1;\r
+ vuint32_t M0SM:2;\r
+ vuint32_t M0UM:3;\r
+ } B;\r
+ } RGDAAC[8];\r
+\r
+ vuint8_t MPU_reserved3[14304]; /* Reserved 14304 Bytes (+0x0820-0x03FFF) */\r
+\r
+}; /* end of MPU_tag */\r
+/****************************************************************************/\r
+/* MODULE : eDMA (base address - 0xFFF4_4000) */\r
+/****************************************************************************/\r
+\r
+ /*for "standard" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=0) */\r
+ struct EDMA_TCD_STD_tag {\r
+\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (?minor?) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITER:15;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */\r
+ vuint16_t BITER:15;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+\r
+ }; /* end of EDMA_TCD_STD_tag */\r
+\r
+ /*for "channel link" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=1)*/\r
+ struct EDMA_TCD_CHLINK_tag {\r
+\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (?minor?) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITERLINKCH:6;\r
+ vuint16_t CITER:9;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning (?major?) iteration count */\r
+ vuint16_t BITERLINKCH:6;\r
+ vuint16_t BITER:9;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+\r
+ }; /* end of EDMA_TCD_CHLINK_tag */\r
+\r
+\r
+\r
+struct EDMA_tag {\r
+\r
+ union { /* Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :14;\r
+ vuint32_t CX:1;\r
+ vuint32_t ECX:1;\r
+ vuint32_t :6; \r
+ vuint32_t GRP0PRI:2;\r
+ vuint32_t EMLM:1;\r
+ vuint32_t CLM:1;\r
+ vuint32_t HALT:1;\r
+ vuint32_t HOE:1;\r
+ vuint32_t ERGA:1;\r
+ vuint32_t ERCA:1;\r
+ vuint32_t EDBG:1;\r
+ vuint32_t EBW:1;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* Error Status (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VLD:1;\r
+ vuint32_t :16;\r
+ vuint32_t CPE:1;\r
+ vuint32_t ERRCHN:6;\r
+ vuint32_t SAE:1;\r
+ vuint32_t SOE:1;\r
+ vuint32_t DAE:1;\r
+ vuint32_t DOE:1;\r
+ vuint32_t NCE:1;\r
+ vuint32_t SGE:1;\r
+ vuint32_t SBE:1;\r
+ vuint32_t DBE:1;\r
+ } B;\r
+ } ESR;\r
+\r
+ vuint8_t eDMA_reserved0[4]; /* Reserved 4 bytes (Base+0x0008-0x000B)*/\r
+\r
+ union { /* Enable Request Low Ch15..0 (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t ERQ15:1;\r
+ vuint32_t ERQ14:1;\r
+ vuint32_t ERQ13:1;\r
+ vuint32_t ERQ12:1;\r
+ vuint32_t ERQ11:1;\r
+ vuint32_t ERQ10:1;\r
+ vuint32_t ERQ09:1;\r
+ vuint32_t ERQ08:1;\r
+ vuint32_t ERQ07:1;\r
+ vuint32_t ERQ06:1;\r
+ vuint32_t ERQ05:1;\r
+ vuint32_t ERQ04:1;\r
+ vuint32_t ERQ03:1;\r
+ vuint32_t ERQ02:1;\r
+ vuint32_t ERQ01:1;\r
+ vuint32_t ERQ00:1;\r
+ } B;\r
+ } ERQRL;\r
+\r
+ vuint8_t eDMA_reserved1[4]; /* Reserved 4 bytes (Base+0x0010-0x0013)*/\r
+\r
+ union { /* Enable Error Interrupt Low (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t EEI15:1;\r
+ vuint32_t EEI14:1;\r
+ vuint32_t EEI13:1;\r
+ vuint32_t EEI12:1;\r
+ vuint32_t EEI11:1;\r
+ vuint32_t EEI10:1;\r
+ vuint32_t EEI09:1;\r
+ vuint32_t EEI08:1;\r
+ vuint32_t EEI07:1;\r
+ vuint32_t EEI06:1;\r
+ vuint32_t EEI05:1;\r
+ vuint32_t EEI04:1;\r
+ vuint32_t EEI03:1;\r
+ vuint32_t EEI02:1;\r
+ vuint32_t EEI01:1;\r
+ vuint32_t EEI00:1;\r
+ } B;\r
+ } EEIRL;\r
+\r
+ union { /* DMA Set Enable Request (Base+0x0018) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t SERQ:7;\r
+ } B;\r
+ } SERQR;\r
+\r
+ union { /* DMA Clear Enable Request (Base+0x0019) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CERQ:7;\r
+ } B;\r
+ } CERQR;\r
+\r
+ union { /* DMA Set Enable Error Interrupt (Base+0x001A) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t SEEI:7;\r
+ } B;\r
+ } SEEIR;\r
+\r
+ union { /* DMA Clr Enable Error Interrupt (Base+0x001B) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:1;\r
+ vuint8_t CEEI:7;\r
+ } B;\r
+ } CEEIR;\r
+\r
+ union { /* DMA Clear Interrupt Request (Base+0x001C) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CINT:7;\r
+ } B;\r
+ } CIRQR;\r
+\r
+ union { /* DMA Clear error (Base+0x001D) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CERR:7;\r
+ } B;\r
+ } CER;\r
+\r
+ union { /* DMA Set Start Bit (Base+0x001E) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t NOP:1;\r
+ vuint8_t SSB:7;\r
+ } B;\r
+ } SSBR;\r
+\r
+ union { /* DMA Clear Done Status Bit (Base+0x001F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CDSB:7;\r
+ } B;\r
+ } CDSBR;\r
+\r
+ vuint8_t eDMA_reserved2[4]; /* Reserved 4 bytes (Base+0x0020-0x0023)*/\r
+\r
+ union { /* DMA Interrupt Req Low Ch15..0 (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t INT15:1;\r
+ vuint32_t INT14:1;\r
+ vuint32_t INT13:1;\r
+ vuint32_t INT12:1;\r
+ vuint32_t INT11:1;\r
+ vuint32_t INT10:1;\r
+ vuint32_t INT09:1;\r
+ vuint32_t INT08:1;\r
+ vuint32_t INT07:1;\r
+ vuint32_t INT06:1;\r
+ vuint32_t INT05:1;\r
+ vuint32_t INT04:1;\r
+ vuint32_t INT03:1;\r
+ vuint32_t INT02:1;\r
+ vuint32_t INT01:1;\r
+ vuint32_t INT00:1;\r
+ } B;\r
+ } IRQRL;\r
+\r
+ vuint8_t eDMA_reserved3[4]; /* Reserved 4 bytes (Base+0x0028-0x002B)*/\r
+\r
+ union { /* DMA Error Low Ch15..0 (Base+0x002C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t ERR15:1;\r
+ vuint32_t ERR14:1;\r
+ vuint32_t ERR13:1;\r
+ vuint32_t ERR12:1;\r
+ vuint32_t ERR11:1;\r
+ vuint32_t ERR10:1;\r
+ vuint32_t ERR09:1;\r
+ vuint32_t ERR08:1;\r
+ vuint32_t ERR07:1;\r
+ vuint32_t ERR06:1;\r
+ vuint32_t ERR05:1;\r
+ vuint32_t ERR04:1;\r
+ vuint32_t ERR03:1;\r
+ vuint32_t ERR02:1;\r
+ vuint32_t ERR01:1;\r
+ vuint32_t ERR00:1;\r
+ } B;\r
+ } ERL;\r
+\r
+ vuint8_t eDMA_reserved4[4]; /* Reserved 4 bytes (Base+0x0030-0x0033)*/\r
+\r
+ union { /* DMA Hardware Request Stat Low (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t HRS15:1;\r
+ vuint32_t HRS14:1;\r
+ vuint32_t HRS13:1;\r
+ vuint32_t HRS12:1;\r
+ vuint32_t HRS11:1;\r
+ vuint32_t HRS10:1;\r
+ vuint32_t HRS09:1;\r
+ vuint32_t HRS08:1;\r
+ vuint32_t HRS07:1;\r
+ vuint32_t HRS06:1;\r
+ vuint32_t HRS05:1;\r
+ vuint32_t HRS04:1;\r
+ vuint32_t HRS03:1;\r
+ vuint32_t HRS02:1;\r
+ vuint32_t HRS01:1;\r
+ vuint32_t HRS00:1;\r
+ } B;\r
+ } HRSL;\r
+\r
+ vuint8_t eDMA_reserved5[200]; /* Reserved 200 bytes (Base+0x0038-0x00FF)*/\r
+\r
+ union { /* Channel n Priority (Base+0x0100-0x010F)*/\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ECP:1;\r
+ vuint8_t DPA:1;\r
+ vuint8_t GRPPRI:2;\r
+ vuint8_t CHPRI:4;\r
+ } B;\r
+ } CPR[16];\r
+\r
+ vuint8_t eDMA_reserved6[3824]; /* Reserved 3808 bytes (+0x0110-0x0FFF) */\r
+\r
+ /* Transfer Control Descriptors 0..16 (Base+0x1000-0x11E0) */\r
+ struct EDMA_TCD_STD_tag TCD[16];\r
+ \r
+ /* or change to following if using channel linking */\r
+ /* Struct EDMA_TCD_CHLINK_tag TCD[16]; */\r
+ \r
+ vuint8_t eDMA_reserved7[28160]; /* Reserved 28160 bytes (+0x1200-0x7FFF) */\r
+\r
+}; /* end of EDMA_tag */\r
+/*************************************************************************/\r
+/* MODULE : INTC (base address - 0xFFF4_8000) */\r
+/*************************************************************************/\r
+struct INTC_tag {\r
+\r
+ union { /* INTC Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t VTES:1;\r
+ vuint32_t:4;\r
+ vuint32_t HVEN:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ vuint8_t INTC_reserved0[4]; /* reserved 4 bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* INTC Current Priority (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t PRI:4;\r
+ } B;\r
+ } CPR;\r
+ \r
+ vuint8_t INTC_reserved1[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */\r
+\r
+ union { /* INTC Interrupt Acknowledge (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VTBA_PRC0:21;\r
+ vuint32_t INTVEC_PRC0:9;\r
+ vuint32_t:2;\r
+ } B;\r
+ } IACKR;\r
+\r
+ vuint8_t INTC_reserved2[4]; /* Reserved 4 bytes (Base+0x0014-0x0017) */\r
+ \r
+ union { /* INTC End Of Interrupt (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } EOIR;\r
+\r
+ vuint8_t INTC_reserved3[4]; /* reserved 4 bytes (Base+0x001C-0x0019) */\r
+ \r
+ union { /* INTC Software Set/Clear Interrupt0-7 (+0x0020-0x0027) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t SET:1;\r
+ vuint8_t CLR:1;\r
+ } B;\r
+ } SSCIR[8];\r
+\r
+ vuint8_t INTC_reserved4[24]; /* Reserved 24 bytes (Base+0x0028-0x003F) */\r
+\r
+ union { /* INTC Priority Select (Base+0x0040-0x0128) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t PRI:4;\r
+ } B;\r
+ } PSR[234]; \r
+\r
+}; /* end of INTC_tag */\r
+/****************************************************************************/\r
+/* MODULE : DSPI */\r
+/* Base Addresses: */\r
+/* DSPI_0 - 0xFFF9_0000 */\r
+/* DSPI_1 - 0xFFF9_4000 */\r
+/* DSPI_2 - 0xFFF9_8000 */\r
+/* DSPI_3 - 0xFFF9_C000 */\r
+/* DSPI_4 - 0xFFFA_0000 */\r
+/* DSPI_5 - 0xFFFA_4000 */\r
+/****************************************************************************/\r
+struct DSPI_tag{\r
+\r
+ union { /* DSPI Module Configuraiton (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MSTR:1;\r
+ vuint32_t CONT_SCKE:1;\r
+ vuint32_t DCONF:2;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t MTFE:1;\r
+ vuint32_t PCSSE:1;\r
+ vuint32_t ROOE:1;\r
+ vuint32_t :2; \r
+ vuint32_t PCSIS5:1;\r
+ vuint32_t PCSIS4:1;\r
+ vuint32_t PCSIS3:1;\r
+ vuint32_t PCSIS2:1;\r
+ vuint32_t PCSIS1:1;\r
+ vuint32_t PCSIS0:1;\r
+ vuint32_t DOZE:1; \r
+ vuint32_t MDIS:1;\r
+ vuint32_t DIS_TXF:1;\r
+ vuint32_t DIS_RXF:1;\r
+ vuint32_t CLR_TXF:1;\r
+ vuint32_t CLR_RXF:1;\r
+ vuint32_t SMPL_PT:2;\r
+ vuint32_t :7;\r
+ vuint32_t HALT:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ vuint8_t DSPI_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* DSPI Transfer Count (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCNT:16;\r
+ vuint32_t :16;\r
+ } B;\r
+ } TCR;\r
+\r
+ union { /* DSPI Clock & Tranfer Attrib 0-5 (+0x000C-0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DBR:1;\r
+ vuint32_t FMSZ:4;\r
+ vuint32_t CPOL:1;\r
+ vuint32_t CPHA:1;\r
+ vuint32_t LSBFE:1;\r
+ vuint32_t PCSSCK:2;\r
+ vuint32_t PASC:2;\r
+ vuint32_t PDT:2;\r
+ vuint32_t PBR:2;\r
+ vuint32_t CSSCK:4;\r
+ vuint32_t ASC:4;\r
+ vuint32_t DT:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } CTAR[6];\r
+\r
+ vuint8_t DSPI_reserved1[8]; /* Reserved 4 bytes (Base+0x0024-0x002B) */\r
+\r
+ union { /* DSPI Status (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCF:1;\r
+ vuint32_t TXRXS:1;\r
+ vuint32_t :1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t TFUF:1;\r
+ vuint32_t :1;\r
+ vuint32_t TFFF:1;\r
+ vuint32_t :5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t :1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t :1;\r
+ vuint32_t TXCTR:4;\r
+ vuint32_t TXNXTPTR:4;\r
+ vuint32_t RXCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } SR;\r
+\r
+ union { /* DSPI DMA/Int Request Select & Enable (+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCFRE:1;\r
+ vuint32_t :2;\r
+ vuint32_t EOQFRE:1;\r
+ vuint32_t TFUFRE:1;\r
+ vuint32_t :1;\r
+ vuint32_t TFFFRE:1;\r
+ vuint32_t TFFFDIRS:1;\r
+ vuint32_t :4;\r
+ vuint32_t RFOFRE:1;\r
+ vuint32_t :1;\r
+ vuint32_t RFDFRE:1;\r
+ vuint32_t RFDFDIRS:1;\r
+ vuint32_t :16;\r
+ } B;\r
+ } RSER;\r
+\r
+ union { /* DSPI Push TX FIFO (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CONT:1;\r
+ vuint32_t CTAS:3;\r
+ vuint32_t EOQ:1;\r
+ vuint32_t CTCNT:1;\r
+ vuint32_t :4; \r
+ vuint32_t PCS5:1;\r
+ vuint32_t PCS4:1;\r
+ vuint32_t PCS3:1;\r
+ vuint32_t PCS2:1;\r
+ vuint32_t PCS1:1;\r
+ vuint32_t PCS0:1;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } PUSHR;\r
+\r
+ union { /* DSPI Pop RX FIFO (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16; \r
+ vuint32_t RXDATA:16; \r
+ } B;\r
+ } POPR;\r
+\r
+ union { /* DSPI Transmit FIFO 0-3 (Base+0x003C-0x0048)*/\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t TXCMD:16; \r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } TXFR[4];\r
+\r
+ vuint8_t DSPI_reserved2[48]; /* Reserved 48 bytes (Base+0x004C-0x007B) */\r
+\r
+ union { /* DSPI Receive FIFO 0-3 (Base+0x007C-0x0088) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16; \r
+ vuint32_t RXDATA:16; \r
+ } B;\r
+ } RXFR[4];\r
+ }; /* end of DSPI_tag */\r
+ /****************************************************************************/\r
+/* MODULE : FlexCAN */\r
+/* Base Addresses: */\r
+/* FlexCAN_0 - 0xFFFC_0000 */\r
+/* FlexCAN_1 - 0xFFFC_4000 */\r
+/* FlexCAN_2 - 0xFFFC_8000 */\r
+/* FlexCAN_3 - 0xFFFC_C000 */\r
+/* FlexCAN_4 - 0xFFFD_0000 */\r
+/* FlexCAN_5 - 0xFFFD_4000 */\r
+/****************************************************************************/\r
+struct FLEXCAN_BUF_t{\r
+\r
+ union { /* FLEXCAN MBx Control & Status (Offset+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CODE:4;\r
+ vuint32_t :1;\r
+ vuint32_t SRR:1;\r
+ vuint32_t IDE:1;\r
+ vuint32_t RTR:1;\r
+ vuint32_t LENGTH:4;\r
+ vuint32_t TIMESTAMP:16;\r
+ } B;\r
+ } CS;\r
+\r
+ union { /* FLEXCAN MBx Identifier (Offset+0x0084) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRIO:3;\r
+ vuint32_t STD_ID:11;\r
+ vuint32_t EXT_ID:18;\r
+ } B;\r
+ } ID;\r
+\r
+ union { /* FLEXCAN MBx Data 0..7 (Offset+0x0088) */\r
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
+ } DATA;\r
+\r
+}; /* end of FLEXCAN_BUF_t */\r
+\r
+\r
+struct FLEXCAN_RXFIFO_t{ /* RxFIFO Configuration */\r
+\r
+ union { /* RxFIFO Control & Status (Offset+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :9;\r
+ vuint32_t SRR:1;\r
+ vuint32_t IDE:1;\r
+ vuint32_t RTR:1;\r
+ vuint32_t LENGTH:4;\r
+ vuint32_t TIMESTAMP:16;\r
+ } B;\r
+ } CS;\r
+\r
+ union { /* RxFIFO Identifier (Offset+0x0084) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t STD_ID:11;\r
+ vuint32_t EXT_ID:18;\r
+ } B;\r
+ } ID;\r
+\r
+ union { /* RxFIFO Data 0..7 (Offset+0x0088) */\r
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
+ } DATA;\r
+\r
+ vuint8_t FLEXCAN_RX_reserved0[80]; /* Reserved 80 bytes (+0x0090-0x00DF)*/\r
+\r
+ union { /* RxFIFO ID Table 0..7 (+0x00E0-0x00FC) */\r
+ vuint32_t R;\r
+ } IDTABLE[8];\r
+\r
+}; /* end of FLEXCAN_RXFIFO_t */\r
+\r
+\r
+struct FLEXCAN_tag{\r
+\r
+ union { /* FLEXCAN Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t HALT:1;\r
+ vuint32_t NOTRDY:1;\r
+ vuint32_t WAKMSK:1;\r
+ vuint32_t SOFTRST:1;\r
+ vuint32_t FRZACK:1;\r
+ vuint32_t SUPV:1;\r
+ vuint32_t SLFWAK:1; /*not present in RM*/\r
+ vuint32_t WRNEN:1;\r
+ vuint32_t LPMACK:1;\r
+ vuint32_t WAKSRC:1;\r
+ vuint32_t DOZE:1; /*not present in RM*/\r
+ vuint32_t SRXDIS:1;\r
+ vuint32_t BCC:1;\r
+ vuint32_t:2;\r
+ vuint32_t LPRIO_EN:1;\r
+ vuint32_t AEN:1;\r
+ vuint32_t:2;\r
+ vuint32_t IDAM:2;\r
+ vuint32_t:2;\r
+ vuint32_t MAXMB:6;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* FLEXCAN Control (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRESDIV:8;\r
+ vuint32_t RJW:2;\r
+ vuint32_t PSEG1:3;\r
+ vuint32_t PSEG2:3;\r
+ vuint32_t BOFFMSK:1;\r
+ vuint32_t ERRMSK:1;\r
+ vuint32_t CLKSRC:1;\r
+ vuint32_t LPB:1;\r
+ vuint32_t TWRNMSK:1;\r
+ vuint32_t RWRNMSK:1;\r
+ vuint32_t :2;\r
+ vuint32_t SMP:1;\r
+ vuint32_t BOFFREC:1;\r
+ vuint32_t TSYN:1;\r
+ vuint32_t LBUF:1;\r
+ vuint32_t LOM:1;\r
+ vuint32_t PROPSEG:3;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* FLEXCAN Free Running Timer (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t TIMER:16;\r
+ } B;\r
+ } TIMER;\r
+\r
+ vuint8_t FLEXCAN_reserved0[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */\r
+\r
+ union { /* FLEXCAN RX Global Mask (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RXGMASK;\r
+\r
+ /* --- Following 2 registers are included for legacy purposes only --- */\r
+\r
+ union { /* FLEXCAN RX 14 Mask (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RX14MASK;\r
+\r
+ union { /* FLEXCAN RX 15 Mask (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RX15MASK;\r
+\r
+ /* --- */\r
+\r
+ union { /* FLEXCAN Error Counter (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t RXECNT:8;\r
+ vuint32_t TXECNT:8;\r
+ } B;\r
+ } ECR;\r
+\r
+ union { /* FLEXCAN Error & Status (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :14;\r
+ vuint32_t TWRNINT:1;\r
+ vuint32_t RWRNINT:1;\r
+ vuint32_t BIT1ERR:1;\r
+ vuint32_t BIT0ERR:1;\r
+ vuint32_t ACKERR:1;\r
+ vuint32_t CRCERR:1;\r
+ vuint32_t FRMERR:1;\r
+ vuint32_t STFERR:1;\r
+ vuint32_t TXWRN:1;\r
+ vuint32_t RXWRN:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t TXRX:1;\r
+ vuint32_t FLTCONF:2;\r
+ vuint32_t :1;\r
+ vuint32_t BOFFINT:1;\r
+ vuint32_t ERRINT:1;\r
+ vuint32_t :1;\r
+ } B;\r
+ } ESR;\r
+\r
+ union { /* FLEXCAN Interruput Masks H (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63M:1;\r
+ vuint32_t BUF62M:1;\r
+ vuint32_t BUF61M:1;\r
+ vuint32_t BUF60M:1;\r
+ vuint32_t BUF59M:1;\r
+ vuint32_t BUF58M:1;\r
+ vuint32_t BUF57M:1;\r
+ vuint32_t BUF56M:1;\r
+ vuint32_t BUF55M:1;\r
+ vuint32_t BUF54M:1;\r
+ vuint32_t BUF53M:1;\r
+ vuint32_t BUF52M:1;\r
+ vuint32_t BUF51M:1;\r
+ vuint32_t BUF50M:1;\r
+ vuint32_t BUF49M:1;\r
+ vuint32_t BUF48M:1;\r
+ vuint32_t BUF47M:1;\r
+ vuint32_t BUF46M:1;\r
+ vuint32_t BUF45M:1;\r
+ vuint32_t BUF44M:1;\r
+ vuint32_t BUF43M:1;\r
+ vuint32_t BUF42M:1;\r
+ vuint32_t BUF41M:1;\r
+ vuint32_t BUF40M:1;\r
+ vuint32_t BUF39M:1;\r
+ vuint32_t BUF38M:1;\r
+ vuint32_t BUF37M:1;\r
+ vuint32_t BUF36M:1;\r
+ vuint32_t BUF35M:1;\r
+ vuint32_t BUF34M:1;\r
+ vuint32_t BUF33M:1;\r
+ vuint32_t BUF32M:1;\r
+ } B;\r
+ } IMRH;\r
+\r
+ union { /* FLEXCAN Interruput Masks L (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31M:1;\r
+ vuint32_t BUF30M:1;\r
+ vuint32_t BUF29M:1;\r
+ vuint32_t BUF28M:1;\r
+ vuint32_t BUF27M:1;\r
+ vuint32_t BUF26M:1;\r
+ vuint32_t BUF25M:1;\r
+ vuint32_t BUF24M:1;\r
+ vuint32_t BUF23M:1;\r
+ vuint32_t BUF22M:1;\r
+ vuint32_t BUF21M:1;\r
+ vuint32_t BUF20M:1;\r
+ vuint32_t BUF19M:1;\r
+ vuint32_t BUF18M:1;\r
+ vuint32_t BUF17M:1;\r
+ vuint32_t BUF16M:1;\r
+ vuint32_t BUF15M:1;\r
+ vuint32_t BUF14M:1;\r
+ vuint32_t BUF13M:1;\r
+ vuint32_t BUF12M:1;\r
+ vuint32_t BUF11M:1;\r
+ vuint32_t BUF10M:1;\r
+ vuint32_t BUF09M:1;\r
+ vuint32_t BUF08M:1;\r
+ vuint32_t BUF07M:1;\r
+ vuint32_t BUF06M:1;\r
+ vuint32_t BUF05M:1;\r
+ vuint32_t BUF04M:1;\r
+ vuint32_t BUF03M:1;\r
+ vuint32_t BUF02M:1;\r
+ vuint32_t BUF01M:1;\r
+ vuint32_t BUF00M:1;\r
+ } B;\r
+ } IMRL;\r
+\r
+ union { /* FLEXCAN Interruput Flag H (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63I:1;\r
+ vuint32_t BUF62I:1;\r
+ vuint32_t BUF61I:1;\r
+ vuint32_t BUF60I:1;\r
+ vuint32_t BUF59I:1;\r
+ vuint32_t BUF58I:1;\r
+ vuint32_t BUF57I:1;\r
+ vuint32_t BUF56I:1;\r
+ vuint32_t BUF55I:1;\r
+ vuint32_t BUF54I:1;\r
+ vuint32_t BUF53I:1;\r
+ vuint32_t BUF52I:1;\r
+ vuint32_t BUF51I:1;\r
+ vuint32_t BUF50I:1;\r
+ vuint32_t BUF49I:1;\r
+ vuint32_t BUF48I:1;\r
+ vuint32_t BUF47I:1;\r
+ vuint32_t BUF46I:1;\r
+ vuint32_t BUF45I:1;\r
+ vuint32_t BUF44I:1;\r
+ vuint32_t BUF43I:1;\r
+ vuint32_t BUF42I:1;\r
+ vuint32_t BUF41I:1;\r
+ vuint32_t BUF40I:1;\r
+ vuint32_t BUF39I:1;\r
+ vuint32_t BUF38I:1;\r
+ vuint32_t BUF37I:1;\r
+ vuint32_t BUF36I:1;\r
+ vuint32_t BUF35I:1;\r
+ vuint32_t BUF34I:1;\r
+ vuint32_t BUF33I:1;\r
+ vuint32_t BUF32I:1;\r
+ } B;\r
+ } IFRH;\r
+\r
+ union { /* FLEXCAN Interruput Flag l (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31I:1;\r
+ vuint32_t BUF30I:1;\r
+ vuint32_t BUF29I:1;\r
+ vuint32_t BUF28I:1;\r
+ vuint32_t BUF27I:1;\r
+ vuint32_t BUF26I:1;\r
+ vuint32_t BUF25I:1;\r
+ vuint32_t BUF24I:1;\r
+ vuint32_t BUF23I:1;\r
+ vuint32_t BUF22I:1;\r
+ vuint32_t BUF21I:1;\r
+ vuint32_t BUF20I:1;\r
+ vuint32_t BUF19I:1;\r
+ vuint32_t BUF18I:1;\r
+ vuint32_t BUF17I:1;\r
+ vuint32_t BUF16I:1;\r
+ vuint32_t BUF15I:1;\r
+ vuint32_t BUF14I:1;\r
+ vuint32_t BUF13I:1;\r
+ vuint32_t BUF12I:1;\r
+ vuint32_t BUF11I:1;\r
+ vuint32_t BUF10I:1;\r
+ vuint32_t BUF09I:1;\r
+ vuint32_t BUF08I:1;\r
+ vuint32_t BUF07I:1;\r
+ vuint32_t BUF06I:1;\r
+ vuint32_t BUF05I:1;\r
+ vuint32_t BUF04I:1;\r
+ vuint32_t BUF03I:1;\r
+ vuint32_t BUF02I:1;\r
+ vuint32_t BUF01I:1;\r
+ vuint32_t BUF00I:1;\r
+ } B;\r
+ } IFRL; /* Interruput Flag Register */\r
+\r
+ vuint8_t FLEXCAN_reserved1[76]; /*Reserved 76 bytes (Base+0x0034-0x007F)*/\r
+\r
+/****************************************************************************/\r
+/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */\r
+/****************************************************************************/\r
+ /* Standard Buffer Structure */\r
+ struct FLEXCAN_BUF_t BUF[64];\r
+\r
+ /* RX FIFO and Buffer Structure */\r
+ /*struct FLEXCAN_RXFIFO_t RXFIFO; */\r
+ /*struct FLEXCAN_BUF_t BUF[56]; */\r
+/****************************************************************************/\r
+\r
+ vuint8_t FLEXCAN_reserved2[1024]; /*Reserved 1024 (Base+0x0480-0x087F)*/\r
+\r
+ union { /* FLEXCAN RX Individual Mask (Base+0x0880-0x097F) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RXIMR[64];\r
+\r
+}; /* end of FLEXCAN_tag */\r
+/****************************************************************************/\r
+/* MODULE : DMAMUX (base address - 0xFFFD_C000) */\r
+/****************************************************************************/\r
+ struct DMAMUX_tag {\r
+ union { /* DMAMUX Channel Configuration (Base+0x0000-0x000F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ENBL:1;\r
+ vuint8_t TRIG:1;\r
+ vuint8_t SOURCE:6;\r
+ } B;\r
+ } CHCONFIG[16]; \r
+\r
+ }; /* end of DMAMUX_tag */\r
+/****************************************************************************/\r
+/* MODULE : DFLASH (base address - 0x0080_0000) */\r
+/****************************************************************************/\r
+ struct DFLASH_tag {\r
+ union { /* Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EDC:1;\r
+ vuint32_t:4;\r
+ vuint32_t SIZE:3;\r
+ vuint32_t:1;\r
+ vuint32_t LAS:3;\r
+ vuint32_t:3;\r
+ vuint32_t MAS:1;\r
+ vuint32_t EER:1;\r
+ vuint32_t RWE:1;\r
+ vuint32_t:2;\r
+ vuint32_t PEAS:1;\r
+ vuint32_t DONE:1;\r
+ vuint32_t PEG:1;\r
+ vuint32_t:4;\r
+ vuint32_t PGM:1;\r
+ vuint32_t PSUS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t ESUS:1;\r
+ vuint32_t EHV:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* Low/Mid address block locking (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LME:1;\r
+ vuint32_t:10;\r
+ vuint32_t TSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t MLK:2;\r
+ vuint32_t LLK:16;\r
+ } B;\r
+ } LML;\r
+\r
+ union { /* High address block locking (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBE:1;\r
+ vuint32_t :25;\r
+ vuint32_t HBLOCK:6;\r
+ } B;\r
+ } HBL;\r
+\r
+ union { /* Secondary Low/mid block locking (Base+0x000C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLE:1;\r
+ vuint32_t:10;\r
+ vuint32_t STSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t SMK:2;\r
+ vuint32_t SLK:16;\r
+ } B;\r
+ } SLL;\r
+\r
+ union { /* Low/Mid address space block sel (Base+0x0010)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MSL:2;\r
+ vuint32_t LSL:16;\r
+ } B;\r
+ } LMS;\r
+\r
+ union { /* High address space block sel (Base+0x0014)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t HSL:6;\r
+ } B;\r
+ } HBS;\r
+\r
+ union { /* Address Register (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:9;\r
+ vuint32_t ADD:20;\r
+ vuint32_t:3;\r
+ } B;\r
+ } ADR;\r
+\r
+ vuint8_t DFLASH_reserved0[32]; /* Reserved 32 Bytes (+0x001C-0x003B) */\r
+\r
+ union { /* User Test 0 (Base+0x003C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t UTE:1;\r
+ vuint32_t:7;\r
+ vuint32_t DSI:8;\r
+ vuint32_t:10;\r
+ vuint32_t MRE:1;\r
+ vuint32_t MRV:1;\r
+ vuint32_t EIE:1;\r
+ vuint32_t AIS:1;\r
+ vuint32_t AIE:1;\r
+ vuint32_t AID:1;\r
+ } B;\r
+ } UT0;\r
+\r
+ union { /* User Test 1 (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT1;\r
+\r
+ union { /* User Test 2 (Base+0x0044) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT2;\r
+\r
+ union { /* User Multiple Input sig 0..1 (+0x0048-0x004F)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MS:32;\r
+ } B;\r
+ } UMISR[5];\r
+\r
+ }; /* end of Dflash_tag */\r
+/****************************************************************************/\r
+/* MODULE : CFLASH (base address - 0xC3F8_8000) */\r
+/****************************************************************************/\r
+ struct CFLASH_tag {\r
+ union { /* Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EDC:1;\r
+ vuint32_t:4;\r
+ vuint32_t SIZE:3;\r
+ vuint32_t:1;\r
+ vuint32_t LAS:3;\r
+ vuint32_t:3;\r
+ vuint32_t MAS:1;\r
+ vuint32_t EER:1;\r
+ vuint32_t RWE:1;\r
+ vuint32_t:1;\r
+ vuint32_t:1;\r
+ vuint32_t PEAS:1;\r
+ vuint32_t DONE:1;\r
+ vuint32_t PEG:1;\r
+ vuint32_t:4;\r
+ vuint32_t PGM:1;\r
+ vuint32_t PSUS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t ESUS:1;\r
+ vuint32_t EHV:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* Low/Mid address block locking (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LME:1;\r
+ vuint32_t:10;\r
+ vuint32_t TSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t MLK:2;\r
+ vuint32_t LLK:16;\r
+ } B;\r
+ } LML;\r
+\r
+ union { /* High address space block locking (Base+0x0008)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBE:1;\r
+ vuint32_t :19;\r
+ vuint32_t HBLOCK:12;\r
+ } B;\r
+ } HBL;\r
+\r
+ union { /* Secondary Low/Mid block lock (Base+0x000C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLE:1;\r
+ vuint32_t:10;\r
+ vuint32_t STSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t SMK:2;\r
+ vuint32_t SLK:16;\r
+ } B;\r
+ } SLL;\r
+\r
+ union { /* Low/Mid address space block sel (Base+0x0010)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MSL:2;\r
+ vuint32_t LSL:16;\r
+ } B;\r
+ } LMS;\r
+\r
+ union { /* High address Space block select (Base+0x0014)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t HSL:12;\r
+ } B;\r
+ } HBS;\r
+\r
+ union { /* Address Register (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:9;\r
+ vuint32_t ADD:20;\r
+ vuint32_t:3;\r
+ } B;\r
+ } ADR;\r
+\r
+ /* Note the following 3 registers, BIU[0..2] are mirrored to */\r
+ /* the code flash configuraiton PFCR[0..2] registers */\r
+ /* To make it easier to code, the BIU registers have been */\r
+ /* replaced with the PFCR registers in this header file! */\r
+ /* A commented out BIU register is shown for reference! */\r
+\r
+\r
+ union { /* CFLASH Configuration 0 (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BK0_APC:5;\r
+ vuint32_t BK0_WWSC:5;\r
+ vuint32_t BK0_RWSC:5;\r
+ vuint32_t BK0_RWWC2:1;\r
+ vuint32_t BK0_RWWC1:1;\r
+ /* vuint32_t B0_P1_BCFG:2; // only has one port to the cross bar i.e. port 0 \r
+ vuint32_t B0_P1_DPFE:1;\r
+ vuint32_t B0_P1_IPFE:1;\r
+ vuint32_t B0_P1_PFLM:2;\r
+ vuint32_t B0_P1_BFE:1; */\r
+ vuint32_t :7;\r
+ vuint32_t BK0_RWWC0:1;\r
+ vuint32_t B0_P0_BCFG:2;\r
+ vuint32_t B0_P0_DPFE:1;\r
+ vuint32_t B0_P0_IPFE:1;\r
+ vuint32_t B0_P0_PFLM:2;\r
+ vuint32_t B0_P0_BFE:1;\r
+ } B;\r
+ } PFCR0;\r
+ \r
+/* Commented out Bus Interface Unit 0 (Base+0x001C) */\r
+ /*union { \r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BI0:32;\r
+ } B;\r
+ } BIU0; */\r
+\r
+ union { /* CFLASH Configuration Register 1 (Base+0x0020)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BK1_APC:5;\r
+ vuint32_t BK1_WWSC:5;\r
+ vuint32_t BK1_RWSC:5;\r
+ vuint32_t BK1_RWWC2:1;\r
+ vuint32_t BK1_RWWC1:1;\r
+ vuint32_t:7; /* changed to 7 to suit comment below */\r
+ //vuint32_t B1_P1_BFE:1; /* should have no effect, there is only one XBAR port (no P1) to P-flash controller */ \r
+ vuint32_t BK1_RWWC0:1;\r
+ vuint32_t:6;\r
+ vuint32_t B1_P0_BFE:1;\r
+ } B;\r
+ } PFCR1;\r
+ \r
+/* Commented out Bus Interface Unit 1 (Base+0x0020) */\r
+ /*union { \r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BI1:32;\r
+ } B;\r
+ } BIU1; */\r
+\r
+ union { /* CFLASH Access Protection (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6; /*incorrect - B1M/B1.5M does not have this many masters TBD*/ \r
+ vuint32_t ARBM:2;\r
+ vuint32_t M7PFD:1;\r
+ vuint32_t M6PFD:1;\r
+ vuint32_t M5PFD:1;\r
+ vuint32_t M4PFD:1;\r
+ vuint32_t M3PFD:1;\r
+ vuint32_t M2PFD:1;\r
+ vuint32_t M1PFD:1;\r
+ vuint32_t M0PFD:1;\r
+ vuint32_t M7AP:2;\r
+ vuint32_t M6AP:2;\r
+ vuint32_t M5AP:2;\r
+ vuint32_t M4AP:2;\r
+ vuint32_t M3AP:2;\r
+ vuint32_t M2AP:2;\r
+ vuint32_t M1AP:2;\r
+ vuint32_t M0AP:2;\r
+ } B;\r
+ } PFAPR;\r
+ \r
+/* Commented out Bus Interface Unit 2 (Base+0x0024) */\r
+ /*union { \r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BI2:32;\r
+ } B;\r
+ } BIU2; */\r
+\r
+ vuint8_t CFLASH_reserved0[20]; /* Reserved 20 Bytes (Base+0x0028-0x003B) */\r
+\r
+ union { /* User Test 0 (Base+0x003C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t UTE:1;\r
+ vuint32_t:7;\r
+ vuint32_t DSI:8;\r
+ vuint32_t:10;\r
+ vuint32_t MRE:1;\r
+ vuint32_t MRV:1;\r
+ vuint32_t EIE:1;\r
+ vuint32_t AIS:1;\r
+ vuint32_t AIE:1;\r
+ vuint32_t AID:1;\r
+ } B;\r
+ } UT0;\r
+\r
+ union { /* User Test 1 (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT1;\r
+\r
+ union { /* User Test 2 (Base+0x0044) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT2;\r
+\r
+ union { /* User Multiple Input Sig 0..4 (Base+0x0048-0x005B) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MS:32;\r
+ } B;\r
+ } UMISR[5];\r
+ \r
+ vuint8_t CFLASH_reserved1[16292]; /* Reserved 16292 (Base+0x005C-0x3FFF)*/\r
+\r
+ }; /* end of CFLASH_tag */\r
+/****************************************************************** \r
+| defines and macros (scope: module-local) \r
+|-----------------------------------------------------------------*/\r
+/* Define instances of modules */\r
+\r
+#define ADC_0 (*(volatile struct ADC_tag *) 0xFFE00000UL)\r
+#define ADC_1 (*(volatile struct ADC_tag *) 0xFFE04000UL)\r
+#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)\r
+#define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)\r
+#define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)\r
+#define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)\r
+#define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)\r
+#define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)\r
+#define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL)\r
+#define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL)\r
+#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)\r
+#define CTUL (*(volatile struct CTUL_tag *) 0xFFE64000UL)\r
+#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)\r
+#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)\r
+#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)\r
+#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)\r
+#define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL)\r
+#define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL)\r
+#define DSPI_4 (*(volatile struct DSPI_tag *) 0xFFFA0000UL)\r
+#define DSPI_5 (*(volatile struct DSPI_tag *) 0xFFFA4000UL)\r
+#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) \r
+#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)\r
+#define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL)\r
+#define I2C_0 (*(volatile struct I2C_tag *) 0xFFE30000UL)\r
+#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)\r
+#define LINFLEX_0 (*(volatile struct LINFLEXD0_tag *) 0xFFE40000UL)\r
+#define LINFLEX_1 (*(volatile struct LINFLEXD1_tag *) 0xFFE44000UL)\r
+#define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL)\r
+#define LINFLEX_3 (*(volatile struct LINFLEX_tag *) 0xFFE4C000UL)\r
+#define LINFLEX_4 (*(volatile struct LINFLEX_tag *) 0xFFE50000UL)\r
+#define LINFLEX_5 (*(volatile struct LINFLEX_tag *) 0xFFE54000UL)\r
+#define LINFLEX_6 (*(volatile struct LINFLEX_tag *) 0xFFE58000UL)\r
+#define LINFLEX_7 (*(volatile struct LINFLEX_tag *) 0xFFE5C000UL)\r
+//#define LINFLEX_8 (*(volatile struct LINFLEX_tag *) 0xFFFB0000UL)\r
+//#define LINFLEX_9 (*(volatile struct LINFLEX_tag *) 0xFFFB4000UL)\r
+#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)\r
+#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)\r
+#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)\r
+#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)\r
+#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)\r
+#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)\r
+#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)\r
+#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)\r
+#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)\r
+#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)\r
+#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)\r
+#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)\r
+\r
+#ifdef __MWERKS__\r
+#pragma pop\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif \r
+/* End of file */\r
--- /dev/null
+/**************************************************************************** \r
+ * PROJECT : MPC5607B\r
+ * \r
+ * FILE : MPC5607B_2.01.h\r
+ * \r
+ * DESCRIPTION : This is the header file describing the register\r
+ * set for MPC5607B\r
+ * \r
+ * COPYRIGHT :(c) 2011, Freescale \r
+ * \r
+ * VERSION : 2.01 \r
+ * DATE : 3.30.2011 \r
+ * AUTHOR : r23668\r
+ * HISTORY : Based Upon Bolero 1M; Version 0.03 header file\r
+ * Updated and corrected errors present on B1.5M 01.04.1 \r
+ * and have brought up to date and format with B3M. Corrected\r
+ * LinFlex error.\r
+ * \r
+*\r
+* Example instantiation and use: \r
+* \r
+* <MODULE>.<REGISTER>.B.<BIT> = 1; \r
+* <MODULE>.<REGISTER>.R = 0x10000000;\r
+\r
+*****************************************************************************/\r
+\r
+#ifndef _JDP_H_\r
+#define _JDP_H_\r
+\r
+#include "typedefs.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#ifdef __MWERKS__\r
+#pragma push\r
+#pragma ANSI_strict off\r
+#endif\r
+\r
+//#define CUT2\r
+/****************************************************************************/\r
+/* MODULE : ADC0 */\r
+/****************************************************************************/\r
+ struct ADC0_tag {\r
+\r
+ union { /* ADC0 Main Configuration Register (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t OWREN:1;\r
+ vuint32_t WLSIDE:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t:4;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t:1;\r
+ vuint32_t JTRGEN:1;\r
+ vuint32_t JEDGE:1;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:2;\r
+ vuint32_t CTUEN:1;\r
+ vuint32_t:8;\r
+ vuint32_t ADCLKSEL:1;\r
+ vuint32_t ABORTCHAIN:1;\r
+ vuint32_t ABORT:1;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:4; \r
+ vuint32_t PWDN:1; \r
+ } B;\r
+ } MCR; \r
+ \r
+ union { /* ADC0 Main Status Register (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:7;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t JABORT:1;\r
+ vuint32_t:2;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:3;\r
+ vuint32_t CTUSTART:1;\r
+ vuint32_t CHADDR:7;\r
+ vuint32_t:3;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:2; \r
+ vuint32_t ADCSTATUS:3;\r
+ } B;\r
+ } MSR; \r
+ \r
+ vuint8_t ADC0_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */\r
+ \r
+ union { /* ADC0 Interrupt Status (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t EOCTU:1;\r
+ vuint32_t JEOC:1;\r
+ vuint32_t JECH:1;\r
+ vuint32_t EOC:1;\r
+ vuint32_t ECH:1;\r
+ } B;\r
+ } ISR; \r
+ \r
+ \r
+ union { /* ADC0 Channel Pending 0 (Base+0x0014) */\r
+ vuint32_t R; /* (For precision channels) */\r
+ struct {\r
+ vuint32_t EOC_CH31:1;\r
+ vuint32_t EOC_CH30:1;\r
+ vuint32_t EOC_CH29:1;\r
+ vuint32_t EOC_CH28:1;\r
+ vuint32_t EOC_CH27:1;\r
+ vuint32_t EOC_CH26:1;\r
+ vuint32_t EOC_CH25:1;\r
+ vuint32_t EOC_CH24:1;\r
+ vuint32_t EOC_CH23:1;\r
+ vuint32_t EOC_CH22:1;\r
+ vuint32_t EOC_CH21:1;\r
+ vuint32_t EOC_CH20:1;\r
+ vuint32_t EOC_CH19:1;\r
+ vuint32_t EOC_CH18:1;\r
+ vuint32_t EOC_CH17:1;\r
+ vuint32_t EOC_CH16:1;\r
+ vuint32_t EOC_CH15:1;\r
+ vuint32_t EOC_CH14:1;\r
+ vuint32_t EOC_CH13:1;\r
+ vuint32_t EOC_CH12:1;\r
+ vuint32_t EOC_CH11:1;\r
+ vuint32_t EOC_CH10:1;\r
+ vuint32_t EOC_CH9:1;\r
+ vuint32_t EOC_CH8:1;\r
+ vuint32_t EOC_CH7:1;\r
+ vuint32_t EOC_CH6:1;\r
+ vuint32_t EOC_CH5:1;\r
+ vuint32_t EOC_CH4:1;\r
+ vuint32_t EOC_CH3:1;\r
+ vuint32_t EOC_CH2:1;\r
+ vuint32_t EOC_CH1:1;\r
+ vuint32_t EOC_CH0:1;\r
+ } B;\r
+ } CEOCFR0; \r
+ \r
+ \r
+ union { /* ADC0 Channel Pending Register 1 (Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EOC_CH63:1;\r
+ vuint32_t EOC_CH62:1;\r
+ vuint32_t EOC_CH61:1;\r
+ vuint32_t EOC_CH60:1;\r
+ vuint32_t EOC_CH59:1;\r
+ vuint32_t EOC_CH58:1;\r
+ vuint32_t EOC_CH57:1;\r
+ vuint32_t EOC_CH56:1;\r
+ vuint32_t EOC_CH55:1;\r
+ vuint32_t EOC_CH54:1;\r
+ vuint32_t EOC_CH53:1;\r
+ vuint32_t EOC_CH52:1;\r
+ vuint32_t EOC_CH51:1;\r
+ vuint32_t EOC_CH50:1;\r
+ vuint32_t EOC_CH49:1;\r
+ vuint32_t EOC_CH48:1;\r
+ vuint32_t EOC_CH47:1;\r
+ vuint32_t EOC_CH46:1;\r
+ vuint32_t EOC_CH45:1;\r
+ vuint32_t EOC_CH44:1;\r
+ vuint32_t EOC_CH43:1;\r
+ vuint32_t EOC_CH42:1;\r
+ vuint32_t EOC_CH41:1;\r
+ vuint32_t EOC_CH40:1;\r
+ vuint32_t EOC_CH39:1;\r
+ vuint32_t EOC_CH38:1;\r
+ vuint32_t EOC_CH37:1;\r
+ vuint32_t EOC_CH36:1;\r
+ vuint32_t EOC_CH35:1;\r
+ vuint32_t EOC_CH34:1;\r
+ vuint32_t EOC_CH33:1;\r
+ vuint32_t EOC_CH32:1;\r
+ } B;\r
+ } CEOCFR1; \r
+ \r
+ union { /* ADC0 Channel Pending 2 (Base+0x001C) */\r
+ vuint32_t R; /* (For external mux'd Channels) */\r
+ struct {\r
+ vuint32_t EOC_CH95:1;\r
+ vuint32_t EOC_CH94:1;\r
+ vuint32_t EOC_CH93:1;\r
+ vuint32_t EOC_CH92:1;\r
+ vuint32_t EOC_CH91:1;\r
+ vuint32_t EOC_CH90:1;\r
+ vuint32_t EOC_CH89:1;\r
+ vuint32_t EOC_CH88:1;\r
+ vuint32_t EOC_CH87:1;\r
+ vuint32_t EOC_CH86:1;\r
+ vuint32_t EOC_CH85:1;\r
+ vuint32_t EOC_CH84:1;\r
+ vuint32_t EOC_CH83:1;\r
+ vuint32_t EOC_CH82:1;\r
+ vuint32_t EOC_CH81:1;\r
+ vuint32_t EOC_CH80:1;\r
+ vuint32_t EOC_CH79:1;\r
+ vuint32_t EOC_CH78:1;\r
+ vuint32_t EOC_CH77:1;\r
+ vuint32_t EOC_CH76:1;\r
+ vuint32_t EOC_CH75:1;\r
+ vuint32_t EOC_CH74:1;\r
+ vuint32_t EOC_CH73:1;\r
+ vuint32_t EOC_CH72:1;\r
+ vuint32_t EOC_CH71:1;\r
+ vuint32_t EOC_CH70:1;\r
+ vuint32_t EOC_CH69:1;\r
+ vuint32_t EOC_CH68:1;\r
+ vuint32_t EOC_CH67:1;\r
+ vuint32_t EOC_CH66:1;\r
+ vuint32_t EOC_CH65:1;\r
+ vuint32_t EOC_CH64:1;\r
+ } B;\r
+ } CE0CFR2; \r
+ \r
+\r
+ union { /* ADC0 Interrupt Mask (Base+0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t MSKEOCTU:1;\r
+ vuint32_t MSKJEOC:1;\r
+ vuint32_t MSKJECH:1;\r
+ vuint32_t MSKEOC:1;\r
+ vuint32_t MSKECH:1; \r
+ } B;\r
+ } IMR; \r
+ \r
+\r
+\r
+ union { /* ADC0 Channel Interrupt Mask 0 (Base+0x0024) */\r
+ vuint32_t R; /* (For Precision Channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t CIM15:1;\r
+ vuint32_t CIM14:1;\r
+ vuint32_t CIM13:1;\r
+ vuint32_t CIM12:1;\r
+ vuint32_t CIM11:1;\r
+ vuint32_t CIM10:1;\r
+ vuint32_t CIM9:1;\r
+ vuint32_t CIM8:1;\r
+ vuint32_t CIM7:1;\r
+ vuint32_t CIM6:1;\r
+ vuint32_t CIM5:1;\r
+ vuint32_t CIM4:1;\r
+ vuint32_t CIM3:1;\r
+ vuint32_t CIM2:1;\r
+ vuint32_t CIM1:1;\r
+ vuint32_t CIM0:1;\r
+ } B;\r
+ } CIMR0;\r
+\r
+ union { /* ADC0 Channel Interrupt Mask 1 (+0x0028) */\r
+ vuint32_t R; /* (For Standard Channels) */ \r
+ struct {\r
+ vuint32_t CIM63:1;\r
+ vuint32_t CIM62:1;\r
+ vuint32_t CIM61:1;\r
+ vuint32_t CIM60:1;\r
+ vuint32_t CIM59:1;\r
+ vuint32_t CIM58:1;\r
+ vuint32_t CIM57:1;\r
+ vuint32_t CIM56:1;\r
+ vuint32_t CIM55:1;\r
+ vuint32_t CIM54:1;\r
+ vuint32_t CIM53:1;\r
+ vuint32_t CIM52:1;\r
+ vuint32_t CIM51:1;\r
+ vuint32_t CIM50:1;\r
+ vuint32_t CIM49:1;\r
+ vuint32_t CIM48:1;\r
+ vuint32_t CIM47:1;\r
+ vuint32_t CIM46:1;\r
+ vuint32_t CIM45:1;\r
+ vuint32_t CIM44:1;\r
+ vuint32_t CIM43:1;\r
+ vuint32_t CIM42:1;\r
+ vuint32_t CIM41:1;\r
+ vuint32_t CIM40:1;\r
+ vuint32_t CIM39:1;\r
+ vuint32_t CIM38:1;\r
+ vuint32_t CIM37:1;\r
+ vuint32_t CIM36:1;\r
+ vuint32_t CIM35:1;\r
+ vuint32_t CIM34:1;\r
+ vuint32_t CIM33:1;\r
+ vuint32_t CIM32:1;\r
+ } B;\r
+ } CIMR1;\r
+\r
+ union { /* ADC0 Channel Interrupt Mask 2 (+0x002C) */\r
+ vuint32_t R; /* (For PExternal Mux'd Channels) */ \r
+ struct {\r
+ vuint32_t CIM95:1;\r
+ vuint32_t CIM94:1;\r
+ vuint32_t CIM93:1;\r
+ vuint32_t CIM92:1;\r
+ vuint32_t CIM91:1;\r
+ vuint32_t CIM90:1;\r
+ vuint32_t CIM89:1;\r
+ vuint32_t CIM88:1;\r
+ vuint32_t CIM87:1;\r
+ vuint32_t CIM86:1;\r
+ vuint32_t CIM85:1;\r
+ vuint32_t CIM84:1;\r
+ vuint32_t CIM83:1;\r
+ vuint32_t CIM82:1;\r
+ vuint32_t CIM81:1;\r
+ vuint32_t CIM80:1;\r
+ vuint32_t CIM79:1;\r
+ vuint32_t CIM78:1;\r
+ vuint32_t CIM77:1;\r
+ vuint32_t CIM76:1;\r
+ vuint32_t CIM75:1;\r
+ vuint32_t CIM74:1;\r
+ vuint32_t CIM73:1;\r
+ vuint32_t CIM72:1;\r
+ vuint32_t CIM71:1;\r
+ vuint32_t CIM70:1;\r
+ vuint32_t CIM69:1;\r
+ vuint32_t CIM68:1;\r
+ vuint32_t CIM67:1;\r
+ vuint32_t CIM66:1;\r
+ vuint32_t CIM65:1;\r
+ vuint32_t CIM64:1;\r
+ } B;\r
+ } CIMR2; \r
+\r
+ union { /* ADC0 Watchdog Threshold Interrupt Status (+0x0030)*/\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:20;\r
+ vuint32_t WDG5H:1; \r
+ vuint32_t WDG5L:1; \r
+ vuint32_t WDG4H:1; \r
+ vuint32_t WDG4L:1; \r
+ vuint32_t WDG3H:1; \r
+ vuint32_t WDG3L:1; \r
+ vuint32_t WDG2H:1; \r
+ vuint32_t WDG2L:1; \r
+ vuint32_t WDG1H:1;\r
+ vuint32_t WDG1L:1; \r
+ vuint32_t WDG0H:1; \r
+ vuint32_t WDG0L:1; \r
+ } B; \r
+ } WTISR; \r
+ \r
+ union { /* ADC0 Watchdog Threshold Interrupt Mask (+0x0034) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:20;\r
+ vuint32_t MSKWDG5H:1; \r
+ vuint32_t MSKWDG5L:1; \r
+ vuint32_t MSKWDG4H:1; \r
+ vuint32_t MSKWDG4L:1;\r
+ vuint32_t MSKWDG3H:1; \r
+ vuint32_t MSKWDG2H:1; \r
+ vuint32_t MSKWDG1H:1; \r
+ vuint32_t MSKWDG0H:1; \r
+ vuint32_t MSKWDG3L:1; \r
+ vuint32_t MSKWDG2L:1; \r
+ vuint32_t MSKWDG1L:1; \r
+ vuint32_t MSKWDG0L:1; \r
+ } B; \r
+ } WTIMR; \r
+\r
+ vuint8_t ADC0_reserved1[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */\r
+ \r
+ union { /* ADC0 DMA Enable (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t:30;\r
+ vuint32_t DCLR:1;\r
+ vuint32_t DMAEN:1;\r
+ } B;\r
+ } DMAE; \r
+ \r
+ union { /* ADC0 DMA Channel Select 0 (Base+0x0044) */\r
+ vuint32_t R; /* (for precision channels) */\r
+ struct { \r
+ vuint32_t:16;\r
+ vuint32_t DMA15:1;\r
+ vuint32_t DMA14:1;\r
+ vuint32_t DMA13:1;\r
+ vuint32_t DMA12:1;\r
+ vuint32_t DMA11:1;\r
+ vuint32_t DMA10:1;\r
+ vuint32_t DMA9:1;\r
+ vuint32_t DMA8:1;\r
+ vuint32_t DMA7:1;\r
+ vuint32_t DMA6:1;\r
+ vuint32_t DMA5:1;\r
+ vuint32_t DMA4:1;\r
+ vuint32_t DMA3:1;\r
+ vuint32_t DMA2:1;\r
+ vuint32_t DMA1:1;\r
+ vuint32_t DMA0:1;\r
+ } B;\r
+ } DMAR0; \r
+ \r
+ union { /* ADC0 DMA Channel Select 1 (Base+0x0048) */\r
+ vuint32_t R; /* (for standard channels) */ \r
+ struct {\r
+ vuint32_t DMA63:1;\r
+ vuint32_t DMA62:1;\r
+ vuint32_t DMA61:1;\r
+ vuint32_t DMA60:1;\r
+ vuint32_t DMA59:1;\r
+ vuint32_t DMA58:1;\r
+ vuint32_t DMA57:1;\r
+ vuint32_t DMA56:1;\r
+ vuint32_t DMA55:1;\r
+ vuint32_t DMA54:1;\r
+ vuint32_t DMA53:1;\r
+ vuint32_t DMA52:1;\r
+ vuint32_t DMA51:1;\r
+ vuint32_t DMA50:1;\r
+ vuint32_t DMA49:1;\r
+ vuint32_t DMA48:1;\r
+ vuint32_t DMA47:1;\r
+ vuint32_t DMA46:1;\r
+ vuint32_t DMA45:1;\r
+ vuint32_t DMA44:1;\r
+ vuint32_t DMA43:1;\r
+ vuint32_t DMA42:1;\r
+ vuint32_t DMA41:1;\r
+ vuint32_t DMA40:1;\r
+ vuint32_t DMA39:1;\r
+ vuint32_t DMA38:1;\r
+ vuint32_t DMA37:1;\r
+ vuint32_t DMA36:1;\r
+ vuint32_t DMA35:1;\r
+ vuint32_t DMA34:1;\r
+ vuint32_t DMA33:1;\r
+ vuint32_t DMA32:1;\r
+ } B;\r
+ } DMAR1;\r
+\r
+ union { /* ADC0 DMA Channel Select 2 (Base+0x004C) */\r
+ vuint32_t R; /* (for external mux'd channels) */ \r
+ struct {\r
+ vuint32_t DMA95:1;\r
+ vuint32_t DMA94:1;\r
+ vuint32_t DMA93:1;\r
+ vuint32_t DMA92:1;\r
+ vuint32_t DMA91:1;\r
+ vuint32_t DMA90:1;\r
+ vuint32_t DMA89:1;\r
+ vuint32_t DMA88:1;\r
+ vuint32_t DMA87:1;\r
+ vuint32_t DMA86:1;\r
+ vuint32_t DMA85:1;\r
+ vuint32_t DMA84:1;\r
+ vuint32_t DMA83:1;\r
+ vuint32_t DMA82:1;\r
+ vuint32_t DMA81:1;\r
+ vuint32_t DMA80:1;\r
+ vuint32_t DMA79:1;\r
+ vuint32_t DMA78:1;\r
+ vuint32_t DMA77:1;\r
+ vuint32_t DMA76:1;\r
+ vuint32_t DMA75:1;\r
+ vuint32_t DMA74:1;\r
+ vuint32_t DMA73:1;\r
+ vuint32_t DMA72:1;\r
+ vuint32_t DMA71:1;\r
+ vuint32_t DMA70:1;\r
+ vuint32_t DMA69:1;\r
+ vuint32_t DMA68:1;\r
+ vuint32_t DMA67:1;\r
+ vuint32_t DMA66:1;\r
+ vuint32_t DMA65:1;\r
+ vuint32_t DMA64:1;\r
+ } B;\r
+ } DMAR2; \r
+\r
+ vuint8_t ADC0_reserved2[16]; /* Reserved 16 bytes (Base+0x0050-0x005F) */\r
+ \r
+\r
+ /*Note the threshold registers are split [0..3] then [4..5]. For this \r
+ reason thay are NOT implemented as an array in order to maintain \r
+ concistency through all THRHLR registers */ \r
+\r
+ union { /* ADC0 Threshold 0 (Base+0x0060) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR0;\r
+\r
+ union { /* ADC0 Threshold 1 (Base+0x0064) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR1;\r
+\r
+ union { /* ADC0 Threshold 2 (Base+0x0068) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR2;\r
+\r
+ union { /* ADC0 Threshold 3 (Base+0x006C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR3; \r
+ \r
+\r
+ vuint8_t ADC0_reserved3[16]; /* Reserved 16 bytes (Base+0x0070-0x007F) */\r
+ \r
+ union { /* ADC0 Presampling Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:25;\r
+ vuint32_t PREVAL2:2;\r
+ vuint32_t PREVAL1:2;\r
+ vuint32_t PREVAL0:2;\r
+ vuint32_t PRECONV:1; \r
+ } B;\r
+ } PSCR; \r
+\r
+ \r
+ union { /* ADC0 Presampling 0 (Base+0x0084) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t PRES31:1;\r
+ vuint32_t PRES30:1;\r
+ vuint32_t PRES29:1;\r
+ vuint32_t PRES28:1;\r
+ vuint32_t PRES27:1;\r
+ vuint32_t PRES26:1;\r
+ vuint32_t PRES25:1;\r
+ vuint32_t PRES24:1;\r
+ vuint32_t PRES23:1;\r
+ vuint32_t PRES22:1;\r
+ vuint32_t PRES21:1;\r
+ vuint32_t PRES20:1;\r
+ vuint32_t PRES19:1;\r
+ vuint32_t PRES18:1;\r
+ vuint32_t PRES17:1;\r
+ vuint32_t PRES16:1;\r
+ vuint32_t PRES15:1;\r
+ vuint32_t PRES14:1;\r
+ vuint32_t PRES13:1;\r
+ vuint32_t PRES12:1;\r
+ vuint32_t PRES11:1;\r
+ vuint32_t PRES10:1;\r
+ vuint32_t PRES9:1;\r
+ vuint32_t PRES8:1;\r
+ vuint32_t PRES7:1;\r
+ vuint32_t PRES6:1;\r
+ vuint32_t PRES5:1;\r
+ vuint32_t PRES4:1;\r
+ vuint32_t PRES3:1;\r
+ vuint32_t PRES2:1;\r
+ vuint32_t PRES1:1;\r
+ vuint32_t PRES0:1;\r
+ } B;\r
+ } PSR0; \r
+ \r
+ union { /* ADC0 Presampling 1 (Base+0x0088) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t PRES63:1;\r
+ vuint32_t PRES62:1;\r
+ vuint32_t PRES61:1;\r
+ vuint32_t PRES60:1;\r
+ vuint32_t PRES59:1;\r
+ vuint32_t PRES58:1;\r
+ vuint32_t PRES57:1;\r
+ vuint32_t PRES56:1;\r
+ vuint32_t PRES55:1;\r
+ vuint32_t PRES54:1;\r
+ vuint32_t PRES53:1;\r
+ vuint32_t PRES52:1;\r
+ vuint32_t PRES51:1;\r
+ vuint32_t PRES50:1;\r
+ vuint32_t PRES49:1;\r
+ vuint32_t PRES48:1;\r
+ vuint32_t PRES47:1;\r
+ vuint32_t PRES46:1;\r
+ vuint32_t PRES45:1;\r
+ vuint32_t PRES44:1;\r
+ vuint32_t PRES43:1;\r
+ vuint32_t PRES42:1;\r
+ vuint32_t PRES41:1;\r
+ vuint32_t PRES40:1;\r
+ vuint32_t PRES39:1;\r
+ vuint32_t PRES38:1;\r
+ vuint32_t PRES37:1;\r
+ vuint32_t PRES36:1;\r
+ vuint32_t PRES35:1;\r
+ vuint32_t PRES34:1;\r
+ vuint32_t PRES33:1;\r
+ vuint32_t PRES32:1;\r
+ } B;\r
+ } PSR1;\r
+\r
+ union { /* ADC0 Presampling 2 (Base+0x008C) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t PRES95:1;\r
+ vuint32_t PRES94:1;\r
+ vuint32_t PRES93:1;\r
+ vuint32_t PRES92:1;\r
+ vuint32_t PRES91:1;\r
+ vuint32_t PRES90:1;\r
+ vuint32_t PRES89:1;\r
+ vuint32_t PRES88:1;\r
+ vuint32_t PRES87:1;\r
+ vuint32_t PRES86:1;\r
+ vuint32_t PRES85:1;\r
+ vuint32_t PRES84:1;\r
+ vuint32_t PRES83:1;\r
+ vuint32_t PRES82:1;\r
+ vuint32_t PRES81:1;\r
+ vuint32_t PRES80:1;\r
+ vuint32_t PRES79:1;\r
+ vuint32_t PRES78:1;\r
+ vuint32_t PRES77:1;\r
+ vuint32_t PRES76:1;\r
+ vuint32_t PRES75:1;\r
+ vuint32_t PRES74:1;\r
+ vuint32_t PRES73:1;\r
+ vuint32_t PRES72:1;\r
+ vuint32_t PRES71:1;\r
+ vuint32_t PRES70:1;\r
+ vuint32_t PRES69:1;\r
+ vuint32_t PRES68:1;\r
+ vuint32_t PRES67:1;\r
+ vuint32_t PRES66:1;\r
+ vuint32_t PRES65:1;\r
+ vuint32_t PRES64:1;\r
+ } B;\r
+ } PSR2; \r
+\r
+ vuint8_t ADC0_reserved4[4]; /* Reserved 4 bytes (Base+0x0090-0x0093) */\r
+ \r
+ \r
+\r
+ /* Note the following CTR registers are NOT implemented as an array to */\r
+ /* try and maintain some concistency through the header file */\r
+ /* (The registers are however identical) */\r
+\r
+ union { /* ADC0 Conversion Timing 0 (Base+0x0094) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR0;\r
+\r
+ union { /* ADC0 Conversion Timing 1 (Base+0x0098) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR1;\r
+\r
+ union { /* ADC0 Conversion Timing 2 (Base+0x009C) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR2; \r
+\r
+ vuint8_t ADC0_reserved5[4]; /* Reserved 4 bytes (Base+0x00A0-0x00A3) */\r
+ \r
+\r
+union { /* ADC0 Normal Conversion Mask 0 (Base+0x00A4) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } NCMR0;\r
+\r
+ union { /* ADC0 Normal Conversion Mask 1 (Base+0x00A8) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CH59:1;\r
+ vuint32_t CH58:1;\r
+ vuint32_t CH57:1;\r
+ vuint32_t CH56:1;\r
+ vuint32_t CH55:1;\r
+ vuint32_t CH54:1;\r
+ vuint32_t CH53:1;\r
+ vuint32_t CH52:1;\r
+ vuint32_t CH51:1;\r
+ vuint32_t CH50:1;\r
+ vuint32_t CH49:1;\r
+ vuint32_t CH48:1;\r
+ vuint32_t CH47:1;\r
+ vuint32_t CH46:1;\r
+ vuint32_t CH45:1;\r
+ vuint32_t CH44:1;\r
+ vuint32_t CH43:1;\r
+ vuint32_t CH42:1;\r
+ vuint32_t CH41:1;\r
+ vuint32_t CH40:1;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } NCMR1;\r
+\r
+ union { /* ADC0 Normal Conversion Mask 2 (Base+0x00AC) */\r
+ vuint32_t R; /* (For external mux'd channels) */ \r
+ struct {\r
+ vuint32_t CH95:1;\r
+ vuint32_t CH94:1;\r
+ vuint32_t CH93:1;\r
+ vuint32_t CH92:1;\r
+ vuint32_t CH91:1;\r
+ vuint32_t CH90:1;\r
+ vuint32_t CH89:1;\r
+ vuint32_t CH88:1;\r
+ vuint32_t CH87:1;\r
+ vuint32_t CH86:1;\r
+ vuint32_t CH85:1;\r
+ vuint32_t CH84:1;\r
+ vuint32_t CH83:1;\r
+ vuint32_t CH82:1;\r
+ vuint32_t CH81:1;\r
+ vuint32_t CH80:1;\r
+ vuint32_t CH79:1;\r
+ vuint32_t CH78:1;\r
+ vuint32_t CH77:1;\r
+ vuint32_t CH76:1;\r
+ vuint32_t CH75:1;\r
+ vuint32_t CH74:1;\r
+ vuint32_t CH73:1;\r
+ vuint32_t CH72:1;\r
+ vuint32_t CH71:1;\r
+ vuint32_t CH70:1;\r
+ vuint32_t CH69:1;\r
+ vuint32_t CH68:1;\r
+ vuint32_t CH67:1;\r
+ vuint32_t CH66:1;\r
+ vuint32_t CH65:1;\r
+ vuint32_t CH64:1;\r
+ } B;\r
+ } NCMR2; \r
+\r
+vuint8_t ADC0_reserved6[4]; /* Reserved 4 bytes (Base+0x00B0-0x00B3) */\r
+\r
+ \r
+ union { /* ADC0 Injected Conversion Mask0 (Base+0x00B4) */\r
+ vuint32_t R; /* (precision channels) */ \r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } JCMR0;\r
+\r
+ union { /* ADC0 Injected Conversion Mask1 (Base+0x00B8) */\r
+ vuint32_t R; /* (standard channels) */ \r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CH59:1;\r
+ vuint32_t CH58:1;\r
+ vuint32_t CH57:1;\r
+ vuint32_t CH56:1;\r
+ vuint32_t CH55:1;\r
+ vuint32_t CH54:1;\r
+ vuint32_t CH53:1;\r
+ vuint32_t CH52:1;\r
+ vuint32_t CH51:1;\r
+ vuint32_t CH50:1;\r
+ vuint32_t CH49:1;\r
+ vuint32_t CH48:1;\r
+ vuint32_t CH47:1;\r
+ vuint32_t CH46:1;\r
+ vuint32_t CH45:1;\r
+ vuint32_t CH44:1;\r
+ vuint32_t CH43:1;\r
+ vuint32_t CH42:1;\r
+ vuint32_t CH41:1;\r
+ vuint32_t CH40:1;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } JCMR1;\r
+\r
+ union { /* ADC0 Injected Conversion Mask2 (Base+0x00BC) */\r
+ vuint32_t R; /* (external mux'd channels) */ \r
+ struct {\r
+ vuint32_t CH95:1;\r
+ vuint32_t CH94:1;\r
+ vuint32_t CH93:1;\r
+ vuint32_t CH92:1;\r
+ vuint32_t CH91:1;\r
+ vuint32_t CH90:1;\r
+ vuint32_t CH89:1;\r
+ vuint32_t CH88:1;\r
+ vuint32_t CH87:1;\r
+ vuint32_t CH86:1;\r
+ vuint32_t CH85:1;\r
+ vuint32_t CH84:1;\r
+ vuint32_t CH83:1;\r
+ vuint32_t CH82:1;\r
+ vuint32_t CH81:1;\r
+ vuint32_t CH80:1;\r
+ vuint32_t CH79:1;\r
+ vuint32_t CH78:1;\r
+ vuint32_t CH77:1;\r
+ vuint32_t CH76:1;\r
+ vuint32_t CH75:1;\r
+ vuint32_t CH74:1;\r
+ vuint32_t CH73:1;\r
+ vuint32_t CH72:1;\r
+ vuint32_t CH71:1;\r
+ vuint32_t CH70:1;\r
+ vuint32_t CH69:1;\r
+ vuint32_t CH68:1;\r
+ vuint32_t CH67:1;\r
+ vuint32_t CH66:1;\r
+ vuint32_t CH65:1;\r
+ vuint32_t CH64:1;\r
+ } B;\r
+ } JCMR2;\r
+ \r
+ \r
+ vuint8_t ADC0_reserved7[4]; /* Reserved 4 bytes (Base+0x00C0-0x00C3) */\r
+ \r
+ union { /* ADC0 Decode Signals Delay (Base+0x00C4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t DSD:12;\r
+ } B;\r
+ } DSDR; \r
+ \r
+ union { /* ADC0 Power-Down exit Delay (Base+0x00C8) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t PDED:8;\r
+ } B;\r
+ } PDEDR; \r
+\r
+ \r
+ vuint8_t ADC0_reserved8[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */\r
+ \r
+ union { /* ADC0 Channel 0-95 Data (Base+0x0100-0x027C) */\r
+ vuint32_t R; /* Note CDR[16..31] and CDR[60..63] are reserved */\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t VALID:1;\r
+ vuint32_t OVERW:1;\r
+ vuint32_t RESULT:2;\r
+ vuint32_t:6;\r
+ vuint32_t CDATA:10;\r
+ } B;\r
+ } CDR[96]; \r
+ \r
+ union { /* ADC0 Threshold 4 (Base+0x0280) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR4;\r
+\r
+ union { /* ADC0 Threshold 5 (Base+0x0284) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t THRH:10;\r
+ vuint32_t:6;\r
+ vuint32_t THRL:10;\r
+ } B;\r
+ } THRHLR5;\r
+ \r
+ vuint8_t ADC0_reserved9[40]; /* Reserved 40 bytes (Base+0x0288-0x02AF) */\r
+ \r
+ \r
+ union { /* ADC0 Channel Watchdog Select 0 (Base+0x02B0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH7:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH6:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH5:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH4:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH3:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH2:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH1:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH0:3;\r
+ } B;\r
+ } CWSELR0; \r
+ \r
+ union { /* ADC0 Channel Watchdog Select 1 (Base+0x02B4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH15:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH14:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH13:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH12:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH11:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH10:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH9:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH8:3;\r
+ } B;\r
+ } CWSELR1; \r
+ \r
+ vuint8_t ADC0_reserved10[8]; /* Reserved 4 bytes (Base+0x02B8-0x02BF) */ \r
+ \r
+ union { /* ADC0 Channel Watchdog Select 4 (Base+0x02C0) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH39:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH38:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH37:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH36:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH35:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH34:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH33:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH32:3;\r
+ } B;\r
+ } CWSELR4;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 5 (Base+0x02C4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH47:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH46:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH45:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH44:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH43:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH42:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH41:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH40:3;\r
+ } B;\r
+ } CWSELR5;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 6 (Base+0x02C8) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH55:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH54:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH53:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH52:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH51:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH50:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH49:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH48:3;\r
+ } B;\r
+ } CWSELR6;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 7 (Base+0x02CC) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH63:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH62:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH61:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH60:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH59:3;\r
+ vuint32_t:12;\r
+ } B;\r
+ } CWSELR7;\r
+ \r
+ union { /* ADC0 Channel Watchdog Select 8 (Base+0x02D0) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH71:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH70:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH69:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH68:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH67:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH66:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH65:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH64:3;\r
+ } B;\r
+ } CWSELR8;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 9 (Base+0x02D4) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH79:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH78:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH77:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH76:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH75:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH74:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH73:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH72:3;\r
+ } B;\r
+ } CWSELR9;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 10 (Base+0x02D8)*/\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH87:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH86:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH85:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH84:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH83:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH82:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH81:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH80:3;\r
+ } B;\r
+ } CWSELR10;\r
+\r
+ union { /* ADC0 Channel Watchdog Select 11 (Base+0x02DC)*/\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH95:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH94:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH93:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH92:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH91:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH90:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH89:3;\r
+ vuint32_t:1;\r
+ vuint32_t WSEL_CH88:3;\r
+ } B;\r
+ } CWSELR11;\r
+ \r
+ union { /* ADC0 Channel Watchdog Enable0 (Base++0x02E0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CWEN15:1;\r
+ vuint32_t CWEN14:1;\r
+ vuint32_t CWEN13:1;\r
+ vuint32_t CWEN12:1;\r
+ vuint32_t CWEN11:1;\r
+ vuint32_t CWEN10:1;\r
+ vuint32_t CWEN9:1;\r
+ vuint32_t CWEN8:1;\r
+ vuint32_t CWEN7:1;\r
+ vuint32_t CWEN6:1;\r
+ vuint32_t CWEN5:1;\r
+ vuint32_t CWEN4:1;\r
+ vuint32_t CWEN3:1;\r
+ vuint32_t CWEN2:1;\r
+ vuint32_t CWEN1:1;\r
+ vuint32_t CWEN0:1;\r
+ } B;\r
+ } CWENR0;\r
+\r
+ union { /* ADC0 Channel Watchdog Enable1 (Base++0x02E4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CWEN59:1;\r
+ vuint32_t CWEN58:1;\r
+ vuint32_t CWEN57:1;\r
+ vuint32_t CWEN56:1;\r
+ vuint32_t CWEN55:1;\r
+ vuint32_t CWEN54:1;\r
+ vuint32_t CWEN53:1;\r
+ vuint32_t CWEN52:1;\r
+ vuint32_t CWEN51:1;\r
+ vuint32_t CWEN50:1;\r
+ vuint32_t CWEN49:1;\r
+ vuint32_t CWEN48:1;\r
+ vuint32_t CWEN47:1;\r
+ vuint32_t CWEN46:1;\r
+ vuint32_t CWEN45:1;\r
+ vuint32_t CWEN44:1;\r
+ vuint32_t CWEN43:1;\r
+ vuint32_t CWEN42:1;\r
+ vuint32_t CWEN41:1;\r
+ vuint32_t CWEN40:1;\r
+ vuint32_t CWEN39:1;\r
+ vuint32_t CWEN38:1;\r
+ vuint32_t CWEN37:1;\r
+ vuint32_t CWEN36:1;\r
+ vuint32_t CWEN35:1;\r
+ vuint32_t CWEN34:1;\r
+ vuint32_t CWEN33:1;\r
+ vuint32_t CWEN32:1;\r
+ } B;\r
+ } CWENR1;\r
+\r
+ union { /* ADC0 Channel Watchdog Enable2 (Base++0x02E8) */\r
+ vuint32_t R; /* (external mux'd channels) */\r
+ struct {\r
+ vuint32_t CWEN95:1;\r
+ vuint32_t CWEN94:1;\r
+ vuint32_t CWEN93:1;\r
+ vuint32_t CWEN92:1;\r
+ vuint32_t CWEN91:1;\r
+ vuint32_t CWEN90:1;\r
+ vuint32_t CWEN89:1;\r
+ vuint32_t CWEN88:1;\r
+ vuint32_t CWEN87:1;\r
+ vuint32_t CWEN86:1;\r
+ vuint32_t CWEN85:1;\r
+ vuint32_t CWEN84:1;\r
+ vuint32_t CWEN83:1;\r
+ vuint32_t CWEN82:1;\r
+ vuint32_t CWEN81:1;\r
+ vuint32_t CWEN80:1;\r
+ vuint32_t CWEN79:1;\r
+ vuint32_t CWEN78:1;\r
+ vuint32_t CWEN77:1;\r
+ vuint32_t CWEN76:1;\r
+ vuint32_t CWEN75:1;\r
+ vuint32_t CWEN74:1;\r
+ vuint32_t CWEN73:1;\r
+ vuint32_t CWEN72:1;\r
+ vuint32_t CWEN71:1;\r
+ vuint32_t CWEN70:1;\r
+ vuint32_t CWEN69:1;\r
+ vuint32_t CWEN68:1;\r
+ vuint32_t CWEN67:1;\r
+ vuint32_t CWEN66:1;\r
+ vuint32_t CWEN65:1;\r
+ vuint32_t CWEN64:1;\r
+ } B;\r
+ } CWENR2;\r
+\r
+ vuint8_t ADC0_reserved11[4]; /* Reserved 4 bytes (Base+0x02EC-0x02EF) */\r
+ \r
+union { /* ADC0 Watchdog out of range 0 (Base+0x02F0) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t AWORR_CH15:1;\r
+ vuint32_t AWORR_CH14:1;\r
+ vuint32_t AWORR_CH13:1;\r
+ vuint32_t AWORR_CH12:1;\r
+ vuint32_t AWORR_CH11:1;\r
+ vuint32_t AWORR_CH10:1;\r
+ vuint32_t AWORR_CH9:1;\r
+ vuint32_t AWORR_CH8:1;\r
+ vuint32_t AWORR_CH7:1;\r
+ vuint32_t AWORR_CH6:1;\r
+ vuint32_t AWORR_CH5:1;\r
+ vuint32_t AWORR_CH4:1;\r
+ vuint32_t AWORR_CH3:1;\r
+ vuint32_t AWORR_CH2:1;\r
+ vuint32_t AWORR_CH1:1;\r
+ vuint32_t AWORR_CH0:1;\r
+ } B;\r
+ } AWORR0;\r
+\r
+ union { /* ADC0 Watchdog out of range 1 (Base+0x02F4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t AWORR_CH59:1;\r
+ vuint32_t AWORR_CH58:1;\r
+ vuint32_t AWORR_CH57:1;\r
+ vuint32_t AWORR_CH56:1;\r
+ vuint32_t AWORR_CH55:1;\r
+ vuint32_t AWORR_CH54:1;\r
+ vuint32_t AWORR_CH53:1;\r
+ vuint32_t AWORR_CH52:1;\r
+ vuint32_t AWORR_CH51:1;\r
+ vuint32_t AWORR_CH50:1;\r
+ vuint32_t AWORR_CH49:1;\r
+ vuint32_t AWORR_CH48:1;\r
+ vuint32_t AWORR_CH47:1;\r
+ vuint32_t AWORR_CH46:1;\r
+ vuint32_t AWORR_CH45:1;\r
+ vuint32_t AWORR_CH44:1;\r
+ vuint32_t AWORR_CH43:1;\r
+ vuint32_t AWORR_CH42:1;\r
+ vuint32_t AWORR_CH41:1;\r
+ vuint32_t AWORR_CH40:1;\r
+ vuint32_t AWORR_CH39:1;\r
+ vuint32_t AWORR_CH38:1;\r
+ vuint32_t AWORR_CH37:1;\r
+ vuint32_t AWORR_CH36:1;\r
+ vuint32_t AWORR_CH35:1;\r
+ vuint32_t AWORR_CH34:1;\r
+ vuint32_t AWORR_CH33:1;\r
+ vuint32_t AWORR_CH32:1;\r
+ } B;\r
+ } AWORR1;\r
+\r
+ union { /* ADC0 Watchdog out of range 2 (Base+0x02F8) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t AWORR_CH95:1;\r
+ vuint32_t AWORR_CH94:1;\r
+ vuint32_t AWORR_CH93:1;\r
+ vuint32_t AWORR_CH92:1;\r
+ vuint32_t AWORR_CH91:1;\r
+ vuint32_t AWORR_CH90:1;\r
+ vuint32_t AWORR_CH89:1;\r
+ vuint32_t AWORR_CH88:1;\r
+ vuint32_t AWORR_CH87:1;\r
+ vuint32_t AWORR_CH86:1;\r
+ vuint32_t AWORR_CH85:1;\r
+ vuint32_t AWORR_CH84:1;\r
+ vuint32_t AWORR_CH83:1;\r
+ vuint32_t AWORR_CH82:1;\r
+ vuint32_t AWORR_CH81:1;\r
+ vuint32_t AWORR_CH80:1;\r
+ vuint32_t AWORR_CH79:1;\r
+ vuint32_t AWORR_CH78:1;\r
+ vuint32_t AWORR_CH77:1;\r
+ vuint32_t AWORR_CH76:1;\r
+ vuint32_t AWORR_CH75:1;\r
+ vuint32_t AWORR_CH74:1;\r
+ vuint32_t AWORR_CH73:1;\r
+ vuint32_t AWORR_CH72:1;\r
+ vuint32_t AWORR_CH71:1;\r
+ vuint32_t AWORR_CH70:1;\r
+ vuint32_t AWORR_CH69:1;\r
+ vuint32_t AWORR_CH68:1;\r
+ vuint32_t AWORR_CH67:1;\r
+ vuint32_t AWORR_CH66:1;\r
+ vuint32_t AWORR_CH65:1;\r
+ vuint32_t AWORR_CH64:1;\r
+ } B;\r
+ } AWORR2;\r
+\r
+ //vuint8_t ADC0_reserved12[15620]; /* Reserved 15620 bytes (Base+0x02FC-0x3FFF) */ \r
+ \r
+}; /* end of ADC0_tag */ \r
+\r
+/****************************************************************************/\r
+/* MODULE : ADC1 (12 Bit) */\r
+/****************************************************************************/\r
+struct ADC1_tag {\r
+\r
+ union { /* ADC1 Main Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OWREN:1;\r
+ vuint32_t WLSIDE:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t:4;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t:1;\r
+ vuint32_t JTRGEN:1;\r
+ vuint32_t JEDGE:1;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:2;\r
+ vuint32_t CTUEN:1;\r
+ vuint32_t:8;\r
+ vuint32_t ADCLKSEL:1;\r
+ vuint32_t ABORT_CHAIN:1;\r
+ vuint32_t ABORT:1;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:2;\r
+ vuint32_t:2;\r
+ vuint32_t PWDN:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* ADC1 Main Status (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:7;\r
+ vuint32_t NSTART:1;\r
+ vuint32_t JABORT:1;\r
+ vuint32_t:2;\r
+ vuint32_t JSTART:1;\r
+ vuint32_t:3;\r
+ vuint32_t CTUSTART:1;\r
+ vuint32_t CHADDR:7;\r
+ vuint32_t:3;\r
+ vuint32_t ACKO:1;\r
+ vuint32_t:2;\r
+ vuint32_t ADCSTATUS:3;\r
+ } B;\r
+ } MSR;\r
+\r
+ vuint8_t ADC1_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */\r
+\r
+ union { /* ADC1 Interrupt Status (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t EOCTU:1;\r
+ vuint32_t JEOC:1;\r
+ vuint32_t JECH:1;\r
+ vuint32_t EOC:1;\r
+ vuint32_t ECH:1;\r
+ } B;\r
+ } ISR;\r
+\r
+ union { /* ADC1 Channel Pending 0 (Base+0x0014) */\r
+ vuint32_t R; /* (For precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t EOC_CH15:1;\r
+ vuint32_t EOC_CH14:1;\r
+ vuint32_t EOC_CH13:1;\r
+ vuint32_t EOC_CH12:1;\r
+ vuint32_t EOC_CH11:1;\r
+ vuint32_t EOC_CH10:1;\r
+ vuint32_t EOC_CH9:1;\r
+ vuint32_t EOC_CH8:1;\r
+ vuint32_t EOC_CH7:1;\r
+ vuint32_t EOC_CH6:1;\r
+ vuint32_t EOC_CH5:1;\r
+ vuint32_t EOC_CH4:1;\r
+ vuint32_t EOC_CH3:1;\r
+ vuint32_t EOC_CH2:1;\r
+ vuint32_t EOC_CH1:1;\r
+ vuint32_t EOC_CH0:1;\r
+ } B;\r
+ } CE0CFR0;\r
+\r
+ union { /* ADC1 Channel Pending 1 (Base+0x0018) */\r
+ vuint32_t R; /* (For standard Channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t EOC_CH39:1;\r
+ vuint32_t EOC_CH38:1;\r
+ vuint32_t EOC_CH37:1;\r
+ vuint32_t EOC_CH36:1;\r
+ vuint32_t EOC_CH35:1;\r
+ vuint32_t EOC_CH34:1;\r
+ vuint32_t EOC_CH33:1;\r
+ vuint32_t EOC_CH32:1;\r
+ } B;\r
+ } CE0CFR1;\r
+\r
+ vuint8_t ADC1_reserved1[4]; /* Reserved 4 bytes (Base+0x001C-0x001F) */\r
+\r
+ union { /* ADC1 Interrupt Mask (Base+0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t MSKEOCTU:1;\r
+ vuint32_t MSKJEOC:1;\r
+ vuint32_t MSKJECH:1;\r
+ vuint32_t MSKEOC:1;\r
+ vuint32_t MSKECH:1;\r
+ } B;\r
+ } IMR;\r
+\r
+ union { /* ADC1 Channel Interrupt Mask 0 (Base+0x0024) */\r
+ vuint32_t R; /* (For Precision Channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t CIM15:1;\r
+ vuint32_t CIM14:1;\r
+ vuint32_t CIM13:1;\r
+ vuint32_t CIM12:1;\r
+ vuint32_t CIM11:1;\r
+ vuint32_t CIM10:1;\r
+ vuint32_t CIM9:1;\r
+ vuint32_t CIM8:1;\r
+ vuint32_t CIM7:1;\r
+ vuint32_t CIM6:1;\r
+ vuint32_t CIM5:1;\r
+ vuint32_t CIM4:1;\r
+ vuint32_t CIM3:1;\r
+ vuint32_t CIM2:1;\r
+ vuint32_t CIM1:1;\r
+ vuint32_t CIM0:1;\r
+ } B;\r
+ } CIMR0;\r
+\r
+ union { /* ADC1 Channel Interrupt Mask 1 (+0x0028) */\r
+ vuint32_t R; /* (For Standard Channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CIM39:1;\r
+ vuint32_t CIM38:1;\r
+ vuint32_t CIM37:1;\r
+ vuint32_t CIM36:1;\r
+ vuint32_t CIM35:1;\r
+ vuint32_t CIM34:1;\r
+ vuint32_t CIM33:1;\r
+ vuint32_t CIM32:1;\r
+ } B;\r
+ } CIMR1;\r
+\r
+ vuint8_t ADC1_reserved2[4]; /* Reserved 4 bytes (Base+0x002C-0x002F) */\r
+\r
+ union { /* ADC1 Watchdog Threshold Interrupt Status (+0x0030)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t WDG2H:1;\r
+ vuint32_t WDG2L:1;\r
+ vuint32_t WDG1H:1;\r
+ vuint32_t WDG1L:1;\r
+ vuint32_t WDG0H:1;\r
+ vuint32_t WDG0L:1;\r
+ } B;\r
+ } WTISR;\r
+\r
+ union { /* ADC1 Watchdog Threshold Interrupt Mask (+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t MSKWDG2H:1;\r
+ vuint32_t MSKWDG2L:1;\r
+ vuint32_t MSKWDG1H:1;\r
+ vuint32_t MSKWDG1L:1;\r
+ vuint32_t MSKWDG0H:1;\r
+ vuint32_t MSKWDG0L:1;\r
+ } B;\r
+ } WTIMR;\r
+\r
+ vuint8_t ADC1_reserved3[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */\r
+\r
+ union { /* ADC1 DMA Enable (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t DCLR:1;\r
+ vuint32_t DMAEN:1;\r
+ } B;\r
+ } DMAE;\r
+\r
+ union { /* ADC1 DMA Channel Select 0 (Base+0x0044) */\r
+ vuint32_t R; /* (for precision channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DMA15:1;\r
+ vuint32_t DMA14:1;\r
+ vuint32_t DMA13:1;\r
+ vuint32_t DMA12:1;\r
+ vuint32_t DMA11:1;\r
+ vuint32_t DMA10:1;\r
+ vuint32_t DMA9:1;\r
+ vuint32_t DMA8:1;\r
+ vuint32_t DMA7:1;\r
+ vuint32_t DMA6:1;\r
+ vuint32_t DMA5:1;\r
+ vuint32_t DMA4:1;\r
+ vuint32_t DMA3:1;\r
+ vuint32_t DMA2:1;\r
+ vuint32_t DMA1:1;\r
+ vuint32_t DMA0:1;\r
+ } B;\r
+ } DMAR0;\r
+\r
+ union { /* ADC1 DMA Channel Select 1 (Base+0x0048) */\r
+ vuint32_t R; /* (for standard channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t DMA39:1;\r
+ vuint32_t DMA38:1;\r
+ vuint32_t DMA37:1;\r
+ vuint32_t DMA36:1;\r
+ vuint32_t DMA35:1;\r
+ vuint32_t DMA34:1;\r
+ vuint32_t DMA33:1;\r
+ vuint32_t DMA32:1;\r
+ } B;\r
+ } DMAR1;\r
+\r
+ vuint8_t ADC1_reserved4[20]; /* Reserved 20 bytes (Base+0x004C-0x005F) */\r
+\r
+ /* Note the threshold registers are not implemented as an array for */\r
+ /* concistency with ADC0 header section */\r
+\r
+ union { /* ADC1 Threshold 0 (Base+0x0060) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t THRH:12;\r
+ vuint32_t:4;\r
+ vuint32_t THRL:12;\r
+ } B;\r
+ } THRHLR0;\r
+\r
+ union { /* ADC1 Threshold 1 (Base+0x0064) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t THRH:12;\r
+ vuint32_t:4;\r
+ vuint32_t THRL:12;\r
+ } B;\r
+ } THRHLR1;\r
+\r
+ union { /* ADC1 Threshold 2 (Base+0x0068) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t THRH:12;\r
+ vuint32_t:4;\r
+ vuint32_t THRL:12;\r
+ } B;\r
+ } THRHLR2;\r
+\r
+ vuint8_t ADC1_reserved5[20]; /* Reserved 20 bytes (Base+0x006C-0x007F) */\r
+\r
+ union { /* ADC1 Presampling Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:25;\r
+ vuint32_t PREVAL2:2;\r
+ vuint32_t PREVAL1:2;\r
+ vuint32_t PREVAL0:2;\r
+ vuint32_t PRECONV:1;\r
+ } B;\r
+ } PSCR;\r
+\r
+ union { /* ADC1 Presampling 0 (Base+0x0084) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t PRES15:1;\r
+ vuint32_t PRES14:1;\r
+ vuint32_t PRES13:1;\r
+ vuint32_t PRES12:1;\r
+ vuint32_t PRES11:1;\r
+ vuint32_t PRES10:1;\r
+ vuint32_t PRES9:1;\r
+ vuint32_t PRES8:1;\r
+ vuint32_t PRES7:1;\r
+ vuint32_t PRES6:1;\r
+ vuint32_t PRES5:1;\r
+ vuint32_t PRES4:1;\r
+ vuint32_t PRES3:1;\r
+ vuint32_t PRES2:1;\r
+ vuint32_t PRES1:1;\r
+ vuint32_t PRES0:1;\r
+ } B;\r
+ } PSR0;\r
+\r
+ union { /* ADC1 Presampling 1 (Base+0x0088) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t PRES39:1;\r
+ vuint32_t PRES38:1;\r
+ vuint32_t PRES37:1;\r
+ vuint32_t PRES36:1;\r
+ vuint32_t PRES35:1;\r
+ vuint32_t PRES34:1;\r
+ vuint32_t PRES33:1;\r
+ vuint32_t PRES32:1;\r
+ } B;\r
+ } PSR1;\r
+\r
+ vuint8_t ADC1_reserved6[8]; /* Reserved 8 bytes (Base+0x008C-0x0093) */\r
+\r
+ /* Note the following CTR registers are NOT implemented as an array to */\r
+ /* try and maintain some concistency through the header file */\r
+ /* (The registers are however identical) */\r
+\r
+ union { /* ADC1 Conversion Timing 0 (Base+0x0094) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR0;\r
+\r
+ union { /* ADC1 Conversion Timing 1 (Base+0x0098) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t INPLATCH:1;\r
+ vuint32_t:1;\r
+ vuint32_t OFFSHIFT:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPCMP:2;\r
+ vuint32_t:1;\r
+ vuint32_t INPSAMP:8;\r
+ } B;\r
+ } CTR1;\r
+\r
+ vuint8_t ADC1_reserved7[8]; /* Reserved 8 bytes (Base+0x009C-0x00A3) */\r
+\r
+ union { /* ADC1 Normal Conversion Mask 0 (Base+0x00A4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } NCMR0;\r
+\r
+ union { /* ADC1 Normal Conversion Mask 1 (Base+0x00A8) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } NCMR1;\r
+\r
+ vuint8_t ADC1_reserved8[8]; /* Reserved 8 bytes (Base+0x00AC-0x00B3) */\r
+\r
+ union { /* ADC1 Injected Conversion Mask0 (Base+0x00B4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CH15:1;\r
+ vuint32_t CH14:1;\r
+ vuint32_t CH13:1;\r
+ vuint32_t CH12:1;\r
+ vuint32_t CH11:1;\r
+ vuint32_t CH10:1;\r
+ vuint32_t CH9:1;\r
+ vuint32_t CH8:1;\r
+ vuint32_t CH7:1;\r
+ vuint32_t CH6:1;\r
+ vuint32_t CH5:1;\r
+ vuint32_t CH4:1;\r
+ vuint32_t CH3:1;\r
+ vuint32_t CH2:1;\r
+ vuint32_t CH1:1;\r
+ vuint32_t CH0:1;\r
+ } B;\r
+ } JCMR0;\r
+\r
+ union { /* ADC1 Injected Conversion Mask1 (Base+0x00B8) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t CH39:1;\r
+ vuint32_t CH38:1;\r
+ vuint32_t CH37:1;\r
+ vuint32_t CH36:1;\r
+ vuint32_t CH35:1;\r
+ vuint32_t CH34:1;\r
+ vuint32_t CH33:1;\r
+ vuint32_t CH32:1;\r
+ } B;\r
+ } JCMR1;\r
+\r
+ vuint8_t ADC1_reserved9[12]; /* Reserved 12 bytes (Base+0x00BC-0x00C7) */\r
+ \r
+ union { /* Power Down Exit Delay Register (base+0x00C8)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24; \r
+ vuint32_t PDED:8;\r
+ } B;\r
+ } PDEDR; \r
+\r
+ vuint8_t ADC1_reserved10[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */ \r
+\r
+ union { /* ADC1 Channel 0-39 Data (Base+0x0100-0x019C) */\r
+ vuint32_t R; /* Note CDR[16..31] are reserved 0x0140-0x017F */\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t VALID:1;\r
+ vuint32_t OVERW:1;\r
+ vuint32_t RESULT:2;\r
+ vuint32_t:4;\r
+ vuint32_t CDATA:12;\r
+ } B;\r
+ } CDR[40];\r
+\r
+ vuint8_t ADC1_reserved11[272]; /* Reserved 252 bytes (Base+0x01A0-0x002AF) */\r
+\r
+ union { /* ADC1 Channel Watchdog Select 0 (Base+0x02B0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH7:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH6:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH5:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH4:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH3:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH2:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH1:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH0:2;\r
+ } B;\r
+ } CWSELR0;\r
+\r
+ union { /* ADC1 Channel Watchdog Select 1 (Base+0x02B4) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH15:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH14:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH13:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH12:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH11:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH10:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH9:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH8:2;\r
+ } B;\r
+ } CWSELR1;\r
+\r
+ vuint8_t ADC1_reserved12[8]; /* Reserved 8 bytes (Base+0x02B8-0x02BF) */\r
+\r
+ union { /* ADC1 Channel Watchdog Select 4 (Base+0x02C0) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH39:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH38:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH37:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH36:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH35:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH34:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH33:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH32:2;\r
+ } B;\r
+ } CWSELR4;\r
+\r
+ union { /* ADC1 Channel Watchdog Select 5 (Base+0x02C4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t WSEL_CH44:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH43:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH42:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH41:2;\r
+ vuint32_t:2;\r
+ vuint32_t WSEL_CH40:2;\r
+ } B;\r
+ } CWSELR5;\r
+\r
+ vuint8_t ADC1_reserved13[24]; /* Reserved 24 bytes (Base+0x02C8-0x02DF) */\r
+\r
+ union { /* ADC1 Channel Watchdog Enable0 (Base+0x02E0) */\r
+ vuint32_t R; /* (precision channels) */\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CWEN15:1;\r
+ vuint32_t CWEN14:1;\r
+ vuint32_t CWEN13:1;\r
+ vuint32_t CWEN12:1;\r
+ vuint32_t CWEN11:1;\r
+ vuint32_t CWEN10:1;\r
+ vuint32_t CWEN9:1;\r
+ vuint32_t CWEN8:1;\r
+ vuint32_t CWEN7:1;\r
+ vuint32_t CWEN6:1;\r
+ vuint32_t CWEN5:1;\r
+ vuint32_t CWEN4:1;\r
+ vuint32_t CWEN3:1;\r
+ vuint32_t CWEN2:1;\r
+ vuint32_t CWEN1:1;\r
+ vuint32_t CWEN0:1;\r
+ } B;\r
+ } CWENR0;\r
+\r
+ union { /* ADC1 Channel Watchdog Enable1 (Base++0x02E4) */\r
+ vuint32_t R; /* (standard channels) */\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t CWEN39:1;\r
+ vuint32_t CWEN38:1;\r
+ vuint32_t CWEN37:1;\r
+ vuint32_t CWEN36:1;\r
+ vuint32_t CWEN35:1;\r
+ vuint32_t CWEN34:1;\r
+ vuint32_t CWEN33:1;\r
+ vuint32_t CWEN32:1;\r
+ } B;\r
+ } CWENR1;\r
+\r
+ vuint8_t ADC1_reserved14[8]; /* Reserved 8 bytes (Base+0x02E8-0x02EF) */\r
+\r
+ union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t AWORR_CH15:1;\r
+ vuint32_t AWORR_CH14:1;\r
+ vuint32_t AWORR_CH13:1;\r
+ vuint32_t AWORR_CH12:1;\r
+ vuint32_t AWORR_CH11:1;\r
+ vuint32_t AWORR_CH10:1;\r
+ vuint32_t AWORR_CH9:1;\r
+ vuint32_t AWORR_CH8:1;\r
+ vuint32_t AWORR_CH7:1;\r
+ vuint32_t AWORR_CH6:1;\r
+ vuint32_t AWORR_CH5:1;\r
+ vuint32_t AWORR_CH4:1;\r
+ vuint32_t AWORR_CH3:1;\r
+ vuint32_t AWORR_CH2:1;\r
+ vuint32_t AWORR_CH1:1;\r
+ vuint32_t AWORR_CH0:1;\r
+ } B;\r
+ } AWORR0;\r
+\r
+ union { /* ADC1 Watchdog out of range 1 (Base+0x02F4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t AWORR_CH39:1;\r
+ vuint32_t AWORR_CH38:1;\r
+ vuint32_t AWORR_CH37:1;\r
+ vuint32_t AWORR_CH36:1;\r
+ vuint32_t AWORR_CH35:1;\r
+ vuint32_t AWORR_CH34:1;\r
+ vuint32_t AWORR_CH33:1;\r
+ vuint32_t AWORR_CH32:1;\r
+ } B;\r
+ } AWORR1;\r
+\r
+ vuint8_t ADC1_reserved15[8]; /* Reserved 8 bytes (Base+0x02F8-0x02FF) */\r
+\r
+}; /* end of ADC1_tag */ \r
+/****************************************************************************/\r
+/* MODULE : CANSP */\r
+/****************************************************************************/\r
+ struct CANSP_tag {\r
+ \r
+ union { /* CANSP Control Reg (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RX_COMPLETE:1;\r
+ vuint32_t BUSY:1;\r
+ vuint32_t ACTIVE_CK:1;\r
+ vuint32_t:3;\r
+ vuint32_t MODE:1;\r
+ vuint32_t CAN_RX_SEL:3;\r
+ vuint32_t BRP:5;\r
+ vuint32_t CAN_SMPLR_EN:1;\r
+ } B;\r
+ } CR; \r
+\r
+ union { /* CANSP Sample 0..11 (Base+0x0000-0x0030)*/\r
+ vuint32_t R;\r
+ } SR[12];\r
+\r
+ }; /* end of CANSP_tag */ \r
+/****************************************************************************/\r
+/* MODULE : ECSM */\r
+/****************************************************************************/\r
+struct ECSM_tag{\r
+\r
+ union { /* ECSM Processor Core Type (Base+0x0000) */\r
+ vuint16_t R;\r
+ } PCT;\r
+\r
+ union { /* ECSM Revision (Base+0x0002) */\r
+ vuint16_t R;\r
+ } REV;\r
+\r
+ vuint8_t ECSM_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* ECSM IPS Module Configuration (Base+0x0008) */\r
+ vuint32_t R;\r
+ } IMC;\r
+\r
+ vuint8_t ECSM_reserved1[7]; /* Reserved 7 bytes (Base+0x000C-0x0012) */\r
+\r
+ union { /* ECSM Miscellaneous Wakeup Control (+0x0013) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ENBWCR:1;\r
+ vuint8_t :3;\r
+ vuint8_t PRILVL:4;\r
+ } B;\r
+ } MWCR;\r
+\r
+ vuint8_t ECSM_reserved2[11]; /* Reserved 11 bytes (Base+0x0014-0x001E) */\r
+\r
+ union { /* ECSM Miscellaneous Interrupt (Base+0x001F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t FB0AI:1;\r
+ vuint8_t FB0SI:1;\r
+ vuint8_t FB1AI:1;\r
+ vuint8_t FB1SI:1;\r
+ vuint8_t :4;\r
+ } B;\r
+ } MIR;\r
+\r
+ vuint8_t ECSM_reserved3[4]; /* Reserved 4 bytes (Base+0x0020-0x0023) */\r
+\r
+ union { /*ECSM Miscellaneous User-Defined Control (+0x0024)*/\r
+ vuint32_t R;\r
+ } MUDCR; /* ECSM Miscellaneous User-Defined Control Register */\r
+\r
+ vuint8_t ECSM_reserved4[27]; /* Reserved 27 bytes (Base+0x0028-0x0042) */\r
+\r
+ union { /* ECSM ECC Configuration (Base+0x0043) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :2;\r
+ vuint8_t ER1BR:1;\r
+ vuint8_t EF1BR:1;\r
+ vuint8_t :2;\r
+ vuint8_t ERNCR:1;\r
+ vuint8_t EFNCR:1;\r
+ } B;\r
+ } ECR;\r
+\r
+ vuint8_t ECSM_reserved5[3]; /* Reserved 3 bytes (Base+0x0044-0x0046) */\r
+\r
+ union { /* ECSM ECC Status (Base+0x0047) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :2;\r
+ vuint8_t R1BC:1;\r
+ vuint8_t F1BC:1;\r
+ vuint8_t :2;\r
+ vuint8_t RNCE:1;\r
+ vuint8_t FNCE:1;\r
+ } B;\r
+ } ESR;\r
+\r
+ vuint8_t ECSM_reserved6[2]; /* Reserved 2 bytes (Base+0x0048-0x0049) */\r
+\r
+ union { /* ECSM ECC Error Generation (Base+0x004A) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :2;\r
+ vuint16_t FRC1BI:1;\r
+ vuint16_t FR11BI:1;\r
+ vuint16_t :2;\r
+ vuint16_t FRCNCI:1;\r
+ vuint16_t FR1NCI:1;\r
+ vuint16_t :1;\r
+ vuint16_t ERRBIT:7;\r
+ } B;\r
+ } EEGR;\r
+\r
+ vuint8_t ECSM_reserved7[4]; /* Reserved 4 bytes (Base+0x004C-0x004F) */\r
+\r
+ union { /* ECSM Flash ECC Address(Base+0x0050) */\r
+ vuint32_t R;\r
+ } FEAR;\r
+\r
+ vuint8_t ECSM_reserved8[2]; /* Reserved 2 bytes (Base+0x0054-0x0055) */\r
+\r
+ union { /* ECSM Flash ECC Master Number (Base+0x0056) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :4;\r
+ vuint8_t FEMR:4;\r
+ } B;\r
+ } FEMR;\r
+\r
+ union { /* ECSM Flash ECC Attributes (Base+0x0057) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROTECTION:4;\r
+ } B;\r
+ } FEAT;\r
+\r
+ vuint8_t ECSM_reserved9[4]; /* Reserved 4 bytes (Base+0x0058-0x005B) */\r
+\r
+ union { /* ECSM Flash ECC Data (Base+0x005C) */\r
+ vuint32_t R;\r
+ } FEDR;\r
+\r
+ union { /* ECSM RAM ECC Address (Base+0x0060) */\r
+ vuint32_t R;\r
+ } REAR;\r
+\r
+ vuint8_t ECSM_reserved10[1]; /* Reserved 1 bytes (Base+0x0064) */\r
+\r
+ union { /* ECSM RAM ECC Address (Base+0x0065) */\r
+ vuint8_t R;\r
+ } RESR;\r
+\r
+ union { /* ECSM RAM ECC Master Number (Base+0x0066) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :4;\r
+ vuint8_t REMR:4;\r
+ } B;\r
+ } REMR;\r
+\r
+ union { /* ECSM RAM ECC Attributes (Base+0x0067) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROTECTION:4;\r
+ } B;\r
+ } REAT;\r
+\r
+ vuint8_t ECSM_reserved11[4]; /* Reserved 4 bytes (Base+0x0068-0x006B) */\r
+\r
+ union { /* ECSM RAM ECC Data (Base+0x006C) */\r
+ vuint32_t R;\r
+ } REDR;\r
+\r
+}; /* end of ECSM_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : RTC/API */\r
+/****************************************************************************/\r
+struct RTC_tag{\r
+\r
+ union { /* RTC Supervisor Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SUPV:1;\r
+ vuint32_t :31;\r
+ } B;\r
+ } RTCSUPV ;\r
+\r
+ union { /* RTC Control (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CNTEN:1;\r
+ vuint32_t RTCIE:1;\r
+ vuint32_t FRZEN:1;\r
+ vuint32_t ROVREN:1;\r
+ vuint32_t RTCVAL:12;\r
+ vuint32_t APIEN:1;\r
+ vuint32_t APIIE:1;\r
+ vuint32_t CLKSEL:2;\r
+ vuint32_t DIV512EN:1;\r
+ vuint32_t DIV32EN:1;\r
+ vuint32_t APIVAL:10;\r
+ } B;\r
+ } RTCC;\r
+\r
+ union { /* RTC Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :2;\r
+ vuint32_t RTCF:1;\r
+ vuint32_t :15;\r
+ vuint32_t APIF:1;\r
+ vuint32_t :2;\r
+ vuint32_t ROVRF:1;\r
+ vuint32_t :10;\r
+ } B;\r
+ } RTCS;\r
+\r
+ union { /* RTC Counter (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RTCCNT:32;\r
+ } B;\r
+ } RTCCNT;\r
+\r
+}; /* end of RTC_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : SIU Lite (tagged as SIU for compatibility) */\r
+/****************************************************************************/\r
+struct SIU_tag {\r
+\r
+ vuint8_t SIU_reserved0[4]; /* Reserved 4 Bytes (Base+0x0) */\r
+\r
+ union { /* MCU ID1 (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PARTNUM:16;\r
+ vuint32_t CSP:1;\r
+ vuint32_t PKG:5;\r
+ vuint32_t :2;\r
+ vuint32_t MAJOR_MASK:4;\r
+ vuint32_t MINOR_MASK:4;\r
+ } B;\r
+ } MIDR1;\r
+\r
+ union { /* MCU ID2 (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SF:1;\r
+ vuint32_t FLASH_SIZE_1:4;\r
+ vuint32_t FLASH_SIZE_2:4;\r
+ vuint32_t :7;\r
+ vuint32_t PARTNUM:8;\r
+ vuint32_t :3;\r
+ vuint32_t EE:1;\r
+ vuint32_t :3;\r
+ vuint32_t FR:1;\r
+ } B;\r
+ } MIDR2;\r
+\r
+ vuint8_t SIU_reserved1[8]; /* Reserved 8 Bytes (Base+(0x000C--0x0013)) */\r
+\r
+ union { /* Interrupt Status Flag (Base+0x0014)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EIF23:1;\r
+ vuint32_t EIF22:1;\r
+ vuint32_t EIF21:1;\r
+ vuint32_t EIF20:1;\r
+ vuint32_t EIF19:1;\r
+ vuint32_t EIF18:1;\r
+ vuint32_t EIF17:1;\r
+ vuint32_t EIF16:1;\r
+ vuint32_t EIF15:1;\r
+ vuint32_t EIF14:1;\r
+ vuint32_t EIF13:1;\r
+ vuint32_t EIF12:1;\r
+ vuint32_t EIF11:1;\r
+ vuint32_t EIF10:1;\r
+ vuint32_t EIF9:1;\r
+ vuint32_t EIF8:1;\r
+ vuint32_t EIF7:1;\r
+ vuint32_t EIF6:1;\r
+ vuint32_t EIF5:1;\r
+ vuint32_t EIF4:1;\r
+ vuint32_t EIF3:1;\r
+ vuint32_t EIF2:1;\r
+ vuint32_t EIF1:1;\r
+ vuint32_t EIF0:1;\r
+ } B;\r
+ } ISR;\r
+\r
+ union { /* Interrupt Request Enable (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IRE23:1;\r
+ vuint32_t IRE22:1;\r
+ vuint32_t IRE21:1;\r
+ vuint32_t IRE20:1;\r
+ vuint32_t IRE19:1;\r
+ vuint32_t IRE18:1;\r
+ vuint32_t IRE17:1;\r
+ vuint32_t IRE16:1;\r
+ vuint32_t IRE15:1;\r
+ vuint32_t IRE14:1;\r
+ vuint32_t IRE13:1;\r
+ vuint32_t IRE12:1;\r
+ vuint32_t IRE11:1;\r
+ vuint32_t IRE10:1;\r
+ vuint32_t IRE9:1;\r
+ vuint32_t IRE8:1;\r
+ vuint32_t IRE7:1;\r
+ vuint32_t IRE6:1;\r
+ vuint32_t IRE5:1;\r
+ vuint32_t IRE4:1;\r
+ vuint32_t IRE3:1;\r
+ vuint32_t IRE2:1;\r
+ vuint32_t IRE1:1;\r
+ vuint32_t IRE0:1;\r
+ } B;\r
+ } IRER;\r
+\r
+ vuint8_t SIU_reserved2[12]; /* Reserved 12 Bytes (Base+0x001C-0x0027) */\r
+\r
+ union { /* Interrupt Rising-Edge Event Enable (+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IREE23:1;\r
+ vuint32_t IREE22:1;\r
+ vuint32_t IREE21:1;\r
+ vuint32_t IREE20:1;\r
+ vuint32_t IREE19:1;\r
+ vuint32_t IREE18:1;\r
+ vuint32_t IREE17:1;\r
+ vuint32_t IREE16:1;\r
+ vuint32_t IREE15:1;\r
+ vuint32_t IREE14:1;\r
+ vuint32_t IREE13:1;\r
+ vuint32_t IREE12:1;\r
+ vuint32_t IREE11:1;\r
+ vuint32_t IREE10:1;\r
+ vuint32_t IREE9:1;\r
+ vuint32_t IREE8:1;\r
+ vuint32_t IREE7:1;\r
+ vuint32_t IREE6:1;\r
+ vuint32_t IREE5:1;\r
+ vuint32_t IREE4:1;\r
+ vuint32_t IREE3:1;\r
+ vuint32_t IREE2:1;\r
+ vuint32_t IREE1:1;\r
+ vuint32_t IREE0:1;\r
+ } B;\r
+ } IREER;\r
+\r
+ union { /* Interrupt Falling-Edge Event Enable (+0x002C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IFEE23:1;\r
+ vuint32_t IFEE22:1;\r
+ vuint32_t IFEE21:1;\r
+ vuint32_t IFEE20:1;\r
+ vuint32_t IFEE19:1;\r
+ vuint32_t IFEE18:1;\r
+ vuint32_t IFEE17:1;\r
+ vuint32_t IFEE16:1;\r
+ vuint32_t IFEE15:1;\r
+ vuint32_t IFEE14:1;\r
+ vuint32_t IFEE13:1;\r
+ vuint32_t IFEE12:1;\r
+ vuint32_t IFEE11:1;\r
+ vuint32_t IFEE10:1;\r
+ vuint32_t IFEE9:1;\r
+ vuint32_t IFEE8:1;\r
+ vuint32_t IFEE7:1;\r
+ vuint32_t IFEE6:1;\r
+ vuint32_t IFEE5:1;\r
+ vuint32_t IFEE4:1;\r
+ vuint32_t IFEE3:1;\r
+ vuint32_t IFEE2:1;\r
+ vuint32_t IFEE1:1;\r
+ vuint32_t IFEE0:1;\r
+ } B;\r
+ } IFEER;\r
+\r
+ union { /* Interrupt Filter Enable (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t IFE23:1;\r
+ vuint32_t IFE22:1;\r
+ vuint32_t IFE21:1;\r
+ vuint32_t IFE20:1;\r
+ vuint32_t IFE19:1;\r
+ vuint32_t IFE18:1;\r
+ vuint32_t IFE17:1;\r
+ vuint32_t IFE16:1;\r
+ vuint32_t IFE15:1;\r
+ vuint32_t IFE14:1;\r
+ vuint32_t IFE13:1;\r
+ vuint32_t IFE12:1;\r
+ vuint32_t IFE11:1;\r
+ vuint32_t IFE10:1;\r
+ vuint32_t IFE9:1;\r
+ vuint32_t IFE8:1;\r
+ vuint32_t IFE7:1;\r
+ vuint32_t IFE6:1;\r
+ vuint32_t IFE5:1;\r
+ vuint32_t IFE4:1;\r
+ vuint32_t IFE3:1;\r
+ vuint32_t IFE2:1;\r
+ vuint32_t IFE1:1;\r
+ vuint32_t IFE0:1;\r
+ } B;\r
+ } IFER;\r
+\r
+ vuint8_t SIU_reserved3[12]; /* Reserved 12 Bytes (Base+0x0034-0x003F) */\r
+\r
+ union { /* Pad Configuration 0..148 (Base+0x0040-0x0168)*/\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:1;\r
+ vuint16_t SMC:1;\r
+ vuint16_t APC:1;\r
+ vuint16_t:1;\r
+ vuint16_t PA:2;\r
+ vuint16_t OBE:1;\r
+ vuint16_t IBE:1;\r
+ vuint16_t:2;\r
+ vuint16_t ODE:1;\r
+ vuint16_t:2;\r
+ vuint16_t SRC:1;\r
+ vuint16_t WPE:1;\r
+ vuint16_t WPS:1;\r
+ } B;\r
+ } PCR[149];\r
+\r
+ vuint8_t SIU_reserved4[918]; /*Reserved 918 Bytes (Base+0x016A-0x04FF) */\r
+\r
+ union { /* Pad Selection for Mux Input (0x0500-0x53C) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :4;\r
+ vuint8_t PADSEL:4;\r
+ } B;\r
+ } PSMI[64];\r
+\r
+ vuint8_t SIU_reserved5[192]; /*Reserved 192 Bytes (Base+0x0540-0x05FF) */\r
+\r
+ union { /* GPIO Pad Data Output (Base+0x0600-0x06A0) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :7;\r
+ vuint8_t PDO:1;\r
+ } B;\r
+ } GPDO[152];\r
+\r
+ vuint8_t SIU_reserved6[348]; /*Reserved 348 Bytes (Base+0x06A4-0x07FF) */\r
+\r
+ union { /* GPIO Pad Data Input (Base+0x0800-0x08A0) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :7;\r
+ vuint8_t PDI:1;\r
+ } B;\r
+ } GPDI[152];\r
+\r
+ vuint8_t SIU_reserved7[860]; /*Reserved 860 Bytes (Base+0x08A4-0x0BFF) */\r
+\r
+ union { /* Parallel GPIO Pad Data Out 0-4 (0x0C00-0xC010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PPD0:32;\r
+ } B;\r
+ } PGPDO[5];\r
+\r
+ vuint8_t SIU_reserved8[44]; /* Reserved 44 Bytes (Base+0x0C14-0x0C3F) */\r
+\r
+ union { /* Parallel GPIO Pad Data In 0-4 (0x0C40-0x0C50) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PPDI:32;\r
+ } B;\r
+ } PGPDI[5];\r
+\r
+ vuint8_t SIU_reserved9[44]; /* Reserved 44 Bytes (Base+0x0C54-0x0C7F) */\r
+\r
+ union { /* Masked Parallel GPIO Pad Data Out 0-9 (0x0C80-0x0CA4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MASK:16;\r
+ vuint32_t MPPDO:16;\r
+ } B;\r
+ } MPGPDO[9];\r
+\r
+ vuint8_t SIU_reserved10[856]; /*Reserved 844 Bytes (Base+0x0CA8-0x0FFF)*/\r
+\r
+ union { /* Interrupt Filter Max Counter 0..23 (+0x1000-0x105C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t MAXCNT:4;\r
+ } B;\r
+ } IFMC[24];\r
+\r
+ vuint8_t SIU_reserved11[32]; /* Reserved 32 Bytes (Base+0x1060-0x107F)*/\r
+\r
+ union { /* Interrupt Filter Clock Prescaler (Base+0x1080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t IFCP:4;\r
+ } B;\r
+ } IFCPR;\r
+\r
+ vuint8_t SIU_reserved12[12156]; /* Reserved 12156 Bytes (+0x1084-0x3FFF)*/\r
+\r
+}; /* end of SIU_tag */\r
+/****************************************************************************/\r
+/* MODULE : SSCM */\r
+/****************************************************************************/\r
+struct SSCM_tag{\r
+\r
+ union { /* Status (Base+0x0000) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:4;\r
+ vuint16_t NXEN:1;\r
+ vuint16_t:3;\r
+ vuint16_t BMODE:3;\r
+ vuint16_t :1;\r
+ vuint16_t ABD:1;\r
+ vuint16_t:3;\r
+ } B;\r
+ } STATUS;\r
+\r
+ union { /* System Memory Configuration (Base+0x002) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t PRSZ:5;\r
+ vuint16_t PVLB:1;\r
+ vuint16_t DTSZ:4;\r
+ vuint16_t DVLD:1;\r
+ } B;\r
+ } MEMCONFIG;\r
+\r
+ vuint8_t SSCM_reserved0[2]; /* Reserved 2 bytes (Base+0x0004-0x0005) */\r
+\r
+ union { /* Error Configuration (Base+0x0006) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :14;\r
+ vuint16_t PAE:1;\r
+ vuint16_t RAE:1;\r
+ } B;\r
+ } ERROR;\r
+\r
+ union { /* Debug Status Port (Base+0x0008) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :13;\r
+ vuint16_t DEBUG_MODE:3;\r
+ } B;\r
+ } DEBUGPORT;\r
+\r
+ vuint8_t SSCM_reserved1[2]; /* Reserved 2 bytes (Base+0x000A-0x000B) */\r
+\r
+ union { /* Password Comparison High Word (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PWD_HI:32;\r
+ } B;\r
+ } PWCMPH;\r
+\r
+ union { /* Password Comparison Low Word (Base+0x0010)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PWD_LO:32;\r
+ } B;\r
+ } PWCMPL;\r
+\r
+}; /* end of SSCM_tag */\r
+/****************************************************************************/\r
+/* MODULE : STM */\r
+/****************************************************************************/\r
+ struct STM_CHANNEL_tag{\r
+\r
+ union { /* STM Channel Control 0..3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR;\r
+\r
+ union { /* STM Channel Interrupt 0..3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR;\r
+\r
+ union { /* STM Channel Compare 0..3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CMP:32;\r
+ } B;\r
+ } CMP;\r
+\r
+ vuint8_t STM_CHANNEL_reserved0[4]; /* Reserved 4 bytes between ch reg's */\r
+\r
+ }; /* end of STM_CHANNEL_tag */\r
+\r
+\r
+struct STM_tag{\r
+\r
+ union { /* STM Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CPS:8;\r
+ vuint32_t :6;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* STM Count (Base+0x0004) */\r
+ vuint32_t R;\r
+ } CNT;\r
+\r
+ vuint8_t STM_reserved1[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */\r
+\r
+ struct STM_CHANNEL_tag CH[4]; /*STM Channels 0..3 (Base+0x0010-0x0048) */\r
+\r
+}; /* end of STM_tag */\r
+/****************************************************************************/\r
+/* MODULE : SWT */\r
+/****************************************************************************/\r
+struct SWT_tag{\r
+\r
+ union { /* SWT Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MAP0:1;\r
+ vuint32_t MAP1:1;\r
+ vuint32_t MAP2:1;\r
+ vuint32_t MAP3:1;\r
+ vuint32_t MAP4:1;\r
+ vuint32_t MAP5:1;\r
+ vuint32_t MAP6:1;\r
+ vuint32_t MAP7:1;\r
+ vuint32_t :14;\r
+ vuint32_t KEY:1;\r
+ vuint32_t RIA:1;\r
+ vuint32_t WND:1;\r
+ vuint32_t ITR:1;\r
+ vuint32_t HLK:1;\r
+ vuint32_t SLK:1;\r
+ vuint32_t CSL:1;\r
+ vuint32_t STP:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t WEN:1;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* SWT Interrupt (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } IR;\r
+\r
+ union { /* SWT Time-Out (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t WTO:32;\r
+ } B;\r
+ } TO;\r
+\r
+ union { /* SWT Window (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t WST:32;\r
+ } B;\r
+ } WN;\r
+\r
+ union { /* SWT Service (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t WSC:16;\r
+ } B;\r
+ } SR;\r
+\r
+ union { /* SWT Counter Output (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CNT:32;\r
+ } B;\r
+ } CO;\r
+\r
+}; /* end of SWT_tag */ \r
+/****************************************************************************/\r
+/* MODULE : WKUP */\r
+/****************************************************************************/\r
+struct WKUP_tag{\r
+\r
+ union { /* NMI Status Flag (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NIF0:1; \r
+ vuint32_t NOVF0:1;\r
+ vuint32_t :30;\r
+ } B;\r
+ } NSR;\r
+\r
+ vuint8_t WKUP_reserved0[4]; /* Reserved 4 Bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* NMI Configuration (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NLOCK0:1;\r
+ vuint32_t NDSS0:2;\r
+ vuint32_t NWRE0:1;\r
+ vuint32_t :1;\r
+ vuint32_t NREE0:1;\r
+ vuint32_t NFEE0:1;\r
+ vuint32_t NFE0:1;\r
+ vuint32_t :24;\r
+ } B;\r
+ } NCR;\r
+\r
+ vuint8_t WKUP_reserved1[8]; /* Reserved 8 Bytes (Base+0x000C-0x0013) */\r
+\r
+ union { /* Wakeup/Interrup status flag (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t EIF:29;\r
+ } B;\r
+ } WISR;\r
+\r
+ union { /* Interrupt Request Enable (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t EIRE:29; \r
+ } B;\r
+ } IRER;\r
+\r
+ union { /* Wakeup Request Enable (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t WRE:29;\r
+ } B;\r
+ } WRER;\r
+\r
+ vuint8_t WKUP_reserved2[8]; /* Reserved 8 Bytes (Base+0x0020-0x0027) */\r
+\r
+ union { /* Wakeup/Interrupt Rising-Edge (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IREE:29;\r
+ } B;\r
+ } WIREER;\r
+\r
+ union { /* Wakeup/Interrupt Falling-Edge (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IFEE:29;\r
+ } B;\r
+ } WIFEER;\r
+\r
+ union { /* Wakeup/Interrupt Filter Enable (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IFE:29;\r
+ } B;\r
+ } WIFER;\r
+\r
+ union { /* Wakeup/Interrupt Pullup Enable (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t IPUE:29;\r
+ } B;\r
+ } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */\r
+\r
+ vuint8_t WKUP_reserved3[16328]; /* Reserved 16328 (Base+0x0038-0x3FFF) */\r
+\r
+}; /* end of WKUP_tag */\r
+/****************************************************************************/\r
+/* MODULE : LINFLEX */\r
+/****************************************************************************/\r
+struct LINFLEX_tag {\r
+\r
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CCD:1;\r
+ vuint32_t CFD:1;\r
+ vuint32_t LASE:1;\r
+ vuint32_t AWUM:1;\r
+ vuint32_t MBL:4;\r
+ vuint32_t BF:1;\r
+ vuint32_t SFTM:1;\r
+ vuint32_t LBKM:1;\r
+ vuint32_t MME:1;\r
+ vuint32_t SBDT:1;\r
+ vuint32_t RBLM:1;\r
+ vuint32_t SLEEP:1;\r
+ vuint32_t INIT:1;\r
+ } B;\r
+ } LINCR1;\r
+\r
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZIE:1;\r
+ vuint32_t OCIE:1;\r
+ vuint32_t BEIE:1;\r
+ vuint32_t CEIE:1;\r
+ vuint32_t HEIE:1;\r
+ vuint32_t :2;\r
+ vuint32_t FEIE:1;\r
+ vuint32_t BOIE:1;\r
+ vuint32_t LSIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t DBFIE:1;\r
+ vuint32_t DBEIE:1;\r
+ vuint32_t DRIE:1;\r
+ vuint32_t DTIE:1;\r
+ vuint32_t HRIE:1;\r
+ } B;\r
+ } LINIER;\r
+\r
+ union { /* LINFLEX LIN Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t LINS:4;\r
+ vuint32_t:2;\r
+ vuint32_t RMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t RBSY:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t DBFF:1;\r
+ vuint32_t DBEF:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t HRF:1;\r
+ } B;\r
+ } LINSR;\r
+\r
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t BEF:1;\r
+ vuint32_t CEF:1;\r
+ vuint32_t SFEF:1;\r
+ vuint32_t BDEF:1;\r
+ vuint32_t IDPEF:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t:6;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } LINESR;\r
+\r
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:1;\r
+ vuint32_t TDFL:2;\r
+ vuint32_t:1;\r
+ vuint32_t RDFL:2;\r
+ vuint32_t:4;\r
+ vuint32_t RXEN:1;\r
+ vuint32_t TXEN:1;\r
+ vuint32_t OP:1;\r
+ vuint32_t PCE:1;\r
+ vuint32_t WL:1;\r
+ vuint32_t UART:1;\r
+ } B;\r
+ } UARTCR;\r
+\r
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/\r
+ vuint32_t RMB:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t:2;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } UARTSR;\r
+\r
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:5;\r
+ vuint32_t LTOM:1;\r
+ vuint32_t IOT:1;\r
+ vuint32_t TOCE:1;\r
+ vuint32_t CNT:8;\r
+ } B;\r
+ } LINTCSR;\r
+\r
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t OC2:8;\r
+ vuint32_t OC1:8;\r
+ } B;\r
+ } LINOCR;\r
+\r
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t RTO:4;\r
+ vuint32_t:1;\r
+ vuint32_t HTO:7;\r
+ } B;\r
+ } LINTOCR;\r
+\r
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIV_F:4;\r
+ } B;\r
+ } LINFBRR;\r
+\r
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:19;\r
+ vuint32_t DIV_M:13;\r
+ } B;\r
+ } LINIBRR;\r
+\r
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CF:8;\r
+ } B;\r
+ } LINCFR;\r
+\r
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:17;\r
+ vuint32_t IOBE:1;\r
+ vuint32_t IOPE:1;\r
+ vuint32_t WURQ:1;\r
+ vuint32_t DDRQ:1;\r
+ vuint32_t DTRQ:1;\r
+ vuint32_t ABRQ:1;\r
+ vuint32_t HTRQ:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LINCR2;\r
+\r
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } BIDR;\r
+\r
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA3:8;\r
+ vuint32_t DATA2:8;\r
+ vuint32_t DATA1:8;\r
+ vuint32_t DATA0:8;\r
+ } B;\r
+ } BDRL;\r
+\r
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA7:8;\r
+ vuint32_t DATA6:8;\r
+ vuint32_t DATA5:8;\r
+ vuint32_t DATA4:8;\r
+ } B;\r
+ } BDRM;\r
+\r
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t FACT:8;\r
+ } B;\r
+ } IFER;\r
+\r
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t IFMI:4;\r
+ } B;\r
+ } IFMI;\r
+\r
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t IFM:5;\r
+ } B;\r
+ } IFMR;\r
+\r
+ union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t:3; /* for LINflexD no reseve here*/\r
+ vuint32_t DFL:3; /* Linflex D - this field is 6 bits (0 and 1), Linflex - this field is 3 bits (2-9 B1.5M) (2-7 B1M) */ \r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } IFCR[16];\r
+\r
+ \r
+}; /* end of LINFLEX_tag */\r
+\r
+\r
+/****************************************************************************/\r
+/* MODULE : LINFLEXD0 */\r
+/****************************************************************************/\r
+struct LINFLEXD0_tag {\r
+\r
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CCD:1;\r
+ vuint32_t CFD:1;\r
+ vuint32_t LASE:1;\r
+ vuint32_t AWUM:1;\r
+ vuint32_t MBL:4;\r
+ vuint32_t BF:1;\r
+ vuint32_t SFTM:1;\r
+ vuint32_t LBKM:1;\r
+ vuint32_t MME:1;\r
+ vuint32_t SBDT:1;\r
+ vuint32_t RBLM:1;\r
+ vuint32_t SLEEP:1;\r
+ vuint32_t INIT:1;\r
+ } B;\r
+ } LINCR1;\r
+\r
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZIE:1;\r
+ vuint32_t OCIE:1;\r
+ vuint32_t BEIE:1;\r
+ vuint32_t CEIE:1;\r
+ vuint32_t HEIE:1;\r
+ vuint32_t :2;\r
+ vuint32_t FEIE:1;\r
+ vuint32_t BOIE:1;\r
+ vuint32_t LSIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t DBFIE:1;\r
+ vuint32_t DBEIE:1;\r
+ vuint32_t DRIE:1;\r
+ vuint32_t DTIE:1;\r
+ vuint32_t HRIE:1;\r
+ } B;\r
+ } LINIER;\r
+\r
+ union { /* LINFLEX LIN Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t LINS:4;\r
+ vuint32_t:2;\r
+ vuint32_t RMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t RBSY:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t DBFF:1;\r
+ vuint32_t DBEF:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t HRF:1;\r
+ } B;\r
+ } LINSR;\r
+\r
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t BEF:1;\r
+ vuint32_t CEF:1;\r
+ vuint32_t SFEF:1;\r
+ vuint32_t BDEF:1;\r
+ vuint32_t IDPEF:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t:6;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } LINESR;\r
+\r
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:1;\r
+ vuint32_t TDFL:2;\r
+ vuint32_t:1;\r
+ vuint32_t RDFL:2;\r
+ vuint32_t:4;\r
+ vuint32_t RXEN:1;\r
+ vuint32_t TXEN:1;\r
+ vuint32_t OP:1;\r
+ vuint32_t PCE:1;\r
+ vuint32_t WL:1;\r
+ vuint32_t UART:1;\r
+ } B;\r
+ } UARTCR;\r
+\r
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/\r
+ vuint32_t RMB:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t:2;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } UARTSR;\r
+\r
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:5;\r
+ vuint32_t LTOM:1;\r
+ vuint32_t IOT:1;\r
+ vuint32_t TOCE:1;\r
+ vuint32_t CNT:8;\r
+ } B;\r
+ } LINTCSR;\r
+\r
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t OC2:8;\r
+ vuint32_t OC1:8;\r
+ } B;\r
+ } LINOCR;\r
+\r
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t RTO:4;\r
+ vuint32_t:1;\r
+ vuint32_t HTO:7;\r
+ } B;\r
+ } LINTOCR;\r
+\r
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIV_F:4;\r
+ } B;\r
+ } LINFBRR;\r
+\r
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:19;\r
+ vuint32_t DIV_M:13;\r
+ } B;\r
+ } LINIBRR;\r
+\r
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CF:8;\r
+ } B;\r
+ } LINCFR;\r
+\r
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:17;\r
+ vuint32_t IOBE:1;\r
+ vuint32_t IOPE:1;\r
+ vuint32_t WURQ:1;\r
+ vuint32_t DDRQ:1;\r
+ vuint32_t DTRQ:1;\r
+ vuint32_t ABRQ:1;\r
+ vuint32_t HTRQ:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LINCR2;\r
+\r
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } BIDR;\r
+\r
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA3:8;\r
+ vuint32_t DATA2:8;\r
+ vuint32_t DATA1:8;\r
+ vuint32_t DATA0:8;\r
+ } B;\r
+ } BDRL;\r
+\r
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA7:8;\r
+ vuint32_t DATA6:8;\r
+ vuint32_t DATA5:8;\r
+ vuint32_t DATA4:8;\r
+ } B;\r
+ } BDRM;\r
+\r
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t FACT:8;\r
+ } B;\r
+ } IFER;\r
+\r
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t IFMI:4;\r
+ } B;\r
+ } IFMI;\r
+\r
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t IFM:5;\r
+ } B;\r
+ } IFMR;\r
+\r
+ union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } IFCR[16];\r
+\r
+ union { /* LINFLEX Global Counter (+0x008C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t TDFBM:1;\r
+ vuint32_t RDFBM:1;\r
+ vuint32_t TDLIS:1;\r
+ vuint32_t RDLIS:1;\r
+ vuint32_t STOP:1;\r
+ vuint32_t SR:1;\r
+ } B;\r
+ } GCR;\r
+\r
+ union { /* LINFLEX UART preset timeout (+0x0090) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t PTO:12;\r
+ } B;\r
+ } UARTPTO;\r
+\r
+ union { /* LINFLEX UART current timeout (+0x0094) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t CTO:12;\r
+ } B;\r
+ } UARTCTO;\r
+\r
+ union { /* LINFLEX DMA Tx Enable (+0x0098) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DTE15:1;\r
+ vuint32_t DTE14:1;\r
+ vuint32_t DTE13:1;\r
+ vuint32_t DTE12:1;\r
+ vuint32_t DTE11:1;\r
+ vuint32_t DTE10:1;\r
+ vuint32_t DTE9:1;\r
+ vuint32_t DTE8:1;\r
+ vuint32_t DTE7:1;\r
+ vuint32_t DTE6:1;\r
+ vuint32_t DTE5:1;\r
+ vuint32_t DTE4:1;\r
+ vuint32_t DTE3:1;\r
+ vuint32_t DTE2:1;\r
+ vuint32_t DTE1:1;\r
+ vuint32_t DTE0:1;\r
+ } B;\r
+ } DMATXE;\r
+\r
+ union { /* LINFLEX DMA RX Enable (+0x009C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DRE15:1;\r
+ vuint32_t DRE14:1;\r
+ vuint32_t DRE13:1;\r
+ vuint32_t DRE12:1;\r
+ vuint32_t DRE11:1;\r
+ vuint32_t DRE10:1;\r
+ vuint32_t DRE9:1;\r
+ vuint32_t DRE8:1;\r
+ vuint32_t DRE7:1;\r
+ vuint32_t DRE6:1;\r
+ vuint32_t DRE5:1;\r
+ vuint32_t DRE4:1;\r
+ vuint32_t DRE3:1;\r
+ vuint32_t DRE2:1;\r
+ vuint32_t DRE1:1;\r
+ vuint32_t DRE0:1;\r
+ } B;\r
+ } DMARXE;\r
+}; /* end of LINFLEXD0_tag */\r
+/****************************************************************************/\r
+/* MODULE : LINFLEXD1 */\r
+/****************************************************************************/\r
+struct LINFLEXD1_tag {\r
+\r
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t CCD:1;\r
+ vuint32_t CFD:1;\r
+ vuint32_t LASE:1;\r
+ vuint32_t AWUM:1;\r
+ vuint32_t MBL:4;\r
+ vuint32_t BF:1;\r
+ vuint32_t SFTM:1;\r
+ vuint32_t LBKM:1;\r
+ vuint32_t MME:1;\r
+ vuint32_t SBDT:1;\r
+ vuint32_t RBLM:1;\r
+ vuint32_t SLEEP:1;\r
+ vuint32_t INIT:1;\r
+ } B;\r
+ } LINCR1;\r
+\r
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZIE:1;\r
+ vuint32_t OCIE:1;\r
+ vuint32_t BEIE:1;\r
+ vuint32_t CEIE:1;\r
+ vuint32_t HEIE:1;\r
+ vuint32_t :2;\r
+ vuint32_t FEIE:1;\r
+ vuint32_t BOIE:1;\r
+ vuint32_t LSIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t DBFIE:1;\r
+ vuint32_t DBEIE:1;\r
+ vuint32_t DRIE:1;\r
+ vuint32_t DTIE:1;\r
+ vuint32_t HRIE:1;\r
+ } B;\r
+ } LINIER;\r
+\r
+ union { /* LINFLEX LIN Status (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t LINS:4;\r
+ vuint32_t:2;\r
+ vuint32_t RMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t RBSY:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t DBFF:1;\r
+ vuint32_t DBEF:1;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t HRF:1;\r
+ } B;\r
+ } LINSR;\r
+\r
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t BEF:1;\r
+ vuint32_t CEF:1;\r
+ vuint32_t SFEF:1;\r
+ vuint32_t BDEF:1;\r
+ vuint32_t IDPEF:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t:6;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } LINESR;\r
+\r
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:1;\r
+ vuint32_t TDFL:2;\r
+ vuint32_t:1;\r
+ vuint32_t RDFL:2;\r
+ vuint32_t:4;\r
+ vuint32_t RXEN:1;\r
+ vuint32_t TXEN:1;\r
+ vuint32_t OP:1;\r
+ vuint32_t PCE:1;\r
+ vuint32_t WL:1;\r
+ vuint32_t UART:1;\r
+ } B;\r
+ } UARTCR;\r
+\r
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t SZF:1;\r
+ vuint32_t OCF:1;\r
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/\r
+ vuint32_t RMB:1;\r
+ vuint32_t FEF:1;\r
+ vuint32_t BOF:1;\r
+ vuint32_t RPS:1;\r
+ vuint32_t WUF:1;\r
+ vuint32_t:2;\r
+ vuint32_t DRF:1;\r
+ vuint32_t DTF:1;\r
+ vuint32_t NF:1;\r
+ } B;\r
+ } UARTSR;\r
+\r
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t:5;\r
+ vuint32_t LTOM:1;\r
+ vuint32_t IOT:1;\r
+ vuint32_t TOCE:1;\r
+ vuint32_t CNT:8;\r
+ } B;\r
+ } LINTCSR;\r
+\r
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t OC2:8;\r
+ vuint32_t OC1:8;\r
+ } B;\r
+ } LINOCR;\r
+\r
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t RTO:4;\r
+ vuint32_t:1;\r
+ vuint32_t HTO:7;\r
+ } B;\r
+ } LINTOCR;\r
+\r
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIV_F:4;\r
+ } B;\r
+ } LINFBRR;\r
+\r
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:19;\r
+ vuint32_t DIV_M:13;\r
+ } B;\r
+ } LINIBRR;\r
+\r
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t CF:8;\r
+ } B;\r
+ } LINCFR;\r
+\r
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:17;\r
+ vuint32_t IOBE:1;\r
+ vuint32_t IOPE:1;\r
+ vuint32_t WURQ:1;\r
+ vuint32_t DDRQ:1;\r
+ vuint32_t DTRQ:1;\r
+ vuint32_t ABRQ:1;\r
+ vuint32_t HTRQ:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LINCR2;\r
+\r
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DFL:6;\r
+ vuint32_t DIR:1;\r
+ vuint32_t CCS:1;\r
+ vuint32_t:2;\r
+ vuint32_t ID:6;\r
+ } B;\r
+ } BIDR;\r
+\r
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA3:8;\r
+ vuint32_t DATA2:8;\r
+ vuint32_t DATA1:8;\r
+ vuint32_t DATA0:8;\r
+ } B;\r
+ } BDRL;\r
+\r
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATA7:8;\r
+ vuint32_t DATA6:8;\r
+ vuint32_t DATA5:8;\r
+ vuint32_t DATA4:8;\r
+ } B;\r
+ } BDRM;\r
+\r
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t FACT:8;\r
+ } B;\r
+ } IFER;\r
+\r
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t IFMI:4;\r
+ } B;\r
+ } IFMI;\r
+\r
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t IFM:5;\r
+ } B;\r
+ } IFMR;\r
+\r
+/* No IFCR registers on LinFlexD_1 */\r
+\r
+ union { /* LINFLEX Global Counter (+0x004C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t TDFBM:1;\r
+ vuint32_t RDFBM:1;\r
+ vuint32_t TDLIS:1;\r
+ vuint32_t RDLIS:1;\r
+ vuint32_t STOP:1;\r
+ vuint32_t SR:1;\r
+ } B;\r
+ } GCR;\r
+\r
+ union { /* LINFLEX UART preset timeout (+0x0050) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t PTO:12;\r
+ } B;\r
+ } UARTPTO;\r
+\r
+ union { /* LINFLEX UART current timeout (+0x0054) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t CTO:12;\r
+ } B;\r
+ } UARTCTO;\r
+\r
+ union { /* LINFLEX DMA Tx Enable (+0x0058) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DTE15:1;\r
+ vuint32_t DTE14:1;\r
+ vuint32_t DTE13:1;\r
+ vuint32_t DTE12:1;\r
+ vuint32_t DTE11:1;\r
+ vuint32_t DTE10:1;\r
+ vuint32_t DTE9:1;\r
+ vuint32_t DTE8:1;\r
+ vuint32_t DTE7:1;\r
+ vuint32_t DTE6:1;\r
+ vuint32_t DTE5:1;\r
+ vuint32_t DTE4:1;\r
+ vuint32_t DTE3:1;\r
+ vuint32_t DTE2:1;\r
+ vuint32_t DTE1:1;\r
+ vuint32_t DTE0:1;\r
+ } B;\r
+ } DMATXE;\r
+\r
+ union { /* LINFLEX DMA RX Enable (+0x005C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DRE15:1;\r
+ vuint32_t DRE14:1;\r
+ vuint32_t DRE13:1;\r
+ vuint32_t DRE12:1;\r
+ vuint32_t DRE11:1;\r
+ vuint32_t DRE10:1;\r
+ vuint32_t DRE9:1;\r
+ vuint32_t DRE8:1;\r
+ vuint32_t DRE7:1;\r
+ vuint32_t DRE6:1;\r
+ vuint32_t DRE5:1;\r
+ vuint32_t DRE4:1;\r
+ vuint32_t DRE3:1;\r
+ vuint32_t DRE2:1;\r
+ vuint32_t DRE1:1;\r
+ vuint32_t DRE0:1;\r
+ } B;\r
+ } DMARXE;\r
+}; /* end of LINFLEXD1_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : ME */\r
+/****************************************************************************/\r
+struct ME_tag{\r
+\r
+ union { /* Global Status (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t S_CURRENTMODE:4;\r
+ vuint32_t S_MTRANS:1;\r
+ vuint32_t S_DC:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_MVR:1;\r
+ vuint32_t S_DFLA:2;\r
+ vuint32_t S_CFLA:2;\r
+ vuint32_t :9;\r
+ vuint32_t S_FMPLL:1;\r
+ vuint32_t S_FXOSC:1;\r
+ vuint32_t S_FIRC:1;\r
+ vuint32_t S_SYSCLK:4;\r
+ } B;\r
+ } GS;\r
+\r
+ union { /* Mode Control (Base+0x004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TARGET_MODE:4;\r
+ vuint32_t :12;\r
+ vuint32_t KEY:16;\r
+ } B;\r
+ } MCTL;\r
+\r
+ union { /* Mode Enable (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t :2;\r
+ vuint32_t STANDBY0:1;\r
+ vuint32_t :2;\r
+ vuint32_t STOP0:1;\r
+ vuint32_t :1;\r
+ vuint32_t HALT0:1;\r
+ vuint32_t RUN3:1;\r
+ vuint32_t RUN2:1;\r
+ vuint32_t RUN1:1;\r
+ vuint32_t RUN0:1;\r
+ vuint32_t DRUN:1;\r
+ vuint32_t SAFE:1;\r
+ vuint32_t TEST:1;\r
+ vuint32_t RESET:1;\r
+ } B;\r
+ } MER;\r
+\r
+ union { /* Interrupt Status (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t I_ICONF:1;\r
+ vuint32_t I_IMODE:1;\r
+ vuint32_t I_SAFE:1;\r
+ vuint32_t I_MTC:1;\r
+ } B;\r
+ } IS;\r
+\r
+ union { /* Interrupt Mask (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t M_ICONF:1;\r
+ vuint32_t M_IMODE:1;\r
+ vuint32_t M_SAFE:1;\r
+ vuint32_t M_MTC:1;\r
+ } B;\r
+ } IM;\r
+\r
+ union { /* Invalid Mode Transition Status (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :27;\r
+ vuint32_t S_MTI:1;\r
+ vuint32_t S_MRI:1;\r
+ vuint32_t S_DMA:1;\r
+ vuint32_t S_NMA:1;\r
+ vuint32_t S_SEA:1;\r
+ } B;\r
+ } IMTS;\r
+\r
+ union { /* Debug Mode Transition Status (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t MPH_BUSY:1;\r
+ vuint32_t :2;\r
+ vuint32_t PMC_PROG:1;\r
+ vuint32_t CORE_DBG:1;\r
+ vuint32_t :2;\r
+ vuint32_t SMR:1;\r
+ vuint32_t :1;\r
+ vuint32_t FMPLL_SC:1;\r
+ vuint32_t FXOSC_SC:1;\r
+ vuint32_t FIRC_SC:1;\r
+ vuint32_t :1;\r
+ vuint32_t SYSCLK_SW:1;\r
+ vuint32_t DFLASH_SC:1;\r
+ vuint32_t CFLASH_SC:1;\r
+ vuint32_t CDP_PRPH_0_143:1;\r
+ vuint32_t :3;\r
+ vuint32_t CDP_PRPH_96_127:1;\r
+ vuint32_t CDP_PRPH_64_95:1;\r
+ vuint32_t CDP_PRPH_32_63:1;\r
+ vuint32_t CDP_PRPH_0_31:1;\r
+ } B;\r
+ } DMTS;\r
+\r
+ vuint8_t ME_reserved0[4]; /* reserved 4 bytes (Base+0x001C-0x001F) */\r
+\r
+ union { /* Reset Mode Configuration (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } RESET;\r
+\r
+ union { /* Test Mode Configuration (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } TEST;\r
+\r
+ union { /* Safe Mode Configuration (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } SAFE;\r
+\r
+ union { /* DRUN Mode Configuration (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSCON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } DRUN;\r
+\r
+ union { /* RUN 0->4 Mode Configuration (+0x0030-0x003C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } RUN[4];\r
+\r
+ union { /* HALT0 Mode Configuration (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } HALT0;\r
+\r
+ vuint8_t ME_reserved1[4]; /* reserved 4 bytes (Base+0x0044-0x0047) */\r
+\r
+ union { /* STOP0 Mode Configuration (Base+0x0048) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } STOP0;\r
+\r
+ vuint8_t ME_reserved2[8]; /* reserved 8 bytes (Base+0x004C-0x0053) */\r
+\r
+ union { /* STANDBY0 Mode Configuration (Base+0x0054) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t PDO:1;\r
+ vuint32_t :2;\r
+ vuint32_t MVRON:1;\r
+ vuint32_t DFLAON:2;\r
+ vuint32_t CFLAON:2;\r
+ vuint32_t :9;\r
+ vuint32_t FMPLLON:1;\r
+ vuint32_t FXOSC0ON:1;\r
+ vuint32_t FIRCON:1;\r
+ vuint32_t SYSCLK:4;\r
+ } B;\r
+ } STANDBY0;\r
+\r
+ vuint8_t ME_reserved3[8]; /* reserved 8 bytes (Base+0x0058-0x005F) */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct { /* Peripheral Status 0 (Base+0x0060) */\r
+ vuint32_t :8;\r
+ vuint32_t S_DMA_CH_MUX:1;\r
+ vuint32_t :1;\r
+ vuint32_t S_FLEXCAN5:1;\r
+ vuint32_t S_FLEXCAN4:1;\r
+ vuint32_t S_FLEXCAN3:1;\r
+ vuint32_t S_FLEXCAN2:1;\r
+ vuint32_t S_FLEXCAN1:1;\r
+ vuint32_t S_FLEXCAN0:1;\r
+ vuint32_t :2;\r
+ vuint32_t :1; /* S_LINFLEX9:1; // not present on B1M */\r
+ vuint32_t :1; /* S_LINFLEX8:1; // not present on B1M */\r
+ vuint32_t :2;\r
+ vuint32_t S_DSPI5:1;\r
+ vuint32_t S_DSPI4:1;\r
+ vuint32_t S_DSPI3:1;\r
+ vuint32_t S_DSPI2:1;\r
+ vuint32_t S_DSPI1:1;\r
+ vuint32_t S_DSPI0:1;\r
+ vuint32_t :4;\r
+ } B;\r
+ } PS0;\r
+\r
+ union { /* Peripheral Status 1 (Base+0x0064)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t S_CANSAMPLER:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_CTUL:1;\r
+ vuint32_t :1;\r
+ vuint32_t S_LINFLEX7:1;\r
+ vuint32_t S_LINFLEX6:1;\r
+ vuint32_t S_LINFLEX5:1;\r
+ vuint32_t S_LINFLEX4:1;\r
+ vuint32_t S_LINFLEX3:1;\r
+ vuint32_t S_LINFLEX2:1;\r
+ vuint32_t S_LINFLEX1:1;\r
+ vuint32_t S_LINFLEX0:1;\r
+ vuint32_t :3;\r
+ vuint32_t S_I2C0:1;\r
+ vuint32_t :10;\r
+ vuint32_t S_ADC1:1;\r
+ vuint32_t S_ADC0:1;\r
+ } B;\r
+ } PS1;\r
+\r
+ union { /* Peripheral Status 2 (Base+0x0068) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t S_PIT_RTI:1;\r
+ vuint32_t S_RTC_API:1;\r
+ vuint32_t :16;\r
+ vuint32_t S_EMIOS1:1;\r
+ vuint32_t S_EMIOS0:1;\r
+ vuint32_t :2;\r
+ vuint32_t S_WKPU:1; \r
+ vuint32_t S_SIUL:1;\r
+ vuint32_t :4;\r
+ } B;\r
+ } PS2;\r
+\r
+ union { /* Peripheral Status 3 (Base+0x006C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :23;\r
+ vuint32_t S_CMU:1;\r
+ vuint32_t :8;\r
+ } B;\r
+ } PS3;\r
+\r
+ vuint8_t ME_reserved4[16]; /* reserved 16 bytes (Base+0x0070-0x007F) */\r
+\r
+ union { /* RUN Peripheral Config 0..7 (+0x0080-009C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t RUN3:1;\r
+ vuint32_t RUN2:1;\r
+ vuint32_t RUN1:1;\r
+ vuint32_t RUN0:1;\r
+ vuint32_t DRUN:1;\r
+ vuint32_t SAFE:1;\r
+ vuint32_t TEST:1;\r
+ vuint32_t RESET:1;\r
+ } B;\r
+ } RUNPC[8];\r
+\r
+ union { /* Low Pwr Periph Config 0..7 (+0x00A0-0x00BC) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :18;\r
+ vuint32_t STANDBY0:1;\r
+ vuint32_t :2;\r
+ vuint32_t STOP0:1;\r
+ vuint32_t :1;\r
+ vuint32_t HALT0:1;\r
+ vuint32_t :8;\r
+ } B;\r
+ } LPPC[8];\r
+\r
+\r
+ /* Note on PCTL registers: There are only some PCTL implemented in */\r
+ /* Bolero 1.5M/1M. In order to make the PCTL easily addressable, these */\r
+ /* are defined as an array (ie ME.PCTL[x].R). This means you have */\r
+ /* to be careful when addressing these registers in order not to */\r
+ /* access a PCTL that is not implemented. Following are available: */\r
+ /* 104, 92, 91, 73, 72, 69, 68, 60, 57, 55, 53, 51, 50, 49,48, */\r
+ /* 44, 33, 32, 23, 21-16, 13, 12, 9-4 */\r
+\r
+ union { /* Peripheral Control 0..143 (+0x00C0-0x014F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t DBG_F:1;\r
+ vuint8_t LP_CFG:3;\r
+ vuint8_t RUN_CFG:3;\r
+ } B;\r
+ } PCTL[105];\r
+\r
+}; /* end of ME_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : CGM */\r
+/****************************************************************************/\r
+struct CGM_tag{\r
+ /*\r
+ The "CGM" has fairly wide coverage and essentially includes everything in\r
+\r
+ chapter 9 of the Bolero Reference Manual:\r
+\r
+ Base Address | Clock Sources\r
+\r
+ ----------------------------- \r
+\r
+ 0xC3FE0000 | FXOSC_CTL\r
+\r
+ 0xC3FE0040 | SXOSC_CTL\r
+\r
+ 0xC3FE0060 | FIRC_CTL\r
+\r
+ 0xC3FE0080 | SIRC_CTL\r
+\r
+ 0xC3FE00A0 | FMPLL\r
+\r
+ 0xC3FE00C0 | CGM Block 1\r
+\r
+ 0xC3FE0100 | CMU \r
+\r
+ 0xC3FE0120 | CGM Block 2\r
+\r
+\r
+\r
+ In this header file, "Base" referrs to the 1st address, 0xC3FE_0000 \r
+\r
+ */\r
+ /* FXOSC - 0xC3FE_0000*/\r
+ union { /* Fast OSC Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OSCBYP:1;\r
+ vuint32_t :7;\r
+ vuint32_t EOCV:8;\r
+ vuint32_t M_OSC:1;\r
+ vuint32_t :2;\r
+ vuint32_t OSCDIV:5;\r
+ vuint32_t I_OSC:1;\r
+ vuint32_t:7;\r
+ } B;\r
+ } FXOSC_CTL;\r
+\r
+\r
+ /* Reserved Space between end of FXOSC and start SXOSC */\r
+ vuint8_t CGM_reserved0[60]; /* Reserved 60 bytes (Base+0x0004-0x003F) */\r
+\r
+\r
+ /* SXOSC - 0xC3FE_0040*/\r
+ union { /* Slow Osc Control (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OSCBYP:1;\r
+ vuint32_t :7;\r
+ vuint32_t EOCV:8;\r
+ vuint32_t M_OSC:1;\r
+ vuint32_t :2;\r
+ vuint32_t OSCDIV:5;\r
+ vuint32_t I_OSC:1;\r
+ vuint32_t :5;\r
+ vuint32_t S_OSC:1;\r
+ vuint32_t OSCON:1;\r
+ } B;\r
+ } SXOSC_CTL;\r
+\r
+\r
+ /* Reserved space between end of SXOSC and start of FIRC */\r
+ vuint8_t CGM_reserved1[28]; /*Reserved 28 bytes (Base+0x0044-0x005F) */\r
+\r
+\r
+ /* FIRC - 0xC3FE_0060 */\r
+ union { /* Fast IRC Control (Base+0x0060) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :10;\r
+ vuint32_t RCTRIM:6;\r
+ vuint32_t :3;\r
+ vuint32_t RCDIV:5;\r
+ vuint32_t :2;\r
+ vuint32_t FIRCON_STDBY:1;\r
+ vuint32_t :5;\r
+ } B;\r
+ } FIRC_CTL;\r
+\r
+\r
+ /* Reserved space between end of FIRC and start of SIRC */\r
+ vuint8_t CGM_reserved2[28]; /*Reserved 28 bytes (Base+0x0064-0x007F) */\r
+\r
+\r
+ /* SIRC - 0xC3FE_0080 */\r
+ union { /* Slow IRC Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :11;\r
+ vuint32_t SIRCTRIM:5;\r
+ vuint32_t :3;\r
+ vuint32_t SIRCDIV:5;\r
+ vuint32_t :3;\r
+ vuint32_t S_SIRC:1;\r
+ vuint32_t :3;\r
+ vuint32_t SIRCON_STDBY:1;\r
+ } B;\r
+ } SIRC_CTL;\r
+\r
+\r
+ /* Reserved space between end of SIRC and start of FMPLL */\r
+ vuint8_t CGM_reserved3[28]; /*Reserved 28 bytes (Base+0x0084-0x009F) */\r
+\r
+\r
+ /* FMPLL - 0xC3FE_00A0 */\r
+ union { /* FMPLL Control (Base+0x00A0) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t IDF:4;\r
+ vuint32_t ODF:2;\r
+ vuint32_t:1;\r
+ vuint32_t NDIV:7;\r
+ vuint32_t:7;\r
+ vuint32_t EN_PLL_SW:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t UNLOCK_ONCE:1;\r
+ vuint32_t:1;\r
+ vuint32_t I_LOCK:1;\r
+ vuint32_t S_LOCK:1;\r
+ vuint32_t PLL_FAIL_MASK:1;\r
+ vuint32_t PLL_FAIL_FLAG:1;\r
+ vuint32_t:1;\r
+ } B;\r
+ } FMPLL_CR;\r
+\r
+ union { /* FMPLL Modulation (Base+0x00A4) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t STRB_BYPASS:1;\r
+ vuint32_t :1;\r
+ vuint32_t SPRD_SEL:1;\r
+ vuint32_t MOD_PERIOD:13;\r
+ vuint32_t FM_EN:1;\r
+ vuint32_t INC_STEP:15;\r
+ } B;\r
+ } FMPLL_MR;\r
+\r
+\r
+ /* Reserved space between end of FMPLL and start of CGM Block 1 */\r
+ vuint8_t CGM_reserved4[88]; /*Reserved 88 bytes (Base+0x00A8-0x00FF) */\r
+\r
+ /* CMU - 0xC3FE_0100 */\r
+ union { /* CMU Control Status (Base+0x0100) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t SFM:1;\r
+ vuint32_t :13;\r
+ vuint32_t CLKSEL1:2;\r
+ vuint32_t :5;\r
+ vuint32_t RCDIV:2;\r
+ vuint32_t CME_A:1;\r
+ } B;\r
+ } CMU_CSR;\r
+\r
+ union { /* CMU Frequency Display (Base+0x0104) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :12;\r
+ vuint32_t FD:20;\r
+ } B;\r
+ } CMU_FDR;\r
+\r
+ union { /* CMU High Freq Reference FMPLL (Base+0x0108) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t HFREF:12;\r
+ } B;\r
+ } CMU_HFREFR;\r
+\r
+ union { /* CMU Low Freq Reference FMPLL (Base+0x010C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :20;\r
+ vuint32_t LFREF:12;\r
+ } B;\r
+ } CMU_LFREFR;\r
+\r
+ union { /* CMU Interrupt Status (Base+0x0110) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :29;\r
+ vuint32_t FHHI:1; // *_A not present in RM\r
+ vuint32_t FLLI:1; // *_A not present in RM\r
+ vuint32_t OLRI:1;\r
+ } B;\r
+ } CMU_ISR;\r
+\r
+ /* Reserved space where IMR was previously positioned */\r
+ vuint8_t CGM_reserved5[4]; /*Reserved 4 bytes (Base+0x0114-0x0117) */\r
+\r
+ union { /* CMU Measurement Duration (Base+0x0118) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :12;\r
+ vuint32_t MD:20;\r
+ } B;\r
+ } CMU_MDR;\r
+\r
+\r
+ /* Reserved space between end of CMU and start of CGM Block 2 */\r
+ vuint8_t CGM_reserved6[596]; /*Reserved 596 bytes (Base+0x011C-0x036F) */\r
+\r
+ union { /* GCM Output Clock Enable (Base+0x0370) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t EN:1;\r
+ } B;\r
+ } OC_EN;\r
+\r
+ union { /* CGM Output Clock Division Sel (Base+0x0374) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :2;\r
+ vuint32_t SELDIV:2;\r
+ vuint32_t SELCTL:4;\r
+ vuint32_t :24;\r
+ } B;\r
+ } OCDS_SC;\r
+\r
+ union { /* CGM System Clock Select Status (Base+0x0378) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t SELSTAT:4;\r
+ vuint32_t :24;\r
+ } B;\r
+ } SC_SS;\r
+\r
+ union { /* CGM Sys Clk Div Config 0.2 (0x037C-0x037E) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t DE:1;\r
+ vuint8_t :3;\r
+ vuint8_t DIV:4;\r
+ } B;\r
+ } SC_DC[3];\r
+\r
+ // vuint8_t CGM_reserved7[15489]; /*Reserved 1 byte (Base+0x037F - 0x3FFF) */\r
+\r
+}; /* end of CGM_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : RGM base address - 0xC3FE_4000 */\r
+/****************************************************************************/\r
+struct RGM_tag{\r
+\r
+ union { /* Functional Event Status (Base+0x0000) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t F_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t F_FLASH:1;\r
+ vuint16_t F_LVD45:1;\r
+ vuint16_t F_CMU_FHL:1;\r
+ vuint16_t F_CMU_OLR:1;\r
+ vuint16_t F_FMPLL:1;\r
+ vuint16_t F_CHKSTOP:1;\r
+ vuint16_t F_SOFT:1;\r
+ vuint16_t F_CORE:1;\r
+ vuint16_t F_JTAG:1;\r
+ } B;\r
+ } FES;\r
+\r
+ union { /* Destructive Event Status (Base+0x0002) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t F_POR:1;\r
+ vuint16_t :10;\r
+ vuint16_t F_LVD27_VREG:1;\r
+ vuint16_t F_LVD27:1;\r
+ vuint16_t F_SWT:1;\r
+ vuint16_t F_LVD12_PD1:1;\r
+ vuint16_t F_LVD12_PD0:1;\r
+ } B;\r
+ } DES;\r
+\r
+ union { /* Functional Event Reset Disable (+0x0004) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t D_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t D_FLASH:1;\r
+ vuint16_t D_LVD45:1;\r
+ vuint16_t D_CMU_FHL:1;\r
+ vuint16_t D_CMU_OLR:1;\r
+ vuint16_t D_FMPLL:1;\r
+ vuint16_t D_CHKSTOP:1;\r
+ vuint16_t D_SOFT:1;\r
+ vuint16_t D_CORE:1;\r
+ vuint16_t D_JTAG:1;\r
+ } B;\r
+ } FERD;\r
+\r
+ union { /* Destructive Event Reset Disable (Base+0x0006)*/\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :11;\r
+ vuint16_t D_LVD27_VREG:1;\r
+ vuint16_t D_LVD27:1;\r
+ vuint16_t D_SWT:1;\r
+ vuint16_t D_LVD12_PD1:1;\r
+ vuint16_t D_LVD12_PD0:1;\r
+ } B;\r
+ } DERD;\r
+\r
+ vuint8_t RGM_reserved0[8]; /*Reserved 8 bytes (Base+0x008-0x000F) */\r
+\r
+ union { /* Functional Event Alt Request (Base+0x0010) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t AR_EXR:1;\r
+ vuint16_t:6;\r
+ vuint16_t AR_FLASH:1;\r
+ vuint16_t AR_LVD45:1;\r
+ vuint16_t AR_CMU_FHL:1;\r
+ vuint16_t AR_CMU_OLR:1;\r
+ vuint16_t AR_FMPLL:1;\r
+ vuint16_t AR_CHKSTOP:1;\r
+ vuint16_t AR_SOFT:1;\r
+ vuint16_t AR_CORE:1;\r
+ vuint16_t AR_JTAG:1;\r
+ } B;\r
+ } FEAR;\r
+ \r
+ union { /* Destructive Event Alt Request (Base+0x0012) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:11;\r
+ vuint16_t AR_LVD27_VREG:1;\r
+ vuint16_t AR_LVD27:1;\r
+ vuint16_t AR_SWT:1;\r
+ vuint16_t AR_LVD12_PD1:1;\r
+ vuint16_t AR_LVD12_PD0:1;\r
+ } B;\r
+ } DEAR; /* Destructive Event Alternate Request */\r
+\r
+ vuint8_t RGM_reserved1[4]; /*Reserved 4 bytes (Base+0x0014-0x0017) */\r
+\r
+ union { /* Functional Event Short Sequence (+0x0018) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t SS_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t SS_FLASH:1;\r
+ vuint16_t SS_LVD45:1;\r
+ vuint16_t SS_CMU_FHL:1;\r
+ vuint16_t SS_CMU_OLR:1;\r
+ vuint16_t SS_FMPLL:1;\r
+ vuint16_t SS_CHKSTOP:1;\r
+ vuint16_t SS_SOFT:1;\r
+ vuint16_t SS_CORE:1;\r
+ vuint16_t SS_JTAG:1;\r
+ } B;\r
+ } FESS;\r
+\r
+ union { /* STANDBY reset sequence (Base+0x001A) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t :8;\r
+ vuint16_t BOOT_FROM_BKP_RAM:1;\r
+ vuint16_t :7;\r
+ } B;\r
+ } STDBY;\r
+\r
+ union { /* Functional Bidirectional Reset En (+0x001C) */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t BE_EXR:1;\r
+ vuint16_t :6;\r
+ vuint16_t BE_FLASH:1;\r
+ vuint16_t BE_LVD45:1;\r
+ vuint16_t BE_CMU_FHL:1;\r
+ vuint16_t BE_CMU_OLR:1;\r
+ vuint16_t BE_FMPLL:1;\r
+ vuint16_t BE_CHKSTOP:1;\r
+ vuint16_t BE_SOFT:1;\r
+ vuint16_t BE_CORE:1;\r
+ vuint16_t BE_JTAG:1;\r
+ } B;\r
+ } FBRE;\r
+\r
+}; /* end of RGM_tag */\r
+/****************************************************************************/\r
+/* MODULE : PCU (base address 0xC3FE_8000) */\r
+/****************************************************************************/\r
+struct PCU_tag{\r
+\r
+ union { /* PCU Power domain 0-3 config (+0x0000-0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :18;\r
+ vuint32_t STBY0:1;\r
+ vuint32_t :2;\r
+ vuint32_t STOP0:1;\r
+ vuint32_t :1;\r
+ vuint32_t HALT0:1;\r
+ vuint32_t RUN3:1;\r
+ vuint32_t RUN2:1;\r
+ vuint32_t RUN1:1;\r
+ vuint32_t RUN0:1;\r
+ vuint32_t DRUN:1;\r
+ vuint32_t SAFE:1;\r
+ vuint32_t TEST:1;\r
+ vuint32_t RST:1;\r
+ } B;\r
+ } PCONF[4];\r
+\r
+ vuint8_t PCU_reserved0[48]; /* Reserved 48 bytes (Base+0x0010-0x003F) */\r
+\r
+ union { /* PCU Power Domain Status (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :28;\r
+ vuint32_t PD3:1;\r
+ vuint32_t PD2:1;\r
+ vuint32_t PD1:1;\r
+ vuint32_t PD0:1;\r
+ } B;\r
+ } PSTAT;\r
+\r
+ vuint8_t PCU_reserved1[60]; /* Reserved 60 bytes (Base+0x0044-0x007F) */\r
+\r
+\r
+ /* Following register is from Voltage Regulators chapter of RM */\r
+\r
+ union { /* PCU Voltage Regulator Control (Base+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t MASK_LVDHV5:1;\r
+ } B;\r
+ } VREG_CTL; /* Changed from VCTL for consistency with other regs here */\r
+\r
+ }; /* end of PCU_tag */\r
+ \r
+/****************************************************************************/\r
+/* MODULE : CTU Lite(base address - 0xFFE6_4000) */\r
+/****************************************************************************/\r
+struct CTUL_tag{\r
+\r
+ // union { /* CTU Control Status Register (Base+0x0000)NOT PRESENT WITHIN RM*/\r
+ // vuint32_t R;\r
+ // struct {\r
+ // vuint32_t :24;\r
+ // vuint32_t TRGIEN:1;\r
+ // vuint32_t TRGI:1;\r
+ // vuint32_t :6;\r
+ // } B;\r
+ // } CSR;\r
+\r
+ vuint8_t CTU_reserved[48]; /* Reserved 48 bytes (Base+0x0000-0x002F) */\r
+\r
+ union { /* Event Config 0..63 (Base+0x0030-0x012C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t TM:1;\r
+ vuint32_t CLR_FLAG:1;\r
+ vuint32_t :5;\r
+ vuint32_t ADC_SEL:1;\r
+ vuint32_t :1;\r
+ vuint32_t CHANNEL_VALUE:7;\r
+ } B;\r
+ } EVTCFGR[64];\r
+\r
+\r
+}; /* end of CTUL_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : EMIOS (base address - eMIOS0 0xC3FA_0000; eMIOS1 0xC3FA_4000) */\r
+/****************************************************************************/\r
+\r
+struct EMIOS_CHANNEL_tag{\r
+\r
+ union { /* Channel A Data (UCn Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t A:16;\r
+ } B;\r
+ } CADR;\r
+\r
+ union { /* Channel B Data (UCn Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t B:16;\r
+ } B;\r
+ } CBDR;\r
+\r
+ union { /* Channel Counter (UCn Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t C:16;\r
+ } B;\r
+ } CCNTR;\r
+\r
+ union { /* Channel Control (UCn Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FREN:1;\r
+ vuint32_t :3;\r
+ vuint32_t UCPRE:2;\r
+ vuint32_t UCPEN:1;\r
+ vuint32_t DMA:1;\r
+ vuint32_t :1;\r
+ vuint32_t IF:4;\r
+ vuint32_t FCK:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t :3;\r
+ vuint32_t FORCMA:1;\r
+ vuint32_t FORCMB:1;\r
+ vuint32_t :1;\r
+ vuint32_t BSL:2;\r
+ vuint32_t EDSEL:1;\r
+ vuint32_t EDPOL:1;\r
+ vuint32_t MODE:7;\r
+ } B;\r
+ } CCR;\r
+\r
+ union { /* Channel Status (UCn Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OVR:1;\r
+ vuint32_t :15;\r
+ vuint32_t OVFL:1;\r
+ vuint32_t :12;\r
+ vuint32_t UCIN:1;\r
+ vuint32_t UCOUT:1;\r
+ vuint32_t FLAG:1;\r
+ } B;\r
+ } CSR;\r
+\r
+ union { /* Alternate Channel A Data (UCn Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t ALTA:16;\r
+ } B;\r
+ } ALTCADR;\r
+\r
+ vuint8_t EMIOS_CHANNEL_reserved0[8]; /* (UCn Base + (0x0018-0x001F) */\r
+\r
+}; /* end of EMIOS_CHANNEL_tag */\r
+\r
+\r
+struct EMIOS_tag{\r
+\r
+ union { /* Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t GTBE:1;\r
+ vuint32_t :1;\r
+ vuint32_t GPREN:1;\r
+ vuint32_t :10;\r
+ vuint32_t GPRE:8;\r
+ vuint32_t :8;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* Global Flag (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t F31:1;\r
+ vuint32_t F30:1;\r
+ vuint32_t F29:1;\r
+ vuint32_t F28:1;\r
+ vuint32_t F27:1;\r
+ vuint32_t F26:1;\r
+ vuint32_t F25:1;\r
+ vuint32_t F24:1;\r
+ vuint32_t F23:1;\r
+ vuint32_t F22:1;\r
+ vuint32_t F21:1;\r
+ vuint32_t F20:1;\r
+ vuint32_t F19:1;\r
+ vuint32_t F18:1;\r
+ vuint32_t F17:1;\r
+ vuint32_t F16:1;\r
+ vuint32_t F15:1;\r
+ vuint32_t F14:1;\r
+ vuint32_t F13:1;\r
+ vuint32_t F12:1;\r
+ vuint32_t F11:1;\r
+ vuint32_t F10:1;\r
+ vuint32_t F9:1;\r
+ vuint32_t F8:1;\r
+ vuint32_t F7:1;\r
+ vuint32_t F6:1;\r
+ vuint32_t F5:1;\r
+ vuint32_t F4:1;\r
+ vuint32_t F3:1;\r
+ vuint32_t F2:1;\r
+ vuint32_t F1:1;\r
+ vuint32_t F0:1;\r
+ } B;\r
+ } GFR;\r
+\r
+ union { /* Output Update Disable (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OU31:1;\r
+ vuint32_t OU30:1;\r
+ vuint32_t OU29:1;\r
+ vuint32_t OU28:1;\r
+ vuint32_t OU27:1;\r
+ vuint32_t OU26:1;\r
+ vuint32_t OU25:1;\r
+ vuint32_t OU24:1;\r
+ vuint32_t OU23:1;\r
+ vuint32_t OU22:1;\r
+ vuint32_t OU21:1;\r
+ vuint32_t OU20:1;\r
+ vuint32_t OU19:1;\r
+ vuint32_t OU18:1;\r
+ vuint32_t OU17:1;\r
+ vuint32_t OU16:1;\r
+ vuint32_t OU15:1;\r
+ vuint32_t OU14:1;\r
+ vuint32_t OU13:1;\r
+ vuint32_t OU12:1;\r
+ vuint32_t OU11:1;\r
+ vuint32_t OU10:1;\r
+ vuint32_t OU9:1;\r
+ vuint32_t OU8:1;\r
+ vuint32_t OU7:1;\r
+ vuint32_t OU6:1;\r
+ vuint32_t OU5:1;\r
+ vuint32_t OU4:1;\r
+ vuint32_t OU3:1;\r
+ vuint32_t OU2:1;\r
+ vuint32_t OU1:1;\r
+ vuint32_t OU0:1;\r
+ } B;\r
+ } OUDR;\r
+\r
+ union { /* Disable Channel (Base+0x000F) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CHDIS31:1;\r
+ vuint32_t CHDIS30:1;\r
+ vuint32_t CHDIS29:1;\r
+ vuint32_t CHDIS28:1;\r
+ vuint32_t CHDIS27:1;\r
+ vuint32_t CHDIS26:1;\r
+ vuint32_t CHDIS25:1;\r
+ vuint32_t CHDIS24:1;\r
+ vuint32_t CHDIS23:1;\r
+ vuint32_t CHDIS22:1;\r
+ vuint32_t CHDIS21:1;\r
+ vuint32_t CHDIS20:1;\r
+ vuint32_t CHDIS19:1;\r
+ vuint32_t CHDIS18:1;\r
+ vuint32_t CHDIS17:1;\r
+ vuint32_t CHDIS16:1;\r
+ vuint32_t CHDIS15:1;\r
+ vuint32_t CHDIS14:1;\r
+ vuint32_t CHDIS13:1;\r
+ vuint32_t CHDIS12:1;\r
+ vuint32_t CHDIS11:1;\r
+ vuint32_t CHDIS10:1;\r
+ vuint32_t CHDIS9:1;\r
+ vuint32_t CHDIS8:1;\r
+ vuint32_t CHDIS7:1;\r
+ vuint32_t CHDIS6:1;\r
+ vuint32_t CHDIS5:1;\r
+ vuint32_t CHDIS4:1;\r
+ vuint32_t CHDIS3:1;\r
+ vuint32_t CHDIS2:1;\r
+ vuint32_t CHDIS1:1;\r
+ vuint32_t CHDIS0:1;\r
+ } B;\r
+ } UCDIS;\r
+\r
+ vuint8_t EMIOS_reserved0[16]; /* Reserved 16 Bytes (Base+0x0010-0x001F) */\r
+\r
+ struct EMIOS_CHANNEL_tag CH[32]; /* Add in 32 unified channels */\r
+\r
+ vuint8_t EMIOS_reserved1[3040]; /* 3040 bytes (Base+0x0420-0x0FFF) */\r
+\r
+}; /* end of EMIOS_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : PIT (base address - 0xC3FF_FFFF) */\r
+/****************************************************************************/\r
+ struct PIT_tag {\r
+\r
+ union { /* PIT Module Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ } B;\r
+ } PITMCR;\r
+\r
+ vuint8_t PIT_reserved0[252]; /* Reserved 252 Bytes (Base+0x0004-0x00FF) */\r
+\r
+ /* PIT Timer Channels 0..7 (Base+0x0100-0x017C) */\r
+ struct {\r
+\r
+ union { /* PIT Timer Load Value (Offset+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSV:32;\r
+ } B;\r
+ } LDVAL;\r
+\r
+ union { /* PIT Current Timer Value (Offset+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TVL:32;\r
+ } B;\r
+ } CVAL;\r
+\r
+ union { /* PIT Timer Control (Offset+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :30;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } TCTRL;\r
+\r
+ union { /* PIT Timer Control (Offset+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } TFLG;\r
+\r
+ }CH[8]; /* End of PIT Timer Channels */\r
+\r
+}; /* end of PIT_tag */\r
+/****************************************************************************/\r
+/* MODULE : I2C (base address - 0xFFE3_0000) */\r
+/****************************************************************************/\r
+struct I2C_tag{\r
+\r
+ union { /* I2C Bus Address (Base+0x0000) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ADR:7;\r
+ vuint8_t :1;\r
+ } B;\r
+ } IBAD;\r
+\r
+ union { /* I2C Bus Frequency Divider (Base+0x0001) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t IBC:8;\r
+ } B;\r
+ } IBFD;\r
+\r
+ union { /* I2C Bus Control (Base+0x0002) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t MDIS:1;\r
+ vuint8_t IBIE:1;\r
+ vuint8_t MS:1; /*different from RM for backward compatiblity MSSL in RM*/ \r
+ vuint8_t TX:1;\r
+ vuint8_t NOACK:1;\r
+ vuint8_t RSTA:1;\r
+ vuint8_t DMAEN:1;\r
+ vuint8_t :1;\r
+ } B;\r
+ } IBCR;\r
+\r
+ union { /* I2C Bus Status (Base+0x0003) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t TCF:1;\r
+ vuint8_t IAAS:1;\r
+ vuint8_t IBB:1;\r
+ vuint8_t IBAL:1;\r
+ vuint8_t :1;\r
+ vuint8_t SRW:1;\r
+ vuint8_t IBIF:1;\r
+ vuint8_t RXAK:1;\r
+ } B;\r
+ } IBSR;\r
+\r
+ union { /* I2C Bus Data I/O (Base+0x0004) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t DATA:8;\r
+ } B;\r
+ } IBDR;\r
+\r
+ union { /* I2C Interrupt Configuration (Base+0x0005) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t BIIE:1;\r
+ vuint8_t :7;\r
+ } B;\r
+ } IBIC;\r
+\r
+ vuint8_t I2C_reserved0[16378]; /* Reserved 16378 (Base+0x0006-0x3FFF) */\r
+\r
+}; /* end of i2c_tag */\r
+/****************************************************************************/\r
+/* MODULE : MPU (base address - 0xFFF1_0000) */\r
+/****************************************************************************/\r
+ struct MPU_tag {\r
+\r
+ union { /* Control/Error Status (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :5;\r
+ vuint32_t SPERR:3;\r
+ vuint32_t:4;\r
+ vuint32_t HRL:4;\r
+ vuint32_t NSP:4;\r
+ vuint32_t NGRD:4;\r
+ vuint32_t :7;\r
+ vuint32_t VLD:1;\r
+ } B;\r
+ } CESR;\r
+\r
+ vuint8_t MPU_reserved0[12]; /* Reserved 12 Bytes (Base+0x0004-0x000F) */\r
+\r
+\r
+ union { /* Error Address Slave Port0 (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR0;\r
+\r
+ union { /* Error Detail Slave Port0 (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EACD:8;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR0;\r
+\r
+\r
+ union { /* Error Address Slave Port1 (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR1;\r
+\r
+ union { /* Error Detail Slave Port1 (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EACD:8;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR1;\r
+\r
+\r
+ union { /* Error Address Slave Port2 (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR2;\r
+\r
+ union { /* Error Detail Slave Port2 (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :8;\r
+ vuint32_t EACD:8;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR2;\r
+\r
+ vuint8_t MPU_reserved1[984]; /* Reserved 984 Bytes (Base+0x0028-0x03FF) */\r
+\r
+ struct { /* Region Descriptor 0..15 (Base+0x0400-0x0470) */\r
+\r
+ union { /* - Word 0 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SRTADDR:27;\r
+ vuint32_t :5;\r
+ } B;\r
+ } WORD0;\r
+\r
+ union { /* - Word 1 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ENDADDR:27;\r
+ vuint32_t :5;\r
+ } B;\r
+ } WORD1;\r
+\r
+ union { /* - Word 2 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t M7RE:1;\r
+ vuint32_t M7WE:1;\r
+ vuint32_t M6RE:1;\r
+ vuint32_t M6WE:1;\r
+ vuint32_t M5RE:1;\r
+ vuint32_t M5WE:1;\r
+ vuint32_t M4RE:1;\r
+ vuint32_t M4WE:1;\r
+ vuint32_t M3PE:1;\r
+ vuint32_t M3SM:2;\r
+ vuint32_t M3UM:3;\r
+ vuint32_t M2PE:1;\r
+ vuint32_t M2SM:2;\r
+ vuint32_t M2UM:2;\r
+ vuint32_t :7; \r
+ vuint32_t M0PE:1;\r
+ vuint32_t M0SM:2;\r
+ vuint32_t M0UM:3;\r
+ } B;\r
+ } WORD2;\r
+\r
+ union { /* - Word 3 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PID:8;\r
+ vuint32_t PIDMASK:8;\r
+ vuint32_t :15;\r
+ vuint32_t VLD:1;\r
+ } B;\r
+ } WORD3;\r
+\r
+ }RGD[8]; /* End of Region Descriptor Structure) */\r
+\r
+ vuint8_t MPU_reserved2[896]; /* Reserved 896 Bytes (Base+0x0480-0x07FF) */\r
+\r
+ union { /* Region Descriptor Alt 0..15 (0x0800-0x081C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t M7RE:1;\r
+ vuint32_t M7WE:1;\r
+ vuint32_t M6RE:1;\r
+ vuint32_t M6WE:1;\r
+ vuint32_t M5RE:1;\r
+ vuint32_t M5WE:1;\r
+ vuint32_t M4RE:1;\r
+ vuint32_t M4WE:1;\r
+ vuint32_t M3PE:1;\r
+ vuint32_t M3SM:2;\r
+ vuint32_t M3UM:3;\r
+ vuint32_t M2PE:1;\r
+ vuint32_t M2SM:2;\r
+ vuint32_t M2UM:2;\r
+ vuint32_t :7; \r
+ vuint32_t M0PE:1;\r
+ vuint32_t M0SM:2;\r
+ vuint32_t M0UM:3;\r
+ } B;\r
+ } RGDAAC[8];\r
+\r
+ vuint8_t MPU_reserved3[14304]; /* Reserved 14304 Bytes (+0x0820-0x03FFF) */\r
+\r
+}; /* end of MPU_tag */\r
+/****************************************************************************/\r
+/* MODULE : eDMA (base address - 0xFFF4_4000) */\r
+/****************************************************************************/\r
+\r
+ /*for "standard" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=0) */\r
+ struct EDMA_TCD_STD_tag {\r
+\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (?minor?) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITER:15;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */\r
+ vuint16_t BITER:15;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+\r
+ }; /* end of EDMA_TCD_STD_tag */\r
+\r
+ /*for "channel link" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=1)*/\r
+ struct EDMA_TCD_CHLINK_tag {\r
+\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (?minor?) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITERLINKCH:6;\r
+ vuint16_t CITER:9;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning (?major?) iteration count */\r
+ vuint16_t BITERLINKCH:6;\r
+ vuint16_t BITER:9;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+\r
+ }; /* end of EDMA_TCD_CHLINK_tag */\r
+\r
+\r
+\r
+struct EDMA_tag {\r
+\r
+ union { /* Control (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :14;\r
+ vuint32_t CX:1;\r
+ vuint32_t ECX:1;\r
+ vuint32_t :6; \r
+ vuint32_t GRP0PRI:2;\r
+ vuint32_t EMLM:1;\r
+ vuint32_t CLM:1;\r
+ vuint32_t HALT:1;\r
+ vuint32_t HOE:1;\r
+ vuint32_t ERGA:1;\r
+ vuint32_t ERCA:1;\r
+ vuint32_t EDBG:1;\r
+ vuint32_t EBW:1;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* Error Status (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VLD:1;\r
+ vuint32_t :16;\r
+ vuint32_t CPE:1;\r
+ vuint32_t ERRCHN:6;\r
+ vuint32_t SAE:1;\r
+ vuint32_t SOE:1;\r
+ vuint32_t DAE:1;\r
+ vuint32_t DOE:1;\r
+ vuint32_t NCE:1;\r
+ vuint32_t SGE:1;\r
+ vuint32_t SBE:1;\r
+ vuint32_t DBE:1;\r
+ } B;\r
+ } ESR;\r
+\r
+ vuint8_t eDMA_reserved0[4]; /* Reserved 4 bytes (Base+0x0008-0x000B)*/\r
+\r
+ union { /* Enable Request Low Ch15..0 (Base+0x000C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t ERQ15:1;\r
+ vuint32_t ERQ14:1;\r
+ vuint32_t ERQ13:1;\r
+ vuint32_t ERQ12:1;\r
+ vuint32_t ERQ11:1;\r
+ vuint32_t ERQ10:1;\r
+ vuint32_t ERQ09:1;\r
+ vuint32_t ERQ08:1;\r
+ vuint32_t ERQ07:1;\r
+ vuint32_t ERQ06:1;\r
+ vuint32_t ERQ05:1;\r
+ vuint32_t ERQ04:1;\r
+ vuint32_t ERQ03:1;\r
+ vuint32_t ERQ02:1;\r
+ vuint32_t ERQ01:1;\r
+ vuint32_t ERQ00:1;\r
+ } B;\r
+ } ERQRL;\r
+\r
+ vuint8_t eDMA_reserved1[4]; /* Reserved 4 bytes (Base+0x0010-0x0013)*/\r
+\r
+ union { /* Enable Error Interrupt Low (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t EEI15:1;\r
+ vuint32_t EEI14:1;\r
+ vuint32_t EEI13:1;\r
+ vuint32_t EEI12:1;\r
+ vuint32_t EEI11:1;\r
+ vuint32_t EEI10:1;\r
+ vuint32_t EEI09:1;\r
+ vuint32_t EEI08:1;\r
+ vuint32_t EEI07:1;\r
+ vuint32_t EEI06:1;\r
+ vuint32_t EEI05:1;\r
+ vuint32_t EEI04:1;\r
+ vuint32_t EEI03:1;\r
+ vuint32_t EEI02:1;\r
+ vuint32_t EEI01:1;\r
+ vuint32_t EEI00:1;\r
+ } B;\r
+ } EEIRL;\r
+\r
+ union { /* DMA Set Enable Request (Base+0x0018) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t SERQ:7;\r
+ } B;\r
+ } SERQR;\r
+\r
+ union { /* DMA Clear Enable Request (Base+0x0019) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CERQ:7;\r
+ } B;\r
+ } CERQR;\r
+\r
+ union { /* DMA Set Enable Error Interrupt (Base+0x001A) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t SEEI:7;\r
+ } B;\r
+ } SEEIR;\r
+\r
+ union { /* DMA Clr Enable Error Interrupt (Base+0x001B) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:1;\r
+ vuint8_t CEEI:7;\r
+ } B;\r
+ } CEEIR;\r
+\r
+ union { /* DMA Clear Interrupt Request (Base+0x001C) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CINT:7;\r
+ } B;\r
+ } CIRQR;\r
+\r
+ union { /* DMA Clear error (Base+0x001D) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CERR:7;\r
+ } B;\r
+ } CER;\r
+\r
+ union { /* DMA Set Start Bit (Base+0x001E) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t NOP:1;\r
+ vuint8_t SSB:7;\r
+ } B;\r
+ } SSBR;\r
+\r
+ union { /* DMA Clear Done Status Bit (Base+0x001F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t :1;\r
+ vuint8_t CDSB:7;\r
+ } B;\r
+ } CDSBR;\r
+\r
+ vuint8_t eDMA_reserved2[4]; /* Reserved 4 bytes (Base+0x0020-0x0023)*/\r
+\r
+ union { /* DMA Interrupt Req Low Ch15..0 (+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t INT15:1;\r
+ vuint32_t INT14:1;\r
+ vuint32_t INT13:1;\r
+ vuint32_t INT12:1;\r
+ vuint32_t INT11:1;\r
+ vuint32_t INT10:1;\r
+ vuint32_t INT09:1;\r
+ vuint32_t INT08:1;\r
+ vuint32_t INT07:1;\r
+ vuint32_t INT06:1;\r
+ vuint32_t INT05:1;\r
+ vuint32_t INT04:1;\r
+ vuint32_t INT03:1;\r
+ vuint32_t INT02:1;\r
+ vuint32_t INT01:1;\r
+ vuint32_t INT00:1;\r
+ } B;\r
+ } IRQRL;\r
+\r
+ vuint8_t eDMA_reserved3[4]; /* Reserved 4 bytes (Base+0x0028-0x002B)*/\r
+\r
+ union { /* DMA Error Low Ch15..0 (Base+0x002C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t ERR15:1;\r
+ vuint32_t ERR14:1;\r
+ vuint32_t ERR13:1;\r
+ vuint32_t ERR12:1;\r
+ vuint32_t ERR11:1;\r
+ vuint32_t ERR10:1;\r
+ vuint32_t ERR09:1;\r
+ vuint32_t ERR08:1;\r
+ vuint32_t ERR07:1;\r
+ vuint32_t ERR06:1;\r
+ vuint32_t ERR05:1;\r
+ vuint32_t ERR04:1;\r
+ vuint32_t ERR03:1;\r
+ vuint32_t ERR02:1;\r
+ vuint32_t ERR01:1;\r
+ vuint32_t ERR00:1;\r
+ } B;\r
+ } ERL;\r
+\r
+ vuint8_t eDMA_reserved4[4]; /* Reserved 4 bytes (Base+0x0030-0x0033)*/\r
+\r
+ union { /* DMA Hardware Request Stat Low (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t HRS15:1;\r
+ vuint32_t HRS14:1;\r
+ vuint32_t HRS13:1;\r
+ vuint32_t HRS12:1;\r
+ vuint32_t HRS11:1;\r
+ vuint32_t HRS10:1;\r
+ vuint32_t HRS09:1;\r
+ vuint32_t HRS08:1;\r
+ vuint32_t HRS07:1;\r
+ vuint32_t HRS06:1;\r
+ vuint32_t HRS05:1;\r
+ vuint32_t HRS04:1;\r
+ vuint32_t HRS03:1;\r
+ vuint32_t HRS02:1;\r
+ vuint32_t HRS01:1;\r
+ vuint32_t HRS00:1;\r
+ } B;\r
+ } HRSL;\r
+\r
+ vuint8_t eDMA_reserved5[200]; /* Reserved 200 bytes (Base+0x0038-0x00FF)*/\r
+\r
+ union { /* Channel n Priority (Base+0x0100-0x010F)*/\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ECP:1;\r
+ vuint8_t DPA:1;\r
+ vuint8_t GRPPRI:2;\r
+ vuint8_t CHPRI:4;\r
+ } B;\r
+ } CPR[16];\r
+\r
+ vuint8_t eDMA_reserved6[3824]; /* Reserved 3808 bytes (+0x0110-0x0FFF) */\r
+\r
+ /* Transfer Control Descriptors 0..16 (Base+0x1000-0x11E0) */\r
+ struct EDMA_TCD_STD_tag TCD[16];\r
+ \r
+ /* or change to following if using channel linking */\r
+ /* Struct EDMA_TCD_CHLINK_tag TCD[16]; */\r
+ \r
+ vuint8_t eDMA_reserved7[28160]; /* Reserved 28160 bytes (+0x1200-0x7FFF) */\r
+\r
+}; /* end of EDMA_tag */\r
+/*************************************************************************/\r
+/* MODULE : INTC (base address - 0xFFF4_8000) */\r
+/*************************************************************************/\r
+struct INTC_tag {\r
+\r
+ union { /* INTC Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t VTES:1;\r
+ vuint32_t:4;\r
+ vuint32_t HVEN:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ vuint8_t INTC_reserved0[4]; /* reserved 4 bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* INTC Current Priority (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t PRI:4;\r
+ } B;\r
+ } CPR;\r
+ \r
+ vuint8_t INTC_reserved1[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */\r
+\r
+ union { /* INTC Interrupt Acknowledge (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VTBA_PRC0:21;\r
+ vuint32_t INTVEC_PRC0:9;\r
+ vuint32_t:2;\r
+ } B;\r
+ } IACKR;\r
+\r
+ vuint8_t INTC_reserved2[4]; /* Reserved 4 bytes (Base+0x0014-0x0017) */\r
+ \r
+ union { /* INTC End Of Interrupt (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } EOIR;\r
+\r
+ vuint8_t INTC_reserved3[4]; /* reserved 4 bytes (Base+0x001C-0x0019) */\r
+ \r
+ union { /* INTC Software Set/Clear Interrupt0-7 (+0x0020-0x0027) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t SET:1;\r
+ vuint8_t CLR:1;\r
+ } B;\r
+ } SSCIR[8];\r
+\r
+ vuint8_t INTC_reserved4[24]; /* Reserved 24 bytes (Base+0x0028-0x003F) */\r
+\r
+ union { /* INTC Priority Select (Base+0x0040-0x0128) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t PRI:4;\r
+ } B;\r
+ } PSR[234]; \r
+\r
+}; /* end of INTC_tag */\r
+/****************************************************************************/\r
+/* MODULE : DSPI */\r
+/* Base Addresses: */\r
+/* DSPI_0 - 0xFFF9_0000 */\r
+/* DSPI_1 - 0xFFF9_4000 */\r
+/* DSPI_2 - 0xFFF9_8000 */\r
+/* DSPI_3 - 0xFFF9_C000 */\r
+/* DSPI_4 - 0xFFFA_0000 */\r
+/* DSPI_5 - 0xFFFA_4000 */\r
+/****************************************************************************/\r
+struct DSPI_tag{\r
+\r
+ union { /* DSPI Module Configuraiton (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MSTR:1;\r
+ vuint32_t CONT_SCKE:1;\r
+ vuint32_t DCONF:2;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t MTFE:1;\r
+ vuint32_t PCSSE:1;\r
+ vuint32_t ROOE:1;\r
+ vuint32_t :2; \r
+ vuint32_t PCSIS5:1;\r
+ vuint32_t PCSIS4:1;\r
+ vuint32_t PCSIS3:1;\r
+ vuint32_t PCSIS2:1;\r
+ vuint32_t PCSIS1:1;\r
+ vuint32_t PCSIS0:1;\r
+ vuint32_t DOZE:1; \r
+ vuint32_t MDIS:1;\r
+ vuint32_t DIS_TXF:1;\r
+ vuint32_t DIS_RXF:1;\r
+ vuint32_t CLR_TXF:1;\r
+ vuint32_t CLR_RXF:1;\r
+ vuint32_t SMPL_PT:2;\r
+ vuint32_t :7;\r
+ vuint32_t HALT:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ vuint8_t DSPI_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */\r
+\r
+ union { /* DSPI Transfer Count (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCNT:16;\r
+ vuint32_t :16;\r
+ } B;\r
+ } TCR;\r
+\r
+ union { /* DSPI Clock & Tranfer Attrib 0-5 (+0x000C-0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DBR:1;\r
+ vuint32_t FMSZ:4;\r
+ vuint32_t CPOL:1;\r
+ vuint32_t CPHA:1;\r
+ vuint32_t LSBFE:1;\r
+ vuint32_t PCSSCK:2;\r
+ vuint32_t PASC:2;\r
+ vuint32_t PDT:2;\r
+ vuint32_t PBR:2;\r
+ vuint32_t CSSCK:4;\r
+ vuint32_t ASC:4;\r
+ vuint32_t DT:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } CTAR[6];\r
+\r
+ vuint8_t DSPI_reserved1[8]; /* Reserved 4 bytes (Base+0x0024-0x002B) */\r
+\r
+ union { /* DSPI Status (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCF:1;\r
+ vuint32_t TXRXS:1;\r
+ vuint32_t :1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t TFUF:1;\r
+ vuint32_t :1;\r
+ vuint32_t TFFF:1;\r
+ vuint32_t :5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t :1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t :1;\r
+ vuint32_t TXCTR:4;\r
+ vuint32_t TXNXTPTR:4;\r
+ vuint32_t RXCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } SR;\r
+\r
+ union { /* DSPI DMA/Int Request Select & Enable (+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCFRE:1;\r
+ vuint32_t :2;\r
+ vuint32_t EOQFRE:1;\r
+ vuint32_t TFUFRE:1;\r
+ vuint32_t :1;\r
+ vuint32_t TFFFRE:1;\r
+ vuint32_t TFFFDIRS:1;\r
+ vuint32_t :4;\r
+ vuint32_t RFOFRE:1;\r
+ vuint32_t :1;\r
+ vuint32_t RFDFRE:1;\r
+ vuint32_t RFDFDIRS:1;\r
+ vuint32_t :16;\r
+ } B;\r
+ } RSER;\r
+\r
+ union { /* DSPI Push TX FIFO (Base+0x0034) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CONT:1;\r
+ vuint32_t CTAS:3;\r
+ vuint32_t EOQ:1;\r
+ vuint32_t CTCNT:1;\r
+ vuint32_t :4; \r
+ vuint32_t PCS5:1;\r
+ vuint32_t PCS4:1;\r
+ vuint32_t PCS3:1;\r
+ vuint32_t PCS2:1;\r
+ vuint32_t PCS1:1;\r
+ vuint32_t PCS0:1;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } PUSHR;\r
+\r
+ union { /* DSPI Pop RX FIFO (Base+0x0038) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16; \r
+ vuint32_t RXDATA:16; \r
+ } B;\r
+ } POPR;\r
+\r
+ union { /* DSPI Transmit FIFO 0-3 (Base+0x003C-0x0048)*/\r
+ vuint32_t R;\r
+ struct { \r
+ vuint32_t TXCMD:16; \r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } TXFR[4];\r
+\r
+ vuint8_t DSPI_reserved2[48]; /* Reserved 48 bytes (Base+0x004C-0x007B) */\r
+\r
+ union { /* DSPI Receive FIFO 0-3 (Base+0x007C-0x0088) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16; \r
+ vuint32_t RXDATA:16; \r
+ } B;\r
+ } RXFR[4];\r
+ }; /* end of DSPI_tag */\r
+ /****************************************************************************/\r
+/* MODULE : FlexCAN */\r
+/* Base Addresses: */\r
+/* FlexCAN_0 - 0xFFFC_0000 */\r
+/* FlexCAN_1 - 0xFFFC_4000 */\r
+/* FlexCAN_2 - 0xFFFC_8000 */\r
+/* FlexCAN_3 - 0xFFFC_C000 */\r
+/* FlexCAN_4 - 0xFFFD_0000 */\r
+/* FlexCAN_5 - 0xFFFD_4000 */\r
+/****************************************************************************/\r
+struct FLEXCAN_BUF_t{\r
+\r
+ union { /* FLEXCAN MBx Control & Status (Offset+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t CODE:4;\r
+ vuint32_t :1;\r
+ vuint32_t SRR:1;\r
+ vuint32_t IDE:1;\r
+ vuint32_t RTR:1;\r
+ vuint32_t LENGTH:4;\r
+ vuint32_t TIMESTAMP:16;\r
+ } B;\r
+ } CS;\r
+\r
+ union { /* FLEXCAN MBx Identifier (Offset+0x0084) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRIO:3;\r
+ vuint32_t STD_ID:11;\r
+ vuint32_t EXT_ID:18;\r
+ } B;\r
+ } ID;\r
+\r
+ union { /* FLEXCAN MBx Data 0..7 (Offset+0x0088) */\r
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
+ } DATA;\r
+\r
+}; /* end of FLEXCAN_BUF_t */\r
+\r
+\r
+struct FLEXCAN_RXFIFO_t{ /* RxFIFO Configuration */\r
+\r
+ union { /* RxFIFO Control & Status (Offset+0x0080) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :9;\r
+ vuint32_t SRR:1;\r
+ vuint32_t IDE:1;\r
+ vuint32_t RTR:1;\r
+ vuint32_t LENGTH:4;\r
+ vuint32_t TIMESTAMP:16;\r
+ } B;\r
+ } CS;\r
+\r
+ union { /* RxFIFO Identifier (Offset+0x0084) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :3;\r
+ vuint32_t STD_ID:11;\r
+ vuint32_t EXT_ID:18;\r
+ } B;\r
+ } ID;\r
+\r
+ union { /* RxFIFO Data 0..7 (Offset+0x0088) */\r
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
+ } DATA;\r
+\r
+ vuint8_t FLEXCAN_RX_reserved0[80]; /* Reserved 80 bytes (+0x0090-0x00DF)*/\r
+\r
+ union { /* RxFIFO ID Table 0..7 (+0x00E0-0x00FC) */\r
+ vuint32_t R;\r
+ } IDTABLE[8];\r
+\r
+}; /* end of FLEXCAN_RXFIFO_t */\r
+\r
+\r
+struct FLEXCAN_tag{\r
+\r
+ union { /* FLEXCAN Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t HALT:1;\r
+ vuint32_t NOTRDY:1;\r
+ vuint32_t WAKMSK:1;\r
+ vuint32_t SOFTRST:1;\r
+ vuint32_t FRZACK:1;\r
+ vuint32_t SUPV:1;\r
+ vuint32_t SLFWAK:1; /*not present in RM*/\r
+ vuint32_t WRNEN:1;\r
+ vuint32_t LPMACK:1;\r
+ vuint32_t WAKSRC:1;\r
+ vuint32_t DOZE:1; /*not present in RM*/\r
+ vuint32_t SRXDIS:1;\r
+ vuint32_t BCC:1;\r
+ vuint32_t:2;\r
+ vuint32_t LPRIO_EN:1;\r
+ vuint32_t AEN:1;\r
+ vuint32_t:2;\r
+ vuint32_t IDAM:2;\r
+ vuint32_t:2;\r
+ vuint32_t MAXMB:6;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* FLEXCAN Control (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRESDIV:8;\r
+ vuint32_t RJW:2;\r
+ vuint32_t PSEG1:3;\r
+ vuint32_t PSEG2:3;\r
+ vuint32_t BOFFMSK:1;\r
+ vuint32_t ERRMSK:1;\r
+ vuint32_t CLKSRC:1;\r
+ vuint32_t LPB:1;\r
+ vuint32_t TWRNMSK:1;\r
+ vuint32_t RWRNMSK:1;\r
+ vuint32_t :2;\r
+ vuint32_t SMP:1;\r
+ vuint32_t BOFFREC:1;\r
+ vuint32_t TSYN:1;\r
+ vuint32_t LBUF:1;\r
+ vuint32_t LOM:1;\r
+ vuint32_t PROPSEG:3;\r
+ } B;\r
+ } CR;\r
+\r
+ union { /* FLEXCAN Free Running Timer (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t TIMER:16;\r
+ } B;\r
+ } TIMER;\r
+\r
+ vuint8_t FLEXCAN_reserved0[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */\r
+\r
+ union { /* FLEXCAN RX Global Mask (Base+0x0010) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RXGMASK;\r
+\r
+ /* --- Following 2 registers are included for legacy purposes only --- */\r
+\r
+ union { /* FLEXCAN RX 14 Mask (Base+0x0014) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RX14MASK;\r
+\r
+ union { /* FLEXCAN RX 15 Mask (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RX15MASK;\r
+\r
+ /* --- */\r
+\r
+ union { /* FLEXCAN Error Counter (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t RXECNT:8;\r
+ vuint32_t TXECNT:8;\r
+ } B;\r
+ } ECR;\r
+\r
+ union { /* FLEXCAN Error & Status (Base+0x0020) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :14;\r
+ vuint32_t TWRNINT:1;\r
+ vuint32_t RWRNINT:1;\r
+ vuint32_t BIT1ERR:1;\r
+ vuint32_t BIT0ERR:1;\r
+ vuint32_t ACKERR:1;\r
+ vuint32_t CRCERR:1;\r
+ vuint32_t FRMERR:1;\r
+ vuint32_t STFERR:1;\r
+ vuint32_t TXWRN:1;\r
+ vuint32_t RXWRN:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t TXRX:1;\r
+ vuint32_t FLTCONF:2;\r
+ vuint32_t :1;\r
+ vuint32_t BOFFINT:1;\r
+ vuint32_t ERRINT:1;\r
+ vuint32_t :1;\r
+ } B;\r
+ } ESR;\r
+\r
+ union { /* FLEXCAN Interruput Masks H (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63M:1;\r
+ vuint32_t BUF62M:1;\r
+ vuint32_t BUF61M:1;\r
+ vuint32_t BUF60M:1;\r
+ vuint32_t BUF59M:1;\r
+ vuint32_t BUF58M:1;\r
+ vuint32_t BUF57M:1;\r
+ vuint32_t BUF56M:1;\r
+ vuint32_t BUF55M:1;\r
+ vuint32_t BUF54M:1;\r
+ vuint32_t BUF53M:1;\r
+ vuint32_t BUF52M:1;\r
+ vuint32_t BUF51M:1;\r
+ vuint32_t BUF50M:1;\r
+ vuint32_t BUF49M:1;\r
+ vuint32_t BUF48M:1;\r
+ vuint32_t BUF47M:1;\r
+ vuint32_t BUF46M:1;\r
+ vuint32_t BUF45M:1;\r
+ vuint32_t BUF44M:1;\r
+ vuint32_t BUF43M:1;\r
+ vuint32_t BUF42M:1;\r
+ vuint32_t BUF41M:1;\r
+ vuint32_t BUF40M:1;\r
+ vuint32_t BUF39M:1;\r
+ vuint32_t BUF38M:1;\r
+ vuint32_t BUF37M:1;\r
+ vuint32_t BUF36M:1;\r
+ vuint32_t BUF35M:1;\r
+ vuint32_t BUF34M:1;\r
+ vuint32_t BUF33M:1;\r
+ vuint32_t BUF32M:1;\r
+ } B;\r
+ } IMRH;\r
+\r
+ union { /* FLEXCAN Interruput Masks L (Base+0x0028) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31M:1;\r
+ vuint32_t BUF30M:1;\r
+ vuint32_t BUF29M:1;\r
+ vuint32_t BUF28M:1;\r
+ vuint32_t BUF27M:1;\r
+ vuint32_t BUF26M:1;\r
+ vuint32_t BUF25M:1;\r
+ vuint32_t BUF24M:1;\r
+ vuint32_t BUF23M:1;\r
+ vuint32_t BUF22M:1;\r
+ vuint32_t BUF21M:1;\r
+ vuint32_t BUF20M:1;\r
+ vuint32_t BUF19M:1;\r
+ vuint32_t BUF18M:1;\r
+ vuint32_t BUF17M:1;\r
+ vuint32_t BUF16M:1;\r
+ vuint32_t BUF15M:1;\r
+ vuint32_t BUF14M:1;\r
+ vuint32_t BUF13M:1;\r
+ vuint32_t BUF12M:1;\r
+ vuint32_t BUF11M:1;\r
+ vuint32_t BUF10M:1;\r
+ vuint32_t BUF09M:1;\r
+ vuint32_t BUF08M:1;\r
+ vuint32_t BUF07M:1;\r
+ vuint32_t BUF06M:1;\r
+ vuint32_t BUF05M:1;\r
+ vuint32_t BUF04M:1;\r
+ vuint32_t BUF03M:1;\r
+ vuint32_t BUF02M:1;\r
+ vuint32_t BUF01M:1;\r
+ vuint32_t BUF00M:1;\r
+ } B;\r
+ } IMRL;\r
+\r
+ union { /* FLEXCAN Interruput Flag H (Base+0x002C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63I:1;\r
+ vuint32_t BUF62I:1;\r
+ vuint32_t BUF61I:1;\r
+ vuint32_t BUF60I:1;\r
+ vuint32_t BUF59I:1;\r
+ vuint32_t BUF58I:1;\r
+ vuint32_t BUF57I:1;\r
+ vuint32_t BUF56I:1;\r
+ vuint32_t BUF55I:1;\r
+ vuint32_t BUF54I:1;\r
+ vuint32_t BUF53I:1;\r
+ vuint32_t BUF52I:1;\r
+ vuint32_t BUF51I:1;\r
+ vuint32_t BUF50I:1;\r
+ vuint32_t BUF49I:1;\r
+ vuint32_t BUF48I:1;\r
+ vuint32_t BUF47I:1;\r
+ vuint32_t BUF46I:1;\r
+ vuint32_t BUF45I:1;\r
+ vuint32_t BUF44I:1;\r
+ vuint32_t BUF43I:1;\r
+ vuint32_t BUF42I:1;\r
+ vuint32_t BUF41I:1;\r
+ vuint32_t BUF40I:1;\r
+ vuint32_t BUF39I:1;\r
+ vuint32_t BUF38I:1;\r
+ vuint32_t BUF37I:1;\r
+ vuint32_t BUF36I:1;\r
+ vuint32_t BUF35I:1;\r
+ vuint32_t BUF34I:1;\r
+ vuint32_t BUF33I:1;\r
+ vuint32_t BUF32I:1;\r
+ } B;\r
+ } IFRH;\r
+\r
+ union { /* FLEXCAN Interruput Flag l (Base+0x0030) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31I:1;\r
+ vuint32_t BUF30I:1;\r
+ vuint32_t BUF29I:1;\r
+ vuint32_t BUF28I:1;\r
+ vuint32_t BUF27I:1;\r
+ vuint32_t BUF26I:1;\r
+ vuint32_t BUF25I:1;\r
+ vuint32_t BUF24I:1;\r
+ vuint32_t BUF23I:1;\r
+ vuint32_t BUF22I:1;\r
+ vuint32_t BUF21I:1;\r
+ vuint32_t BUF20I:1;\r
+ vuint32_t BUF19I:1;\r
+ vuint32_t BUF18I:1;\r
+ vuint32_t BUF17I:1;\r
+ vuint32_t BUF16I:1;\r
+ vuint32_t BUF15I:1;\r
+ vuint32_t BUF14I:1;\r
+ vuint32_t BUF13I:1;\r
+ vuint32_t BUF12I:1;\r
+ vuint32_t BUF11I:1;\r
+ vuint32_t BUF10I:1;\r
+ vuint32_t BUF09I:1;\r
+ vuint32_t BUF08I:1;\r
+ vuint32_t BUF07I:1;\r
+ vuint32_t BUF06I:1;\r
+ vuint32_t BUF05I:1;\r
+ vuint32_t BUF04I:1;\r
+ vuint32_t BUF03I:1;\r
+ vuint32_t BUF02I:1;\r
+ vuint32_t BUF01I:1;\r
+ vuint32_t BUF00I:1;\r
+ } B;\r
+ } IFRL; /* Interruput Flag Register */\r
+\r
+ vuint8_t FLEXCAN_reserved1[76]; /*Reserved 76 bytes (Base+0x0034-0x007F)*/\r
+\r
+/****************************************************************************/\r
+/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */\r
+/****************************************************************************/\r
+ /* Standard Buffer Structure */\r
+ struct FLEXCAN_BUF_t BUF[64];\r
+\r
+ /* RX FIFO and Buffer Structure */\r
+ /*struct FLEXCAN_RXFIFO_t RXFIFO; */\r
+ /*struct FLEXCAN_BUF_t BUF[56]; */\r
+/****************************************************************************/\r
+\r
+ vuint8_t FLEXCAN_reserved2[1024]; /*Reserved 1024 (Base+0x0480-0x087F)*/\r
+\r
+ union { /* FLEXCAN RX Individual Mask (Base+0x0880-0x097F) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RXIMR[64];\r
+\r
+}; /* end of FLEXCAN_tag */\r
+/****************************************************************************/\r
+/* MODULE : DMAMUX (base address - 0xFFFD_C000) */\r
+/****************************************************************************/\r
+ struct DMAMUX_tag {\r
+ union { /* DMAMUX Channel Configuration (Base+0x0000-0x000F) */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ENBL:1;\r
+ vuint8_t TRIG:1;\r
+ vuint8_t SOURCE:6;\r
+ } B;\r
+ } CHCONFIG[16]; \r
+\r
+ }; /* end of DMAMUX_tag */\r
+/****************************************************************************/\r
+/* MODULE : DFLASH (base address - 0x0080_0000) */\r
+/****************************************************************************/\r
+ struct DFLASH_tag {\r
+ union { /* Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EDC:1;\r
+ vuint32_t:4;\r
+ vuint32_t SIZE:3;\r
+ vuint32_t:1;\r
+ vuint32_t LAS:3;\r
+ vuint32_t:3;\r
+ vuint32_t MAS:1;\r
+ vuint32_t EER:1;\r
+ vuint32_t RWE:1;\r
+ vuint32_t:2;\r
+ vuint32_t PEAS:1;\r
+ vuint32_t DONE:1;\r
+ vuint32_t PEG:1;\r
+ vuint32_t:4;\r
+ vuint32_t PGM:1;\r
+ vuint32_t PSUS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t ESUS:1;\r
+ vuint32_t EHV:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* Low/Mid address block locking (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LME:1;\r
+ vuint32_t:10;\r
+ vuint32_t TSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t MLK:2;\r
+ vuint32_t LLK:16;\r
+ } B;\r
+ } LML;\r
+\r
+ union { /* High address block locking (Base+0x0008) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBE:1;\r
+ vuint32_t :25;\r
+ vuint32_t HBLOCK:6;\r
+ } B;\r
+ } HBL;\r
+\r
+ union { /* Secondary Low/mid block locking (Base+0x000C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLE:1;\r
+ vuint32_t:10;\r
+ vuint32_t STSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t SMK:2;\r
+ vuint32_t SLK:16;\r
+ } B;\r
+ } SLL;\r
+\r
+ union { /* Low/Mid address space block sel (Base+0x0010)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MSL:2;\r
+ vuint32_t LSL:16;\r
+ } B;\r
+ } LMS;\r
+\r
+ union { /* High address space block sel (Base+0x0014)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t HSL:6;\r
+ } B;\r
+ } HBS;\r
+\r
+ union { /* Address Register (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:9;\r
+ vuint32_t ADD:20;\r
+ vuint32_t:3;\r
+ } B;\r
+ } ADR;\r
+\r
+ vuint8_t DFLASH_reserved0[32]; /* Reserved 32 Bytes (+0x001C-0x003B) */\r
+\r
+ union { /* User Test 0 (Base+0x003C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t UTE:1;\r
+ vuint32_t:7;\r
+ vuint32_t DSI:8;\r
+ vuint32_t:10;\r
+ vuint32_t MRE:1;\r
+ vuint32_t MRV:1;\r
+ vuint32_t EIE:1;\r
+ vuint32_t AIS:1;\r
+ vuint32_t AIE:1;\r
+ vuint32_t AID:1;\r
+ } B;\r
+ } UT0;\r
+\r
+ union { /* User Test 1 (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT1;\r
+\r
+ union { /* User Test 2 (Base+0x0044) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT2;\r
+\r
+ union { /* User Multiple Input sig 0..1 (+0x0048-0x004F)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MS:32;\r
+ } B;\r
+ } UMISR[5];\r
+\r
+ }; /* end of Dflash_tag */\r
+/****************************************************************************/\r
+/* MODULE : CFLASH (base address - 0xC3F8_8000) */\r
+/****************************************************************************/\r
+ struct CFLASH_tag {\r
+ union { /* Module Configuration (Base+0x0000) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EDC:1;\r
+ vuint32_t:4;\r
+ vuint32_t SIZE:3;\r
+ vuint32_t:1;\r
+ vuint32_t LAS:3;\r
+ vuint32_t:3;\r
+ vuint32_t MAS:1;\r
+ vuint32_t EER:1;\r
+ vuint32_t RWE:1;\r
+ vuint32_t:1;\r
+ vuint32_t:1;\r
+ vuint32_t PEAS:1;\r
+ vuint32_t DONE:1;\r
+ vuint32_t PEG:1;\r
+ vuint32_t:4;\r
+ vuint32_t PGM:1;\r
+ vuint32_t PSUS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t ESUS:1;\r
+ vuint32_t EHV:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* Low/Mid address block locking (Base+0x0004) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LME:1;\r
+ vuint32_t:10;\r
+ vuint32_t TSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t MLK:2;\r
+ vuint32_t LLK:16;\r
+ } B;\r
+ } LML;\r
+\r
+ union { /* High address space block locking (Base+0x0008)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBE:1;\r
+ vuint32_t :19;\r
+ vuint32_t HBLOCK:12;\r
+ } B;\r
+ } HBL;\r
+\r
+ union { /* Secondary Low/Mid block lock (Base+0x000C)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLE:1;\r
+ vuint32_t:10;\r
+ vuint32_t STSLK:1;\r
+ vuint32_t:2;\r
+ vuint32_t SMK:2;\r
+ vuint32_t SLK:16;\r
+ } B;\r
+ } SLL;\r
+\r
+ union { /* Low/Mid address space block sel (Base+0x0010)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MSL:2;\r
+ vuint32_t LSL:16;\r
+ } B;\r
+ } LMS;\r
+\r
+ union { /* High address Space block select (Base+0x0014)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:20;\r
+ vuint32_t HSL:12;\r
+ } B;\r
+ } HBS;\r
+\r
+ union { /* Address Register (Base+0x0018) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:9;\r
+ vuint32_t ADD:20;\r
+ vuint32_t:3;\r
+ } B;\r
+ } ADR;\r
+\r
+ /* Note the following 3 registers, BIU[0..2] are mirrored to */\r
+ /* the code flash configuraiton PFCR[0..2] registers */\r
+ /* To make it easier to code, the BIU registers have been */\r
+ /* replaced with the PFCR registers in this header file! */\r
+ /* A commented out BIU register is shown for reference! */\r
+\r
+\r
+ union { /* CFLASH Configuration 0 (Base+0x001C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BK0_APC:5;\r
+ vuint32_t BK0_WWSC:5;\r
+ vuint32_t BK0_RWSC:5;\r
+ vuint32_t BK0_RWWC2:1;\r
+ vuint32_t BK0_RWWC1:1;\r
+ /* vuint32_t B0_P1_BCFG:2; // only has one port to the cross bar i.e. port 0 \r
+ vuint32_t B0_P1_DPFE:1;\r
+ vuint32_t B0_P1_IPFE:1;\r
+ vuint32_t B0_P1_PFLM:2;\r
+ vuint32_t B0_P1_BFE:1; */\r
+ vuint32_t :7;\r
+ vuint32_t BK0_RWWC0:1;\r
+ vuint32_t B0_P0_BCFG:2;\r
+ vuint32_t B0_P0_DPFE:1;\r
+ vuint32_t B0_P0_IPFE:1;\r
+ vuint32_t B0_P0_PFLM:2;\r
+ vuint32_t B0_P0_BFE:1;\r
+ } B;\r
+ } PFCR0;\r
+ \r
+/* Commented out Bus Interface Unit 0 (Base+0x001C) */\r
+ /*union { \r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BI0:32;\r
+ } B;\r
+ } BIU0; */\r
+\r
+ union { /* CFLASH Configuration Register 1 (Base+0x0020)*/\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BK1_APC:5;\r
+ vuint32_t BK1_WWSC:5;\r
+ vuint32_t BK1_RWSC:5;\r
+ vuint32_t BK1_RWWC2:1;\r
+ vuint32_t BK1_RWWC1:1;\r
+ vuint32_t:7; /* changed to 7 to suit comment below */\r
+ //vuint32_t B1_P1_BFE:1; /* should have no effect, there is only one XBAR port (no P1) to P-flash controller */ \r
+ vuint32_t BK1_RWWC0:1;\r
+ vuint32_t:6;\r
+ vuint32_t B1_P0_BFE:1;\r
+ } B;\r
+ } PFCR1;\r
+ \r
+/* Commented out Bus Interface Unit 1 (Base+0x0020) */\r
+ /*union { \r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BI1:32;\r
+ } B;\r
+ } BIU1; */\r
+\r
+ union { /* CFLASH Access Protection (Base+0x0024) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6; /*incorrect - B1M/B1.5M does not have this many masters TBD*/ \r
+ vuint32_t ARBM:2;\r
+ vuint32_t M7PFD:1;\r
+ vuint32_t M6PFD:1;\r
+ vuint32_t M5PFD:1;\r
+ vuint32_t M4PFD:1;\r
+ vuint32_t M3PFD:1;\r
+ vuint32_t M2PFD:1;\r
+ vuint32_t M1PFD:1;\r
+ vuint32_t M0PFD:1;\r
+ vuint32_t M7AP:2;\r
+ vuint32_t M6AP:2;\r
+ vuint32_t M5AP:2;\r
+ vuint32_t M4AP:2;\r
+ vuint32_t M3AP:2;\r
+ vuint32_t M2AP:2;\r
+ vuint32_t M1AP:2;\r
+ vuint32_t M0AP:2;\r
+ } B;\r
+ } PFAPR;\r
+ \r
+/* Commented out Bus Interface Unit 2 (Base+0x0024) */\r
+ /*union { \r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BI2:32;\r
+ } B;\r
+ } BIU2; */\r
+\r
+ vuint8_t CFLASH_reserved0[20]; /* Reserved 20 Bytes (Base+0x0028-0x003B) */\r
+\r
+ union { /* User Test 0 (Base+0x003C) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t UTE:1;\r
+ vuint32_t:7;\r
+ vuint32_t DSI:8;\r
+ vuint32_t:10;\r
+ vuint32_t MRE:1;\r
+ vuint32_t MRV:1;\r
+ vuint32_t EIE:1;\r
+ vuint32_t AIS:1;\r
+ vuint32_t AIE:1;\r
+ vuint32_t AID:1;\r
+ } B;\r
+ } UT0;\r
+\r
+ union { /* User Test 1 (Base+0x0040) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT1;\r
+\r
+ union { /* User Test 2 (Base+0x0044) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DAI:32;\r
+ } B;\r
+ } UT2;\r
+\r
+ union { /* User Multiple Input Sig 0..4 (Base+0x0048-0x005B) */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MS:32;\r
+ } B;\r
+ } UMISR[5];\r
+ \r
+ vuint8_t CFLASH_reserved1[16292]; /* Reserved 16292 (Base+0x005C-0x3FFF)*/\r
+\r
+ }; /* end of CFLASH_tag */\r
+/****************************************************************** \r
+| defines and macros (scope: module-local) \r
+|-----------------------------------------------------------------*/\r
+/* Define instances of modules */\r
+\r
+#define ADC_0 (*(volatile struct ADC0_tag *) 0xFFE00000UL)\r
+#define ADC_1 (*(volatile struct ADC1_tag *) 0xFFE04000UL)\r
+#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)\r
+#define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)\r
+#define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)\r
+#define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)\r
+#define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)\r
+#define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)\r
+#define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL)\r
+#define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL)\r
+#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)\r
+#define CTUL (*(volatile struct CTUL_tag *) 0xFFE64000UL)\r
+#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)\r
+#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)\r
+#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)\r
+#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)\r
+#define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL)\r
+#define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL)\r
+#define DSPI_4 (*(volatile struct DSPI_tag *) 0xFFFA0000UL)\r
+#define DSPI_5 (*(volatile struct DSPI_tag *) 0xFFFA4000UL)\r
+#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) \r
+#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)\r
+#define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL)\r
+#define I2C_0 (*(volatile struct I2C_tag *) 0xFFE30000UL)\r
+#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)\r
+#define LINFLEX_0 (*(volatile struct LINFLEXD0_tag *) 0xFFE40000UL)\r
+#define LINFLEX_1 (*(volatile struct LINFLEXD1_tag *) 0xFFE44000UL)\r
+#define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL)\r
+#define LINFLEX_3 (*(volatile struct LINFLEX_tag *) 0xFFE4C000UL)\r
+#define LINFLEX_4 (*(volatile struct LINFLEX_tag *) 0xFFE50000UL)\r
+#define LINFLEX_5 (*(volatile struct LINFLEX_tag *) 0xFFE54000UL)\r
+#define LINFLEX_6 (*(volatile struct LINFLEX_tag *) 0xFFE58000UL)\r
+#define LINFLEX_7 (*(volatile struct LINFLEX_tag *) 0xFFE5C000UL)\r
+#define LINFLEX_8 (*(volatile struct LINFLEX_tag *) 0xFFFB0000UL)\r
+#define LINFLEX_9 (*(volatile struct LINFLEX_tag *) 0xFFFB4000UL)\r
+#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)\r
+#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)\r
+#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)\r
+#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)\r
+#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)\r
+#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)\r
+#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)\r
+#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)\r
+#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)\r
+#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)\r
+#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)\r
+#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)\r
+\r
+#ifdef __MWERKS__\r
+#pragma pop\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif \r
+/* End of file */\r
.name = "MPC5604B",\r
.pvr = CORE_PVR_E200Z0H,\r
},\r
+#elif defined(CFG_MPC5606B)\r
+ {\r
+ .name = "MPC5606B",\r
+ .pvr = CORE_PVR_E200Z0H,\r
+ },\r
#elif defined(CFG_MPC5606S)\r
{\r
.name = "MPC5606S",\r
.name = "MPC5604B",\r
.pvr = CORE_PVR_E200Z0H,\r
},\r
+#elif defined(CFG_MPC5606B)\r
+ {\r
+ .name = "MPC5606B",\r
+ .pvr = CORE_PVR_E200Z0H,\r
+ },\r
#elif defined(CFG_MPC5606S)\r
{\r
.name = "MPC5606S",\r
FMPLL.ESYNCR2.B.ERFD = clockSettingsPtr->Pll3;\r
// Connect SYSCLK to FMPLL\r
SIU.SYSCLK.B.SYSCLKSEL = SYSCLOCK_SELECT_PLL;\r
-#elif defined(CFG_MPC5604B)\r
+#elif defined(CFG_MPC5604B) || defined(CFG_MPC5606B)\r
// Write pll parameters.\r
CGM.FMPLL_CR.B.IDF = clockSettingsPtr->Pll1;\r
CGM.FMPLL_CR.B.NDIV = clockSettingsPtr->Pll2;\r
ME.PCTL[4].R = 0x01; /* MPC56xxB/P/S DSPI0 */\r
ME.PCTL[5].R = 0x01; /* MPC56xxB/P/S DSPI1: */\r
ME.PCTL[32].R = 0x01; //ADC0 control\r
+#if defined(CFG_MPC5606B)\r
+ ME.PCTL[33].R = 0x01; //ADC1 control\r
+#endif\r
ME.PCTL[23].R = 0x01; //DMAMUX control\r
ME.PCTL[48].R = 0x01; /* MPC56xxB/P/S LINFlex */\r
ME.PCTL[49].R = 0x01; /* MPC56xxB/P/S LINFlex */\r
while(ME.GS.B.S_CURRENTMODE != 4) {}\r
\r
CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
- CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
- CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
+ CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */\r
+ CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */\r
\r
SIU.PSMI[0].R = 0x01; /* CAN1RX on PCR43 */\r
SIU.PSMI[6].R = 0x01; /* CS0/DSPI_0 on PCR15 */\r
while(ME.GS.B.S_CURRENTMODE != 4) {}\r
\r
CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
- CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
- CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
+ CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */\r
+ CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */\r
\r
#elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
// Partially following the steps in MPC5567 RM..\r
void Mcu_DistributePllClock(void)\r
{\r
VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_UNINIT );\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
VALIDATE( ( CGM.FMPLL_CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );\r
#elif defined(CFG_MPC5606S)\r
VALIDATE( ( CGM.FMPLL[0].CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );\r
\r
if( !SIMULATOR() )\r
{\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
if ( !CGM.FMPLL_CR.B.S_LOCK )\r
{\r
rv = MCU_PLL_UNLOCKED;\r
uint32_t eprediv = FMPLL.SYNCR.B.PREDIV;\r
uint32_t emfd = FMPLL.SYNCR.B.MFD;\r
uint32_t erfd = FMPLL.SYNCR.B.RFD;\r
-#elif defined(CFG_MPC5604B)\r
+#elif defined(CFG_MPC560XB)\r
uint32_t eprediv = CGM.FMPLL_CR.B.IDF;\r
uint32_t emfd = CGM.FMPLL_CR.B.NDIV;\r
uint32_t erfd = CGM.FMPLL_CR.B.ODF;\r
#if defined(CFG_MPC560X)\r
case PERIPHERAL_CLOCK_LIN_A:\r
case PERIPHERAL_CLOCK_LIN_B:\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
case PERIPHERAL_CLOCK_LIN_C:\r
case PERIPHERAL_CLOCK_LIN_D:\r
#endif\r
SIU.PCR[i].R = configType->padConfig[i];\r
++i;\r
\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
if(32 == i || 33 == i) i=34;\r
if(121 == i || 122 == i) i=123;\r
#elif defined(CFG_MPC5606S)\r
Irq_Restore(state); // Restore interrupts\r
pcrPtr++;\r
padCfgPtr++;\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
if(32 == i)\r
{\r
i=34;\r
#include "arc.h"\r
#endif\r
\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
#define PWM_RUNTIME_CHANNEL_COUNT 56\r
#define CHANNELS_OK (Channel <= PWM_MAX_CHANNEL-1)\r
#elif defined(CFG_MPC5606S)\r
return;\r
}\r
\r
- #if defined(CFG_MPC5606S) && !defined(CFG_MPC5604B)\r
+ #if defined(CFG_MPC5606S) && !defined(CFG_MPC560XB)\r
CGM.AC1_SC.R = 0x03000000; /* MPC56xxS: Select aux. set 1 clock to be FMPLL0 */\r
CGM.AC2_SC.R = 0x03000000; /* MPC56xxS: Select aux. set 2 clock to be FMPLL0 */\r
#endif\r
// Pwm_DisableNotification(channel);\r
\r
// Install ISR\r
- #if defined(CFG_MPC5604B)\r
+ #if defined(CFG_MPC560XB)\r
switch(channel)\r
{\r
case 0:\r
\r
#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC5567)\r
#define SPI_CONTROLLER_TOTAL_CNT 4\r
-#elif defined(CFG_MPC5604B)\r
+#elif defined(CFG_MPC560XB)\r
#define SPI_CONTROLLER_TOTAL_CNT 3\r
#elif defined(CFG_MPC560X)\r
#define SPI_CONTROLLER_TOTAL_CNT 2\r
#if defined(CFG_MPC560X)\r
#define DSPI_A_ISR_EOQF DSPI_0_ISR_EOQF\r
#define DSPI_B_ISR_EOQF DSPI_1_ISR_EOQF\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
#define DSPI_C_ISR_EOQF DSPI_2_ISR_EOQF\r
#endif\r
#endif\r
#define SPIE_OK 0\r
#define SPIE_JOB_NOT_DONE 1\r
\r
-#if defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC560XB)\r
#define CTAR_CNT 6\r
#else\r
#define CTAR_CNT 8\r
PIT_INT1, // 5606-60\r
PIT_INT2, // 5606-61\r
\r
- ADC_EOC_INT, // 5606-62\r
- ADC_ER_INT, // 5606-63\r
- ADC_WD_INT, // 5606-64\r
+ ADC0_EOC_INT, // 5606-62\r
+ ADC0_ER_INT, // 5606-63\r
+ ADC0_WD_INT, // 5606-64\r
\r
FLEXCAN_0_ESR_ERR_INT, // 5606-65\r
FLEXCAN_0_ESR_BOFF_INT, // 5606-66\r
LINFLEX_0_TXI, // 5606-80\r
LINFLEX_0_ERR, // 5606-81\r
\r
- RESERVED14, // 5606-82\r
- RESERVED15, // 5606-83\r
- RESERVED16, // 5606-84\r
+ ADC1_EOC_INT, // 5606-82\r
+ ADC1_ER_INT, // 5606-83\r
+ ADC1_WD_INT, // 5606-84\r
\r
FLEXCAN_1_ESR_ERR_INT, // 5606-85\r
FLEXCAN_1_ESR_BOFF_INT, // 5606-86\r
RESERVED51, // 5606-138\r
RESERVED52, // 5606-139\r
RESERVED53, // 5606-140\r
-#if defined (CFG_MPC5604B)\r
+#if defined (CFG_MPC560XB)\r
EMIOS_0_GFR_F0_F1, // 5606-141\r
EMIOS_0_GFR_F2_F3, // 5606-142\r
EMIOS_0_GFR_F4_F5, // 5606-143\r
ARCH_MCU=mpc5604b\r
\r
# CFG (y/n) macros\r
-CFG=PPC E200Z0 MPC55XX MPC560X MPC5604B BRD_MPC5604B_TRK VLE\r
+CFG=PPC E200Z0 MPC55XX MPC560X MPC560XB MPC5604B BRD_MPC5604B_TRK VLE\r
\r
# What buildable modules does this board have, \r
# default or private\r
--- /dev/null
+\r
+\r
+\r
+The Freescale MPC5606S is an PowerPC process with a e200Z0h core, VLE only \r
+ \r
+Datasheets:\r
+ Eval board:\r
+ http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=XPC560SKIT \r
+ http://cache.freescale.com/files/microcontrollers/hardware_tools/schematics/XPC560SADPT176SSCH.pdf?fpsp=1\r
+ http://cache.freescale.com/files/32bit/doc/user_guide/XPC560SEVBUM.pdf?fpsp=1\r
+ Mainboard schematic\r
+ http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC560xB_EVB&parentCode=XPC56xxMB&fpsp=1&nodeId=01624606C1427E\r
+ \r
+ MPC560x\r
+ http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC560xS&fsrch=1&sr=1\r
+\r
+Board:\r
+ 8Mhz external crystal\r
+\r
+Supported compilers:\r
+ Code Warrior\r
+ \r
+Info: \r
+ MPC5606S\r
+ CPU: e200z0h (VLE only)\r
+ Freq: 64 Mhz\r
+ Flash: 1.0 MB, primary\r
+ 64K, data flash\r
+ RAM: 48K, ECC\r
+ 160K, Graphics RAM (not ECC)\r
+ \r
+Memory Map:\r
+ 0x0000_0000 -> 0x000f_ffff Flash\r
+ 0x0080_0000 -> 0x0080_ffff Data Flash\r
+ 0x4000_0000 -> 0x4000_bfff SRAM\r
+ 0x6000_0000 -> 0x6002_7fff Graphics SRAM\r
+ \r
+ \r
+\r
+== SPI == \r
+\r
+Adding a SPI EEPROM (Microship 25LC160B)\r
+\r
+To the left are the pins as they are names in XPC56xxMBSCH (schema for the main board, page 11 of 12) \r
+\r
+<- XPC560S ->#<---------------------- MCU --->\r
+ # PAD Func \r
+----------------------------------------------\r
+SINB,PJ1-7 # PB[7] 23 1 SIN_0 \r
+SOUTB,PJ1-8 # PB[8] 24 1 SOUT_0 \r
+SCKB,PJ1-9 # PB[9] 25 1 SCK_0 \r
+PCSB1,PJ1-11 # PB[13] 29 3 PCS1_0 \r
+\r
+PCSB2,PJ1-12 # PB[12] 28 3 PCS2_0 NOT USED\r
+PCSB0,PJ1-10 # PH[4] 103 1 PCS0_0 NOT USED\r
+\r
+SPI MEMORY \r
+ 25LC160B\r
+ CS - Connect to PJ1-11\r
+ /WP - High\r
+ /HOLD - Low\r
+ Rest of the pins are obvious\r
+ \r
+ Connected with 5V logic\r
+\r
+---------------------------------- NOTE ----------------------------------\r
+ The xPC560S EVB v1.0.1 manual is total crap in chapter "3.8 Pin Mapping"\r
+ Known errors:\r
+ PJ1\r
+ PCS0.2, should be PCS1_0 \r
+ PJ9-Port F\r
+ As I understand it should map to Port F. However, PCS1_1 is\r
+ located on PCR[78]=PF[8] on CPU is connected to PF[0] on PJ9!! \r
+---------------------------------- NOTE ---------------------------------- \r
+ \r
+SPI_0\r
+ PJ1 Connector will have the following layout \r
+ (With ArcCore internal harness and SO/SI as seen from memory):\r
+\r
+ PJ1 \r
+ 1-X X-2\r
+ 3-X X-4 \r
+ 5-X X-6\r
+ SO/Brown 7-X X-8 SI/Orange\r
+ SCK/Blue 9-X X-10 \r
+ CS/Green 11-X X-12\r
+ 13-X X-14\r
+ 15-X X-16 \r
+ Gnd/Black 17-X X-18 VCC/Red \r
+ \r
+ \r
+ If software CS is used Connector PJ2 and PJ[0] is used for that\r
+ PJ2 \r
+ CS and PJ[0] 1-X X-2\r
+ 3-X X-4 \r
+ ... \r
+\r
+\r
+SPI_1\r
+\r
+ PCR[20]/PB[4]/SCK_1\r
+ PCR[21]/PB[5]/SOUT_1\r
+ PCR[22]/PB[6]/SIN_1\r
+\r
+ PJ5 \r
+ 1-X X-2\r
+ 3-X X-4\r
+ SCK/Blue 5-X X-6 SI/Orange\r
+ SO/Brown 7-X X-8 \r
+ 9-X X-10 \r
+ 11-X X-12\r
+ 13-X X-14\r
+ 15-X X-16 \r
+ Gnd/Black 17-X X-18 VCC/Red \r
+\r
+ PJ9\r
+ CS/Green (See NOTE)\r
+ | \r
+ ... 6 4 2 0\r
+ 7 5 3 1\r
+\r
+\r
+\r
+\r
+\r
+ \r
+ \r
+ \r
+\r
--- /dev/null
+\r
+# ARCH defines\r
+ARCH=mpc55xx\r
+ARCH_FAM=ppc\r
+ARCH_MCU=mpc5606b\r
+\r
+# CFG (y/n) macros\r
+CFG=PPC E200Z0 MPC55XX MPC560X MPC560XB MPC5606B BRD_MPC560X_XPC560S VLE\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+\r
+# Memory + Peripherals\r
+MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG NVM MEMIF FEE FLS SPI EEP EA\r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=LINIF CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM WDGIF RTE J1939TP\r
+# Network management\r
+MOD_AVAIL+=COMM NM CANNM CANSM LINSM\r
+# Additional\r
+MOD_AVAIL+= RAMLOG \r
+# CRC\r
+MOD_AVAIL+=CRC32 CRC16\r
+# Required modules\r
+MOD_USE += MCU KERNEL ECUM DET\r
+\r
+# Default cross compiler\r
+COMPILER?=cw\r
+DEFAULT_CROSS_COMPILE = /opt/powerpc-eabispe/bin/powerpc-eabispe-\r
+DEFAULT_CW_COMPILE= /opt/cw\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Dma.h"\r
+\r
+const Dma_MuxConfigType DmaMuxConfig [DMA_NUMBER_OF_CHANNELS] =\r
+{
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_TX\r
+ },\r
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_RX\r
+ },\r
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_TX\r
+ },\r
+ {
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_RX
+ },
+ {
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_ADC
+ }
+};\r
+\r
+const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =\r
+{
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_A_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_A_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
+ },
+ {
+ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
+ }
+};\r
+\r
+\r
+const Dma_ConfigType DmaConfig []=\r
+{
+ {
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S)\r
+ DmaMuxConfig,
+#endif
+ DmaChannelConfig,
+ DMA_FIXED_PRIORITY_ARBITRATION
+ }
+};\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DMA_CFG_H_\r
+#define DMA_CFG_H_\r
+\r
+typedef enum\r
+{
+ DMA_DSPI_A_COMMAND_CHANNEL,\r
+ DMA_DSPI_A_RESULT_CHANNEL,\r
+ DMA_DSPI_B_COMMAND_CHANNEL,\r
+ DMA_DSPI_B_RESULT_CHANNEL,\r
+
+ DMA_ADC_GROUP0_RESULT_CHANNEL,
+
+ DMA_NUMBER_OF_CHANNELS\r
+} Dma_ChannelType;\r
+\r
+#endif /* DMA_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#ifndef EEP_CFG_H_
+#define EEP_CFG_H_
+
+
+#define EEP_USES_EXTERNAL_DRIVER
+
+#include "Spi.h"
+#include "Eep_ConfigTypes.h"
+
+
+// M95256 or 25LC160B
+#define E2_WREN 0x6 // Write Enable 0000 0110
+#define E2_WRDI 0x4 // Write Disable 0000 0100
+#define E2_RDSR 0x5 // Read Status Register 0000 0101
+ // 1 - Read data
+#define E2_WRSR 0x1 // Write Status Register 0000 0001
+ // 1 - Write data
+#define E2_READ 0x3 // Read from Memory Array 0000 0011
+ // 1 - Write 16-bit address
+ // n - 8 -bit read data
+#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
+ // 1 Write 16-bit address
+ // n - 8-bit reads
+
+/* EepGeneral */
+
+// Switches to activate or deactivate interrupt controlled job processing. true:
+// Interrupt controlled job processing enabled. false: Interrupt controlled job
+// processing disabled.
+#define EEP_USE_INTERRUPTS STD_OFF
+
+// Pre-processor switch to enable and disable development error detection.
+// true: Development error detection enabled. false: Development error
+// detection disabled.
+#define EEP_DEV_ERROR_DETECT STD_ON
+
+// Pre-processor switch to enable / disable the API to read out the modules
+// version information. true: Version info API enabled. false: Version info API
+// disabled.
+#define EEP_VERSION_INFO_API STD_ON
+
+// ndex of the driver, used by EA.
+#define EEP_DRIVER_INDEX 1
+
+// Switches to activate or deactivate write cycle reduction (EEPROM value is
+// read and compared before being overwritten). true: Write cycle reduction
+// enabled. false: Write cycle reduction disabled.
+#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
+
+// Container for runtime configuration parameters of the EEPROM driver.
+// Implementation Type: Eep_ConfigType.
+
+/* EepPublishedInformation
+ */
+
+// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
+#define EEP_TOTAL_SIZE TBD
+
+// Size of smallest erasable EEPROM data unit in bytes.
+#define EEP_ERASE_UNIT_SIZE TBD
+
+// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
+// Minimum expected size of Eep_LengthType.
+#define EEP_MINIMUM_LENGTH_TYPE TBD
+
+// Minimum expected size of Eep_AddressType.
+#define EEP_MINIMUM_ADDRESS_TYPE TBD
+
+// Size of smallest writable EEPROM data unit in bytes.
+#define EEP_WRITE_UNIT_SIZE TBD
+
+// Value of an erased EEPROM cell.
+#define EEP_ERASE_VALUE 0
+
+// Number of erase cycles specified for the EEP device (usually given in the
+// device data sheet).
+#define EEP_SPECIFIED_ERASE_CYCLES TBD
+
+// Size of smallest readable EEPROM data unit in bytes.
+#define EEP_READ_UNIT_SIZE TBD
+
+// Time for writing one EEPROM data unit.(float)
+#define EEP_WRITE_TIME TBD
+
+// Time for erasing one EEPROM data unit (float)
+#define EEP_ERASE_TIME TBD
+
+// Specified maximum number of write cycles under worst case conditions of
+// specific EEPROM hardware (e.g. +90°C)
+#define EEP_ALLOWED_WRITE_CYCLES x
+
+
+extern const Eep_ConfigType EepConfigData[];
+
+#define EEP_DEFAULT_CONFIG EepConfigData[0]
+
+#endif /*EEP_CFG_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+/* Configured for:
+ * Microchip 25LC160B (32 bytes pages)
+ */
+
+
+#include "Eep.h"
+#include "Spi.h"
+#include "debug.h"
+
+#define E2_M9525 1
+#define E2_25LC160B 2
+
+#define E2_CHIP E2_25LC160B
+
+
+static void _JobEndNotify(){
+ DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
+}
+static void _JobErrorNotify(){
+ DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
+}
+
+/*
+ * TODO: probably better to
+ */
+#define SPI_SEQ_EEP_CMD SPI_SEQ_CMD
+#define SPI_SEQ_EEP_CMD2 SPI_SEQ_CMD2
+#define SPI_SEQ_EEP_READ SPI_SEQ_READ
+#define SPI_SEQ_EEP_WRITE SPI_SEQ_WRITE
+
+#define SPI_CH_EEP_CMD SPI_CH_CMD
+#define SPI_CH_EEP_ADDR SPI_CH_ADDR
+#define SPI_CH_EEP_WREN SPI_CH_WREN
+#define SPI_CH_EEP_DATA SPI_CH_DATA
+
+
+const Eep_ExternalDriverType EepExternalDriver = {
+ // READ and WRITE sequences and ID's defined in Spi_Cfg.h
+ .EepCmdSequence = SPI_SEQ_EEP_CMD,
+ .EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
+ .EepReadSequence = SPI_SEQ_EEP_READ,
+ .EepWriteSequence = SPI_SEQ_EEP_WRITE,
+
+ // Jobs may be left out..
+
+ // Channels used
+ .EepCmdChannel = SPI_CH_EEP_CMD,
+ .EepAddrChannel = SPI_CH_EEP_ADDR,
+ .EepWrenChannel = SPI_CH_EEP_WREN,
+ .EepDataChannel = SPI_CH_EEP_DATA,
+};
+
+
+
+const Eep_ConfigType EepConfigData[] = {
+ {
+ // call cycle of the job processing function during write/erase operations. Unit: [s]
+// .EepJobCallCycle = 0.2,
+ // This parameter is the EEPROM device base address.
+ .EepBaseAddress = 0,
+
+ // This parameter is the default EEPROM device mode after initialization.
+ .EepDefaultMode = MEMIF_MODE_FAST,
+
+#if (E2_CHIP == E2_25LC160B)
+ // This parameter is the number of bytes read within one job processing cycle in fast mode
+ .EepFastReadBlockSize = 32,
+ // This parameter is the number of bytes written within one job processing cycle in fast mode
+ .EepFastWriteBlockSize = 32,
+#elif (E2_CHIP == E2_M9525)
+ .EepFastReadBlockSize = 64,
+ .EepFastWriteBlockSize = 64,
+#endif
+ // This parameter is a reference to a callback function for positive job result
+ .Eep_JobEndNotification = &_JobEndNotify,
+
+ // This parameter is a reference to a callback function for negative job result
+ .Eep_JobErrorNotification = &_JobErrorNotify,
+
+ .EepNormalReadBlockSize = 4,
+
+ // Number of bytes written within one job processing cycle in normal mode.
+ .EepNormalWriteBlockSize = 1,
+
+ // This parameter is the used size of EEPROM device in bytes.
+ .EepSize = 0x1000, /* 32K bit for M9525, 16K bit 25LC160B*/
+#if (E2_CHIP == E2_25LC160B)
+ .EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
+#elif (E2_CHIP == E2_M9525)
+ .EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
+#endif
+
+ .externalDriver = &EepExternalDriver,
+ }
+};
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "Fls.h"\r
+#include "flash.h"\r
+#include <stdlib.h>\r
+\r
+\r
+#if defined(CFG_MPC5606S)\r
+\r
+/* TODO: This can actually be read from the flash instead */\r
+const FlashType flashInfo[] = {\r
+ /* NO RWW */\r
+\r
+ /* Bank 0, Array 0 (LOW) */\r
+ [0].sectCnt = 8,\r
+ [0].bankSize = 0x80000,\r
+// [0].bankRange = BANK_RANGE_CODE_LOW,\r
+ [0].regBase = 0xC3F88000UL,\r
+ [0].sectAddr[0] = 0, /* 0, B0F0, LOW */\r
+ [0].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,\r
+ [0].sectAddr[1] = 0x08000, /* 1, B0F1, LOW */\r
+ [0].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,\r
+ [0].sectAddr[2] = 0x0c000, /* 2, B0F2, LOW */\r
+ [0].addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,\r
+ [0].sectAddr[3] = 0x10000, /* 3, B0F3, LOW */\r
+ [0].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,\r
+ [0].sectAddr[4] = 0x18000, /* 4, B0F4, LOW */\r
+ [0].addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4,\r
+ [0].sectAddr[5] = 0x20000, /* 5, B0F5, LOW */\r
+ [0].addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5,\r
+ [0].sectAddr[6] = 0x40000, /* 6, B0F6, MID */\r
+ [0].addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,\r
+ [0].sectAddr[7] = 0x60000, /* 7, B0F7, MID */\r
+ [0].addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,\r
+ [0].sectAddr[8] = 0x80000, /* End, NOT a sector */\r
+\r
+ /* Bank 1, Data */\r
+ [1].sectCnt = 4,\r
+ [1].bankSize = 0x810000 - 0x800000,\r
+ [1].regBase = 0xC3F8C000UL,\r
+ [1].sectAddr[0] = 0x800000, /* LOW */\r
+ [1].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,\r
+ [1].sectAddr[1] = 0x804000, /* LOW */\r
+ [1].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,\r
+ [1].sectAddr[2] = 0x808000, /* LOW */\r
+ [1].addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,\r
+ [1].sectAddr[3] = 0x80c000, /* LOW */\r
+ [1].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,\r
+ [1].sectAddr[4] = 0x810000, /* End, NOT a sector */\r
+\r
+ /* Bank 2, Array 1 (MID)*/\r
+ [2].sectCnt = 4,\r
+ [2].bankSize = 0x100000-0x80000,\r
+ [2].regBase = 0xC3FB0000UL,\r
+ [2].sectAddr[0] = 0x80000, /* 0, B2F0, LOW */\r
+ [2].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,\r
+ [2].sectAddr[1] = 0xa0000, /* 1, B2F1, LOW */\r
+ [2].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,\r
+ [2].sectAddr[2] = 0xc0000, /* 2, B2F2, MID */\r
+ [2].addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,\r
+ [2].sectAddr[3] = 0xe0000, /* 3, B2F3, MID */\r
+ [2].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,\r
+ [2].sectAddr[4] = 0x100000, /* End, NOT a sector */\r
+};\r
+#else if defined(CFG_MPC5606B)\r
+\r
+/* TODO: This can actually be read from the flash instead */\r
+const FlashType flashInfo[] = {\r
+ /* NO RWW */\r
+\r
+ /* Bank 0, Array 0 (LOW) */\r
+ [0].sectCnt = 8,\r
+ [0].bankSize = 0x80000,\r
+// [0].bankRange = BANK_RANGE_CODE_LOW,\r
+ [0].regBase = 0xC3F88000UL,\r
+ [0].sectAddr[0] = 0, /* 0, B0F0, LOW */\r
+ [0].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,\r
+ [0].sectAddr[1] = 0x08000, /* 1, B0F1, LOW */\r
+ [0].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,\r
+ [0].sectAddr[2] = 0x0c000, /* 2, B0F2, LOW */\r
+ [0].addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,\r
+ [0].sectAddr[3] = 0x10000, /* 3, B0F3, LOW */\r
+ [0].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,\r
+ [0].sectAddr[4] = 0x18000, /* 4, B0F4, LOW */\r
+ [0].addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4,\r
+ [0].sectAddr[5] = 0x20000, /* 5, B0F5, LOW */\r
+ [0].addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5,\r
+ [0].sectAddr[6] = 0x40000, /* 6, B0F6, MID */\r
+ [0].addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,\r
+ [0].sectAddr[7] = 0x60000, /* 7, B0F7, MID */\r
+ [0].addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,\r
+ [0].sectAddr[8] = 0x80000, /* End, NOT a sector */\r
+\r
+ /* Bank 1, Data */\r
+ [1].sectCnt = 4,\r
+ [1].bankSize = 0x810000 - 0x800000,\r
+ [1].regBase = 0xC3F8C000UL,\r
+ [1].sectAddr[0] = 0x800000, /* LOW */\r
+ [1].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,\r
+ [1].sectAddr[1] = 0x804000, /* LOW */\r
+ [1].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,\r
+ [1].sectAddr[2] = 0x808000, /* LOW */\r
+ [1].addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,\r
+ [1].sectAddr[3] = 0x80c000, /* LOW */\r
+ [1].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,\r
+ [1].sectAddr[4] = 0x810000, /* End, NOT a sector */\r
+};\r
+\r
+#else\r
+#error CPU NOT supported\r
+#endif\r
+\r
+\r
+const Fls_ConfigType FlsConfigSet[]=\r
+{\r
+ {\r
+#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)\r
+ .FlsAcWrite = __FLS_ERASE_RAM__,\r
+ .FlsAcErase = __FLS_WRITE_RAM__,\r
+#else\r
+ .FlsAcWrite = NULL,\r
+ .FlsAcErase = NULL,\r
+#endif\r
+ .FlsJobEndNotification = NULL,\r
+ .FlsJobErrorNotification = NULL,\r
+ .FlsInfo = flashInfo,\r
+// .FlsSectorList = &fls_evbSectorList[0],\r
+// .FlsSectorListSize = sizeof(fls_evbSectorList)/sizeof(Fls_SectorType),\r
+// .FlsBlockToPartitionMap = Fls_BlockToPartitionMap,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/** @addtogroup Fls Flash Driver\r
+ * @{ */\r
+\r
+/** @file Fls_Cfg.h\r
+ * Definitions of configuration parameters for Flash Driver.\r
+ */\r
+\r
+\r
+\r
+#ifndef FLS_CFG_H_\r
+#define FLS_CFG_H_\r
+\r
+#define USE_FLS_INFO STD_ON\r
+\r
+\r
+/* STD container : Fls\r
+ * FlsConfigSet 1..*\r
+ * FlsGeneral 1\r
+ * FlsPublishedInformation 1\r
+ */\r
+\r
+#include "MemIf_Types.h"\r
+\r
+/* FlsGeneral, 3.0 OK */\r
+#define FLS_VARIANT_PB STD_OFF\r
+#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */\r
+#define FLS_BASE_ADDRESS 0x00000000\r
+#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */\r
+#define FLS_COMPARE_API STD_ON\r
+#define FLS_DEV_ERROR_DETECT STD_ON\r
+#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */\r
+#define FLS_GET_JOB_RESULT_API STD_ON\r
+#define FLS_GET_STATUS_API STD_ON\r
+#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */\r
+//#define FLS_TOTAL_SIZE\r
+#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */\r
+#define FLS_VERSION_INFO_API STD_ON\r
+\r
+/* FlsPublishedInformation, 3.0 OK */\r
+#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */\r
+#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */\r
+#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */\r
+#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */\r
+#define FLS_ERASE_TIME 0 /* NO SUPPORT */\r
+#define FLS_ERASED_VALUE 0xff /* NO SUPPORT */\r
+#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */\r
+#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */\r
+#define FLS_WRITE_TIME 0 /* NO SUPPORT */\r
+\r
+/* MCU Specific */\r
+#if defined(CFG_MPC5606S)\r
+\r
+#define FLASH_BANK_CNT 3\r
+#define FLASH_PAGE_SIZE 8\r
+#define FLASH_MAX_SECTORS 16\r
+#define FLS_TOTAL_SIZE ((16*4+512+512)*1024)\r
+\r
+#else\r
+#error CPU not supported\r
+#endif\r
+\r
+#if (USE_FLS_INFO==STD_ON)\r
+\r
+typedef struct Flash {\r
+ uint32_t size;\r
+ uint32_t sectCnt;\r
+ uint32_t bankSize;\r
+ uint32_t regBase;\r
+ uint32_t sectAddr[FLASH_MAX_SECTORS+1];\r
+ uint16_t addrSpace[FLASH_MAX_SECTORS+1];\r
+} FlashType;\r
+\r
+\r
+#else\r
+typedef struct {\r
+ Fls_LengthType FlsNumberOfSectors;\r
+ Fls_LengthType FlsPageSize;\r
+ Fls_LengthType FlsSectorSize;\r
+ Fls_AddressType FlsSectorStartaddress;\r
+} Fls_SectorType;\r
+#endif\r
+\r
+\r
+struct Flash;\r
+\r
+typedef struct {\r
+ void (*FlsAcErase)(); /* NO SUPPORT */\r
+ void (*FlsAcWrite)(); /* NO SUPPORT */\r
+ // FlsCallCycle N/A in core.\r
+ void (*FlsJobEndNotification)();\r
+ void (*FlsJobErrorNotification)();\r
+ uint32_t FlsMaxReadFastMode; /* NO SUPPORT */\r
+ uint32_t FlsMaxReadNormalMode; /* NO SUPPORT */\r
+ uint32_t FlsMaxWriteFastMode; /* NO SUPPORT */\r
+ uint32_t FlsMaxWriteNormalMode; /* NO SUPPORT */\r
+ uint32_t FlsProtection; /* NO SUPPORT */\r
+#if (USE_FLS_INFO==STD_ON)\r
+ const struct Flash *FlsInfo;\r
+#else\r
+ const Fls_SectorType *FlsSectorList;\r
+#endif\r
+// const uint32 FlsSectorListSize; /* NO SUPPORT */\r
+} Fls_ConfigSetType;\r
+\r
+typedef Fls_ConfigSetType Fls_ConfigType;\r
+\r
+extern const Fls_ConfigSetType FlsConfigSet[];\r
+\r
+#endif /*FLS_CFG_H_*/\r
+/** @} */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef WDG_CFG_H_\r
+#define WDG_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "WdgIf_Types.h"\r
+\r
+typedef struct\r
+{\r
+ uint32 ReloadValue;\r
+ uint8 ActivationBit;\r
+}Wdg_SettingsType;\r
+\r
+typedef struct\r
+{\r
+ WdgIf_ModeType Wdg_DefaultMode;\r
+ Wdg_SettingsType WdgSettingsFast;\r
+ Wdg_SettingsType WdgSettingsSlow;\r
+ Wdg_SettingsType WdgSettingsOff;\r
+}Wdg_ModeConfigType;\r
+\r
+typedef struct\r
+{\r
+ const Wdg_GeneralType *Wdg_General;\r
+ const Wdg_ModeConfigType *Wdg_ModeConfig;\r
+}Wdg_ConfigType;\r
+\r
+ extern const Wdg_GeneralType WdgGeneral;\r
+ extern const Wdg_ConfigType WdgConfig;\r
+\r
+#endif /* WDG_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "Wdg.h"\r
+\r
+const Wdg_ModeConfigType WdgModeConfig =\r
+{\r
+ .Wdg_DefaultMode = WDGIF_OFF_MODE,\r
+ .WdgSettingsFast =\r
+ {\r
+ .ReloadValue = 0x280, // 5 ms\r
+ .ActivationBit = 1,\r
+ },\r
+ .WdgSettingsSlow =\r
+ {\r
+ .ReloadValue = 0xA00, // 20 ms\r
+ .ActivationBit = 1,\r
+ },\r
+ .WdgSettingsOff =\r
+ {\r
+ .ReloadValue = 0x7D00,\r
+ .ActivationBit = 0,\r
+ },\r
+};\r
+\r
+const Wdg_GeneralType WdgGeneral =\r
+{\r
+ .Wdg_Index = 1,\r
+ .Wdg_TriggerLocationPtr = Wdg_Trigger,\r
+ .Wdg_SetModeLocationPtr = Wdg_SetMode,\r
+};\r
+\r
+\r
+const Wdg_ConfigType WdgConfig =\r
+{\r
+ .Wdg_General = &WdgGeneral,\r
+ .Wdg_ModeConfig = &WdgModeConfig,\r
+};\r
+\r
+\r
--- /dev/null
+\r
+# Version of build system\r
+REQUIRED_BUILD_SYSTEM_VERSION=1.0.0\r
+\r
+# Get configuration makefiles\r
+-include ../config/*.mk\r
+-include ../config/$(BOARDDIR)/*.mk\r
+\r
+\r
+# Project settings\r
+\r
+SELECT_CONSOLE = RAMLOG\r
+\r
+SELECT_OPT = OPT_DEBUG \r
+\r
--- /dev/null
+\r
+MOD_USE += KERNEL ECUM MCU \r
+\r
--- /dev/null
+/*\r
+* Configuration of module: EcuM (EcuM_Callout_Stubs.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+\r
+#include "EcuM.h"\r
+#include "EcuM_Generated_Types.h"\r
+#include "Det.h"\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_CANTP)\r
+#include "CanTp.h"\r
+#endif\r
+#if defined(USE_J1939TP)\r
+#include "J1939Tp.h"\r
+#endif\r
+#if defined(USE_DCM)\r
+#include "Dcm.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_IOHWAB)\r
+#include "IoHwAb.h"\r
+#endif\r
+#if defined(USE_FLS)\r
+#include "Fls.h"\r
+#endif\r
+#if defined(USE_EEP)\r
+#include "Eep.h"\r
+#endif\r
+#if defined(USE_FEE)\r
+#include "Fee.h"\r
+#endif\r
+#if defined(USE_EA)\r
+#include "Ea.h"\r
+#endif\r
+#if defined(USE_NVM)\r
+#include "NvM.h"\r
+#endif\r
+#if defined(USE_COMM)\r
+#include "ComM.h"\r
+#endif\r
+#if defined(USE_NM)\r
+#include "Nm.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#endif\r
+#if defined(USE_CANSM)\r
+#include "CanSM.h"\r
+#endif\r
+#if defined(USE_UDPNM)\r
+#include "UdpNm.h"\r
+#endif\r
+#if defined(USE_LINSM)\r
+#include "LinSM.h"\r
+#endif\r
+#if defined(USE_SPI)\r
+#include "Spi.h"\r
+#endif\r
+#if defined(USE_WDG)\r
+#include "Wdg.h"\r
+#endif\r
+#if defined(USE_WDGM)\r
+#include "WdgM.h"\r
+#endif\r
+\r
+void EcuM_AL_DriverInitZero(void)\r
+{\r
+ Det_Init();/** @req EcuM2783 */\r
+ Det_Start();/** @req EcuM2634 */\r
+}\r
+\r
+extern EcuM_ConfigType EcuMConfig;\r
+\r
+EcuM_ConfigType* EcuM_DeterminePbConfiguration(void)\r
+{\r
+ return &EcuMConfig;\r
+}\r
+\r
+void EcuM_AL_DriverInitOne(const EcuM_ConfigType *ConfigPtr)\r
+{\r
+ (void)ConfigPtr;\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_MCU)\r
+ Mcu_Init(ConfigPtr->McuConfig);\r
+\r
+ /* Set up default clock (Mcu_InitClock requires initRun==1) */\r
+ /* Ignoring return value */\r
+ (void) Mcu_InitClock( ConfigPtr->McuConfig->McuDefaultClockSettings );\r
+\r
+ // Wait for PLL to sync.\r
+ while (Mcu_GetPllStatus() != MCU_PLL_LOCKED)\r
+ {\r
+ ;\r
+ }\r
+#endif\r
+\r
+#if defined(USE_DEM)\r
+ // Preinitialize DEM\r
+ Dem_PreInit();\r
+#endif\r
+\r
+#if defined(USE_PORT)\r
+ // Setup Port\r
+ Port_Init(ConfigPtr->PortConfig);\r
+#endif\r
+\r
+\r
+#if defined(USE_GPT)\r
+ // Setup the GPT\r
+ Gpt_Init(ConfigPtr->GptConfig);\r
+#endif\r
+\r
+ // Setup watchdog\r
+#if defined(USE_WDG)\r
+ Wdg_Init(ConfigPtr->WdgConfig);\r
+#endif\r
+#if defined(USE_WDGM)\r
+ WdgM_Init(ConfigPtr->WdgMConfig);\r
+#endif\r
+\r
+#if defined(USE_DMA)\r
+ // Setup DMA\r
+ Dma_Init(ConfigPtr->DmaConfig);\r
+#endif\r
+\r
+#if defined(USE_ADC)\r
+ // Setup ADC\r
+ Adc_Init(ConfigPtr->AdcConfig);\r
+#endif\r
+\r
+ // Setup ICU\r
+ // TODO\r
+\r
+ // Setup PWM\r
+#if defined(USE_PWM)\r
+ // Setup PWM\r
+ Pwm_Init(ConfigPtr->PwmConfig);\r
+#endif\r
+}\r
+\r
+void EcuM_AL_DriverInitTwo(const EcuM_ConfigType* ConfigPtr)\r
+{\r
+ (void)ConfigPtr;\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_SPI)\r
+ // Setup SPI\r
+ Spi_Init(ConfigPtr->SpiConfig);\r
+#endif\r
+\r
+#if defined(USE_EEP)\r
+ // Setup EEP\r
+ Eep_Init(ConfigPtr->EepConfig);\r
+#endif\r
+\r
+#if defined(USE_FLS)\r
+ // Setup Flash\r
+ Fls_Init(ConfigPtr->FlashConfig);\r
+#endif\r
+\r
+#if defined(USE_FEE)\r
+ // Setup FEE\r
+ Fee_Init();\r
+#endif\r
+\r
+#if defined(USE_EA)\r
+ // Setup EA\r
+ Ea_Init();\r
+#endif\r
+\r
+#if defined(USE_NVM)\r
+ // Setup NVRAM Manager and start the read all job\r
+ NvM_Init();\r
+ NvM_ReadAll();\r
+#endif\r
+\r
+ // Setup CAN tranceiver\r
+ // TODO\r
+\r
+#if defined(USE_CAN)\r
+ // Setup Can driver\r
+ Can_Init(ConfigPtr->CanConfig);\r
+#endif\r
+\r
+#if defined(USE_CANIF)\r
+ // Setup CanIf\r
+ CanIf_Init(ConfigPtr->CanIfConfig);\r
+#endif\r
+\r
+#if defined(USE_CANTP)\r
+ // Setup CAN TP\r
+ CanTp_Init();\r
+#endif\r
+\r
+#if defined(USE_CANSM)\r
+ CanSM_Init(ConfigPtr->CanSMConfig);\r
+#endif\r
+\r
+#if defined(USE_J1939TP)\r
+ // Setup J1939Tp\r
+ J1939Tp_Init(ConfigPtr->J1939TpConfig);\r
+#endif\r
+\r
+\r
+ // Setup LIN\r
+ // TODO\r
+\r
+#if defined(USE_PDUR)\r
+ // Setup PDU Router\r
+ PduR_Init(ConfigPtr->PduRConfig);\r
+#endif\r
+\r
+#if defined(USE_CANNM)\r
+ // Setup Can Network Manager\r
+ CanNm_Init(ConfigPtr->CanNmConfig);\r
+#endif\r
+\r
+#if defined(USE_UDPNM)\r
+ // Setup Udp Network Manager\r
+ UdpNm_Init(ConfigPtr->UdpNmConfig);\r
+#endif\r
+\r
+#if defined(USE_NM)\r
+ // Setup Network Management Interface\r
+ Nm_Init(ConfigPtr->NmConfig);\r
+#endif\r
+\r
+#if defined(USE_COM)\r
+ // Setup COM layer\r
+ Com_Init(ConfigPtr->ComConfig);\r
+#endif\r
+\r
+#if defined(USE_DCM)\r
+ // Setup DCM\r
+ Dcm_Init();\r
+#endif\r
+\r
+#if defined(USE_IOHWAB)\r
+ // Setup IO hardware abstraction layer\r
+ IoHwAb_Init();\r
+#endif\r
+\r
+}\r
+\r
+void EcuM_AL_DriverInitThree(const EcuM_ConfigType* ConfigPtr)\r
+{\r
+ (void)ConfigPtr;\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_DEM)\r
+ // Setup DEM\r
+ Dem_Init();\r
+#endif\r
+\r
+#if defined(USE_COMM)\r
+ // Setup Communication Manager\r
+ ComM_Init(ConfigPtr->ComMConfig);\r
+#endif\r
+}\r
+\r
+void EcuM_OnEnterRUN(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnExitRun(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnExitPostRun(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnPrepShutdown(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoSleep(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoOffOne(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoOffTwo(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_AL_SwitchOff(void)\r
+{\r
+\r
+}\r
--- /dev/null
+/*\r
+* Configuration of module: EcuM (EcuM_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error EcuM: Configuration file expected BSW module version to be 2.0.*
+#endif
+
+\r
+\r
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_OFF\r
+#define ECUM_DEV_ERROR_DETECT STD_OFF\r
+\r
+#define ECUM_MAIN_FUNCTION_PERIOD (200)\r
+#define ECUM_NVRAM_READALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_WRITEALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_MIN_RUN_DURATION (10000)\r
+\r
+\r
+typedef enum {\r
+ ECUM_USER_User_1,\r
+ ECUM_USER_ENDMARK // Must be the last in list!\r
+} EcuM_UserList;\r
+\r
+\r
+#endif /*ECUM_CFG_H_*/\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: EcuM (EcuM_Generated_Types.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error EcuM: Configuration file expected BSW module version to be 2.0.*
+#endif
+
+\r
+#ifndef _ECUM_GENERATED_TYPES_H_\r
+#define _ECUM_GENERATED_TYPES_H_\r
+\r
+#ifdef CFG_ECUM_USE_SERVICE_COMPONENT\r
+#include "Rte_EcuM.h"\r
+#endif\r
+\r
+#include "EcuM_Types.h"\r
+\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_PORT)\r
+#include "Port.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_DMA)\r
+#include "Dma.h"\r
+#endif\r
+#if defined(USE_ADC)\r
+#include "Adc.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_COMM)\r
+#include "ComM.h"\r
+#endif\r
+#if defined(USE_NM)\r
+#include "Nm.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#endif\r
+#if defined(USE_CANSM)\r
+#include "CanSM.h"\r
+#endif\r
+#if defined(USE_J1939TP)\r
+#include "J1939Tp.h"\r
+#endif\r
+#if defined(USE_UDPNM)\r
+#include "UdpNm.h"\r
+#endif\r
+#if defined(USE_LINSM)\r
+#include "LinSM.h"\r
+#endif\r
+#if defined(USE_FLS)\r
+#include "Fls.h"\r
+#endif\r
+#if defined(USE_EEP)\r
+#include "Eep.h"\r
+#endif\r
+#if defined(USE_SPI)\r
+#include "Spi.h"\r
+#endif\r
+#if defined(USE_WDG)\r
+#include "Wdg.h"\r
+#endif\r
+#if defined(USE_WDGM)\r
+#include "WdgM.h"\r
+#endif\r
+#if defined(USE_WDGIF)\r
+#include "WdgIf.h"\r
+#endif\r
+\r
+\r
+typedef struct\r
+{\r
+ EcuM_StateType EcuMDefaultShutdownTarget;\r
+ uint8 EcuMDefaultSleepMode;\r
+ AppModeType EcuMDefaultAppMode;\r
+ uint32 EcuMRunMinimumDuration;\r
+ uint32 EcuMNvramReadAllTimeout;\r
+ uint32 EcuMNvramWriteAllTimeout;\r
+\r
+#if defined(USE_MCU)\r
+ const Mcu_ConfigType* McuConfig;\r
+#endif\r
+#if defined(USE_PORT)\r
+ const Port_ConfigType* PortConfig;\r
+#endif\r
+#if defined(USE_CAN)\r
+ const Can_ConfigType* CanConfig;\r
+#endif\r
+#if defined(USE_CANIF)\r
+ const CanIf_ConfigType* CanIfConfig;\r
+#endif\r
+#if defined(USE_CANSM)\r
+ const CanSM_ConfigType* CanSMConfig;\r
+#endif\r
+#if defined(USE_NM)\r
+ const Nm_ConfigType* NmConfig;\r
+#endif\r
+#if defined(USE_CANNM)\r
+ const CanNm_ConfigType* CanNmConfig;\r
+#endif\r
+#if defined(USE_UDPNM)\r
+ const UdpNm_ConfigType* UdpNmConfig;\r
+#endif\r
+#if defined(USE_COMM)\r
+ const ComM_ConfigType* ComMConfig;\r
+#endif\r
+#if defined(USE_COM)\r
+ const Com_ConfigType* ComConfig;\r
+#endif\r
+#if defined(USE_J1939TP)\r
+ const J1939Tp_ConfigType* J1939TpConfig;\r
+#endif\r
+#if defined(USE_PDUR)\r
+ const PduR_PBConfigType* PduRConfig;\r
+#endif\r
+#if defined(USE_PWM)\r
+ const Pwm_ConfigType* PwmConfig;\r
+#endif\r
+#if defined(USE_DMA)\r
+ const Dma_ConfigType* DmaConfig;\r
+#endif\r
+#if defined(USE_ADC)\r
+ const Adc_ConfigType* AdcConfig;\r
+#endif\r
+#if defined(USE_GPT)\r
+ const Gpt_ConfigType* GptConfig;\r
+#endif\r
+#if defined(USE_FLS)\r
+ const Fls_ConfigType* FlashConfig;\r
+#endif\r
+#if defined(USE_EEP)\r
+ const Eep_ConfigType* EepConfig;\r
+#endif\r
+#if defined(USE_SPI)\r
+ const Spi_ConfigType* SpiConfig;\r
+#endif\r
+#if defined(USE_WDG)\r
+ const Wdg_ConfigType* WdgConfig;\r
+#endif\r
+#if defined(USE_WDGIF)\r
+ const WdgIf_ConfigType* WdgIfConfig;\r
+#endif\r
+#if defined(USE_WDGM)\r
+ const WdgM_ConfigType* WdgMConfig;\r
+#endif\r
+} EcuM_ConfigType;\r
+\r
+#endif /*_ECUM_GENERATED_TYPES_H_*/\r
--- /dev/null
+/*\r
+* Configuration of module: EcuM (EcuM_PBcfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+\r
+\r
+#include "EcuM.h"\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#if defined(USE_CANSM)\r
+extern const CanSM_ConfigType CanSM_Config;\r
+#endif\r
+#if defined(USE_NM)\r
+extern const Nm_ConfigType Nm_Config;\r
+#endif\r
+#if defined(USE_CANNM)\r
+extern const CanNm_ConfigType CanNm_Config;\r
+#endif\r
+#if defined(USE_UDPNM)\r
+extern const UdpNm_ConfigType UdpNm_Config;\r
+#endif\r
+#if defined(USE_COMM)\r
+extern const ComM_ConfigType ComM_Config;\r
+#endif\r
+\r
+#if defined(USE_J1939TP)\r
+extern const J1939Tp_ConfigType J1939Tp_Config;\r
+#endif\r
+\r
+\r
+EcuM_ConfigType EcuMConfig =\r
+{\r
+ .EcuMDefaultShutdownTarget = ECUM_STATE_RESET,\r
+ .EcuMDefaultSleepMode = 0, // Don't care\r
+ .EcuMDefaultAppMode = OSDEFAULTAPPMODE,\r
+ .EcuMNvramReadAllTimeout = ECUM_NVRAM_READALL_TIMEOUT,\r
+ .EcuMNvramWriteAllTimeout = ECUM_NVRAM_WRITEALL_TIMEOUT,\r
+ .EcuMRunMinimumDuration = ECUM_NVRAM_MIN_RUN_DURATION,\r
+\r
+#if defined(USE_MCU)\r
+ .McuConfig = McuConfigData,\r
+#endif\r
+#if defined(USE_PORT)\r
+ .PortConfig = &PortConfigData,\r
+#endif\r
+#if defined(USE_CAN)\r
+ .CanConfig = &CanConfigData,\r
+#endif\r
+#if defined(USE_CANIF)\r
+ .CanIfConfig = &CanIf_Config,\r
+#endif\r
+#if defined(USE_CANSM)\r
+ .CanSMConfig = &CanSM_Config,\r
+#endif\r
+#if defined(USE_CANNM)\r
+ .CanNmConfig = &CanNm_Config,\r
+#endif\r
+#if defined(USE_UDPNM)\r
+ .UdpNmConfig = &UdpNm_Config,\r
+#endif\r
+#if defined(USE_COM)\r
+ .ComConfig = &ComConfiguration,\r
+#endif\r
+#if defined(USE_COMM)\r
+ .ComMConfig = &ComM_Config,\r
+#endif\r
+#if defined(USE_J1939TP)\r
+ .J1939TpConfig = &J1939Tp_Config,\r
+#endif\r
+#if defined(USE_NM)\r
+ .NmConfig = &Nm_Config,\r
+#endif\r
+#if defined(USE_PDUR)\r
+ .PduRConfig = &PduR_Config,\r
+#endif\r
+#if defined(USE_J1939TP)\r
+ .J1939TpConfig = &J1939Tp_Config,\r
+#endif\r
+#if defined(USE_DMA)\r
+ .DmaConfig = DmaConfig,\r
+#endif\r
+#if defined(USE_ADC)\r
+ .AdcConfig = AdcConfig,\r
+#endif\r
+#if defined(USE_PWM)\r
+ .PwmConfig = &PwmConfig,\r
+#endif\r
+#if defined(USE_WDG)\r
+ .WdgConfig = &WdgConfig,\r
+#endif\r
+#if defined(USE_WDGM)\r
+ .WdgMConfig = &WdgMConfig,\r
+#endif\r
+#if defined(USE_WDGIF)\r
+ .WdgIfConfig = &WdgIfConfig,\r
+#endif\r
+#if defined(USE_GPT)\r
+ .GptConfig = GptConfigData,\r
+#endif\r
+#if defined(USE_FLS)\r
+ .FlashConfig = FlsConfigSet,\r
+#endif\r
+#if defined(USE_EEP)\r
+ .EepConfig = EepConfigData,\r
+#endif\r
+#if defined(USE_SPI)\r
+ .SpiConfig = &SpiConfigData,\r
+#endif\r
+};\r
--- /dev/null
+/*\r
+* Configuration of module: Mcu (Mcu_Cfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+\r
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 8000000UL,\r
+ .Pll1 = 0,\r
+ .Pll2 = 64,\r
+ .Pll3 = 2,\r
+ },\r
+};\r
+\r
+\r
+const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ .McuClockSrcFailureNotification = 0,\r
+ .McuRamSectors = MCU_NBR_OF_RAM_SECTIONS,\r
+ .McuClockSettings = 1,\r
+ .McuDefaultClockSettings = 0,\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ }\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/*\r
+* Configuration of module: Mcu (Mcu_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.2\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((MCU_SW_MAJOR_VERSION == 2) && (MCU_SW_MINOR_VERSION == 0)) )
+#error Mcu: Configuration file expected BSW module version to be 2.0.*
+#endif
+
+\r
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_OFF \r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_Clock = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+\r
+#define MCU_NBR_OF_RAM_SECTIONS 0\r
+\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/*\r
+* Configuration of module: Os (Os_Cfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.34\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+ \r
+\r
+#include "kernel.h"\r
+\r
+\r
+// ############################### EXTERNAL REFERENCES #############################\r
+\r
+/* Application externals */\r
+\r
+/* Interrupt externals */\r
+\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+// ############################### APPLICATIONS #############################\r
+GEN_APPLICATION_HEAD = {\r
+ GEN_APPLICATION(\r
+ /* id */ APPLICATION_ID_OsApplication1,\r
+ /* name */ "OsApplication1",\r
+ /* trusted */ true, /* NOT CONFIGURABLE IN TOOLS */\r
+ /* core */ 0, /* Default value, multicore not enabled.*/\r
+ /* StartupHook */ NULL,\r
+ /* ShutdownHook */ NULL,\r
+ /* ErrorHook */ NULL,\r
+ /* rstrtTaskId */ 0 /* NOT CONFIGURABLE IN TOOLS */\r
+ ), \r
+};\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD = {\r
+ GEN_COUNTER( COUNTER_ID_Counter1,\r
+ "Counter1",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 1,\r
+ 0,\r
+ APPLICATION_ID_OsApplication1, /* Application owner */\r
+ 1 /* Accessing application mask */\r
+ ),\r
+};\r
+\r
+ CounterType Os_Arc_OsTickCounter = COUNTER_ID_Counter1;\r
+\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm1, ALARM_AUTOSTART_RELATIVE, 100, 100, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD = {\r
+ GEN_ALARM( ALARM_ID_Alarm1,\r
+ "Alarm1",\r
+ COUNTER_ID_Counter1,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm1),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_eTask1,\r
+ EVENT_MASK_Event1,\r
+ 0,\r
+ APPLICATION_ID_OsApplication1, /* Application owner */\r
+ 1 /* Accessing application mask */\r
+ ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+\r
+DECLARE_STACK(bTask3,2048);\r
+DECLARE_STACK(eTask1,2048);\r
+DECLARE_STACK(eTask2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD = {\r
+ GEN_BTASK( /* */OsIdle,\r
+ /* name */"OsIdle",\r
+ /* priority */0,\r
+ /* schedule */FULL,\r
+ /* autostart */TRUE,\r
+ /* resource_int_p */NULL,\r
+ /* resource mask */0,\r
+ /* activation lim. */1,\r
+ /* App owner */0,\r
+ /* Accessing apps */1 \r
+ ),\r
+ GEN_BTASK(\r
+ /* */bTask3,\r
+ /* name */"bTask3",\r
+ /* priority */1,\r
+ /* schedule */FULL,\r
+ /* autostart */FALSE,\r
+ /* resource_int_p */NULL,\r
+ /* resource mask */0,\r
+ /* activation lim. */1,\r
+ /* App owner */APPLICATION_ID_OsApplication1,\r
+ /* Accessing apps */1\r
+ ), \r
+ GEN_ETASK(\r
+ /* */eTask1,\r
+ /* name */"eTask1",\r
+ /* priority */1,\r
+ /* schedule */FULL,\r
+ /* name */TRUE,\r
+ /* resource_int_p */NULL,\r
+ /* resource mask */0,\r
+ /* event mask */1,\r
+ /* App owner */APPLICATION_ID_OsApplication1,\r
+ /* Accessing apps */1\r
+ ), \r
+ GEN_ETASK(\r
+ /* */eTask2,\r
+ /* name */"eTask2",\r
+ /* priority */1,\r
+ /* schedule */FULL,\r
+ /* name */TRUE,\r
+ /* resource_int_p */NULL,\r
+ /* resource mask */0,\r
+ /* event mask */1,\r
+ /* App owner */APPLICATION_ID_OsApplication1,\r
+ /* Accessing apps */1\r
+ ), \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+GEN_ISR_MAP = {\r
+ 0\r
+};\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+\r
--- /dev/null
+/*\r
+* Configuration of module: Os (Os_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.34\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+*/\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error Os: Configuration file expected BSW module version to be 2.0.*
+#endif
+
+\r
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+// Application Id's\r
+#define APPLICATION_ID_OsApplication1 0\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm1 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_Counter1 0\r
+\r
+// System counter\r
+#define OSMAXALLOWEDVALUE UINT_MAX// NOT CONFIGURABLE IN TOOLS\r
+#define OSTICKSPERBASE 1 // NOT CONFIGURABLE IN TOOLS\r
+#define OSMINCYCLE 1 // NOT CONFIGURABLE IN TOOLS\r
+#define OSTICKDURATION 1000000UL // Time between ticks in nano seconds\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_Counter1 OSMAXALLOWEDVALUE\r
+#define OSTICKSPERBASE_Counter1 1 // NOT CONFIGURABLE IN TOOLS\r
+#define OSMINCYCLE_Counter1 1\r
+#define OS_TICKS2SEC_Counter1(_ticks) ( (OSTICKDURATION * _ticks)/1000000000UL )\r
+#define OS_TICKS2MS_Counter1(_ticks) ( (OSTICKDURATION * _ticks)/1000000UL )\r
+#define OS_TICKS2US_Counter1(_ticks) ( (OSTICKDURATION * _ticks)/1000UL )\r
+#define OS_TICKS2NS_Counter1(_ticks) (OSTICKDURATION * _ticks)\r
+\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_Event1 1\r
+#define EVENT_MASK_Event2 1\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+\r
+#define TASK_ID_bTask3 1\r
+#define TASK_ID_eTask1 2\r
+#define TASK_ID_eTask2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void bTask3( void );\r
+void eTask1( void );\r
+void eTask2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 2\r
+//#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+#define OS_APPLICATION_CNT 1\r
+#define OS_SERVICE_CNT 0 /* ARCTICSTUDIO_GENERATOR_TODO */\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_USE_APPLICATIONS STD_ON\r
+#define OS_USE_MEMORY_PROT STD_OFF /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_USE_TASK_TIMING_PROT STD_OFF /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_USE_ISR_TIMING_PROT STD_OFF /* NOT CONFIGURABLE IN TOOLS */\r
+//#define OS_SC3 STD_ON /* NOT CONFIGURABLE IN TOOLS */ \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_USE_PARAMETER_ACCESS STD_ON /* NOT CONFIGURABLE IN TOOLS */\r
+#define OS_RES_SCHEDULER STD_ON /* NOT CONFIGURABLE IN TOOLS */\r
+\r
+#define OS_ISR_CNT 0\r
+#define OS_ISR2_CNT 0\r
+#define OS_ISR1_CNT 0\r
+\r
+#define OS_ISR_MAX_CNT 10\r
+\r
+#define OS_NUM_CORES 1\r
+\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+\r
+PROJECTNAME=os_simple\r
+ROOTDIR?=../../../..\r
+include $(ROOTDIR)/scripts/project_defaults.mk\r
+\r
+ifneq (${MAKELEVEL},0) \r
+\r
+ # object files\r
+ obj-y += os_simple.o\r
+ obj-y += system_hooks.o\r
+ \r
+ VPATH += $(ROOTDIR)/examples\r
+ VPATH += $(ROOTDIR)/examples/$(PROJECTNAME)\r
+\r
+endif\r
+\r
+\r
+\r
+\r
+\r
Std_ReturnType ValidateGroup(const Adc_ConfigType *ConfigPtr, Adc_GroupType group,Adc_APIServiceIDType api)\r
{\r
Std_ReturnType res = E_OK;\r
- if(!((group >= 0) && (group < ConfigPtr->nbrOfGroups))) {\r
+ if(!(((group % NOF_GROUP_PER_CONTROLLER) >= 0) && ((group % NOF_GROUP_PER_CONTROLLER) < ConfigPtr->nbrOfGroups))) {\r
Det_ReportError(MODULE_ID_ADC,0,api,ADC_E_PARAM_GROUP );\r
res = E_NOT_OK;\r
}\r
}\r
else\r
{\r
- returnValue = ConfigPtr->groupConfigPtr[group].status->groupStatus;\r
+ returnValue = ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->groupStatus;\r
}\r
#else\r
- returnValue = ConfigPtr->groupConfigPtr[group].status->groupStatus;\r
+ returnValue = ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->groupStatus;\r
#endif\r
return (returnValue);\r
}\r
{\r
res = E_NOT_OK;\r
}\r
- else if (ConfigPtr->groupConfigPtr[group].groupCallback == NULL)\r
+ else if (ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].groupCallback == NULL)\r
{\r
res = E_NOT_OK;\r
Det_ReportError(MODULE_ID_ADC,0,ADC_ENABLEGROUPNOTIFICATION_ID ,ADC_E_NOTIF_CAPABILITY );\r
res = E_OK;\r
#endif\r
if (E_OK == res){\r
- ConfigPtr->groupConfigPtr[group].status->notifictionEnable = 1;\r
+ ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->notifictionEnable = 1;\r
}\r
}\r
\r
{\r
res = E_NOT_OK;\r
}\r
- else if (ConfigPtr->groupConfigPtr[group].groupCallback == NULL)\r
+ else if (ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].groupCallback == NULL)\r
{\r
res = E_NOT_OK;\r
Det_ReportError(MODULE_ID_ADC,0,ADC_DISABLEGROUPNOTIFICATION_ID ,ADC_E_NOTIF_CAPABILITY );\r
res = E_OK;\r
#endif\r
if (E_OK == res){\r
- ConfigPtr->groupConfigPtr[group].status->notifictionEnable = 0;\r
+ ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->notifictionEnable = 0;\r
}\r
}\r
#endif\r
{\r
returnValue = E_NOT_OK;\r
}\r
- else if (ADC_IDLE == ConfigPtr->groupConfigPtr[group].status->groupStatus)\r
+ else if (ADC_IDLE == ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->groupStatus)\r
{\r
/* ADC388. */\r
returnValue = E_NOT_OK;\r
{\r
returnValue = E_NOT_OK;\r
}\r
- else if ( NULL == ConfigPtr->groupConfigPtr[group].status->resultBufferPtr )\r
+ else if ( NULL == ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->resultBufferPtr )\r
{\r
/* ResultBuffer not set, ADC424 */\r
Det_ReportError(MODULE_ID_ADC,0,ADC_STARTGROUPCONVERSION_ID, ADC_E_BUFFER_UNINIT );\r
returnValue = E_NOT_OK;\r
}\r
- else if (!(ADC_TRIGG_SRC_SW == ConfigPtr->groupConfigPtr[group].triggerSrc))\r
+ else if (!(ADC_TRIGG_SRC_SW == ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].triggerSrc))\r
{\r
/* Wrong trig source, ADC133. */\r
Det_ReportError(MODULE_ID_ADC,0,ADC_STARTGROUPCONVERSION_ID, ADC_E_WRONG_TRIGG_SRC);\r
returnValue = E_NOT_OK;\r
}\r
- else if (!((ADC_IDLE == ConfigPtr->groupConfigPtr[group].status->groupStatus) ||\r
- (ADC_STREAM_COMPLETED == ConfigPtr->groupConfigPtr[group].status->groupStatus)))\r
+ else if (!((ADC_IDLE == ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->groupStatus) ||\r
+ (ADC_STREAM_COMPLETED == ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->groupStatus)))\r
{\r
/* Group status not OK, ADC351, ADC428 */\r
Det_ReportError(MODULE_ID_ADC,0,ADC_STARTGROUPCONVERSION_ID, ADC_E_BUSY );\r
{\r
returnValue = E_NOT_OK;\r
}\r
- else if (!(ADC_TRIGG_SRC_SW == ConfigPtr->groupConfigPtr[group].triggerSrc))\r
+ else if (!(ADC_TRIGG_SRC_SW == ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].triggerSrc))\r
{\r
/* Wrong trig source, ADC164. */\r
Det_ReportError(MODULE_ID_ADC,0,ADC_STOPGROUPCONVERSION_ID, ADC_E_WRONG_TRIGG_SRC);\r
returnValue = E_NOT_OK;\r
}\r
- else if (ADC_IDLE == ConfigPtr->groupConfigPtr[group].status->groupStatus)\r
+ else if (ADC_IDLE == ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->groupStatus)\r
{\r
/* Group status not OK, ADC241 */\r
Det_ReportError(MODULE_ID_ADC,0,ADC_STOPGROUPCONVERSION_ID, ADC_E_IDLE );\r
#if ( ADC_DEV_ERROR_DETECT == STD_ON )\r
if(ValidateInit(adcState, ADC_DEINIT_ID) == E_OK)\r
{\r
- for (Adc_GroupType group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ for (Adc_GroupType group = (Adc_GroupType)0; group < ConfigPtr->nbrOfGroups; group++)\r
{\r
/* Check ADC is IDLE or COMPLETE*/\r
- if((ConfigPtr->groupConfigPtr[group].status->groupStatus != ADC_IDLE) && (ConfigPtr->groupConfigPtr[group].status->groupStatus != ADC_STREAM_COMPLETED))\r
+ if((ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->groupStatus != ADC_IDLE) && (ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->groupStatus != ADC_STREAM_COMPLETED))\r
{\r
Det_ReportError(MODULE_ID_ADC,0,ADC_DEINIT_ID, ADC_E_BUSY );\r
returnValue = E_NOT_OK;\r
{\r
returnValue = E_NOT_OK;\r
}\r
- else if(ConfigPtr->groupConfigPtr[group].status->groupStatus == ADC_IDLE)\r
+ else if(ConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->groupStatus == ADC_IDLE)\r
{ /** @req ADC215 Check ADC is not in IDLE */\r
Det_ReportError(MODULE_ID_ADC,0,ADC_GETSTREAMLASTPOINTER_ID, ADC_E_IDLE );\r
returnValue = E_NOT_OK;\r
\r
#include "Adc.h"\r
\r
-#define ADC_GROUP0 0\r
-\r
typedef enum\r
{\r
ADC_UNINIT,\r
#include "mpc563m.h"\r
#elif defined(CFG_MPC5604B)\r
#include "MPC5604B_0M27V_0102.h"\r
+#elif defined(CFG_MPC5606B)\r
+#include "MPC5606B.h"\r
#elif defined(CFG_MPC5606S)\r
#include "mpc5606s.h"\r
#elif defined(CFG_MPC5668)\r
projects / arc.git / commitdiff