]> rtime.felk.cvut.cz Git - arc.git/commitdiff
Handling ECC error (IVOR2 exception). Just storing the error register.
authorhebe <devnull@localhost>
Tue, 25 Sep 2012 10:14:52 +0000 (12:14 +0200)
committerhebe <devnull@localhost>
Tue, 25 Sep 2012 10:14:52 +0000 (12:14 +0200)
(transplanted from ae00a3113566868f19377ae3861ac1c27c4996db)

arch/ppc/mpc55xx/kernel/arch.c
arch/ppc/mpc55xx/kernel/arch_krn.sx
system/kernel/include/arch.h

index f502e56eace07812127d2656d550a84afb3cd6f2..c3bb0e0a37145b6b4bd47e4f53e613f1d65c1f6b 100644 (file)
@@ -169,5 +169,21 @@ void Os_ArchInit( void ) {
 #endif\r
 }\r
 \r
+uint32 EccErrReg = 0;\r
 \r
+void Os_ArchGetECCError( uint32 *err ) {\r
+\r
+       /* Clear interrupt flag */\r
+#if defined(CFG_MPC5668)\r
+       if(ECSM.ESR.B.PFNCE){\r
+               ECSM.ESR.B.PFNCE = 1;\r
+       }\r
+       *err = EccErrReg;\r
+#else\r
+       *err = 0;\r
+#endif\r
+\r
+       /* Clear stored  */\r
+       EccErrReg = 0;\r
+}\r
 \r
index e89bfddcbe3cddcf95df6c76cb5dba8c0796bca6..d92e49b8ed72f4cc406ab2177b10fa1f69911aab 100644 (file)
 #define INTC_EOIR                      0xfff48018\r
 #define INTC_SSCIR0                    0xfff48020\r
 \r
+/* ECC */\r
+#if defined (CFG_MPC5668)\r
+#define ECSM_BASE      0xfff40000\r
+#define ECSM_ESR    0x47\r
+#define ESR_R1BC       0x20\r
+#define ESR_RNCE       0x02\r
+#define ESR_F1BC       0x10\r
+#define ESR_FNCE       0x01\r
+#endif\r
 /* ----------------------------[private macro]-------------------------------*/\r
 \r
 #define        LOCK()                  wrteei  0\r
@@ -249,6 +258,22 @@ restoreFuncContext:
 /**\r
  * External input exception handlers \r
  */ \r
\r
+               .global exception_IVOR2\r
+               .balign 16\r
+exception_IVOR2:\r
+       /* Check for ECC problems */\r
+       //Store err reg\r
+       LOAD_ADDR_32(r8,ECSM_BASE)\r
+       lbz  r9,ECSM_ESR(r8)\r
+       LOAD_ADDR_32(r8,EccErrReg)\r
+       stw             r9,0(r8)\r
+       // Jump to next instruction\r
+       mfspr   r9,srr0\r
+       addi    r9,r9,4\r
+       mtspr   srr0,r9\r
+       rfi     \r
+       \r
                .global exception_IVOR4\r
                .global restoreIsrContext\r
                .balign 16\r
@@ -567,7 +592,12 @@ handleException:
 exception_tbl:\r
        EXC_TABLE_CODE(0)\r
        EXC_TABLE_CODE(1)\r
-       EXC_TABLE_CODE(2)\r
+#if defined(CFG_MPC5668)\r
+       .balign 16\r
+    b      exception_IVOR2\r
+#else\r
+    EXC_TABLE_CODE(2)\r
+#endif\r
        EXC_TABLE_CODE(3)\r
     .balign 16\r
     b      exception_IVOR4\r
index 677a5b737de13874a39646298fda2a60a7df3270..05832eb959a8444aa28141c235030d2135d4a6dc 100644 (file)
@@ -119,4 +119,6 @@ unsigned int Os_ArchGetScSize( void );
 \r
 void Os_ArchSetTaskEntry(OsTaskVarType *pcbPtr );\r
 \r
+boolean Os_ArchGetECCError( uint32 *err );\r
+\r
 #endif /*ARCH_H_*/\r