\r
/* ----------------------------[includes]------------------------------------*/\r
\r
+#include <stdlib.h>\r
+#include <assert.h>\r
+#include <limits.h>\r
+#include <string.h>\r
#include "Spi.h"\r
#include "mpc55xx.h"\r
//#include <stdio.h>\r
#include "Mcu.h"\r
#include "math.h"\r
#include "Dma.h"\r
-#include <assert.h>\r
-#include <limits.h>\r
#include "Det.h"\r
-#include <stdlib.h>\r
#include "isr.h"\r
/* ----------------------------[private define]------------------------------*/\r
\r
#define DEBUG_LVL DEBUG_NONE\r
#include "debug.h"\r
\r
-#define USE_LOCAL_RAMLOG\r
+//#define USE_LOCAL_RAMLOG\r
\r
#if defined(USE_LOCAL_RAMLOG)\r
#define RAMLOG_STR(_x) ramlog_str(_x)\r
\r
/* ----------------------------[private typedef]-----------------------------*/\r
\r
+#if (SPI_IMPLEMENTATION == IMPL_DMA )\r
+typedef struct Spi_DmaConfig {\r
+ Dma_ChannelType RxDmaChannel;\r
+ Dma_ChannelType TxDmaChannel;\r
+} Spi_DmaConfigType;\r
+\r
+#endif\r
+\r
+\r
+\r
typedef union {\r
vuint32_t R;\r
struct {\r
\r
Spi_ChannelInfoType Spi_ChannelInfo[SPI_MAX_CHANNEL];\r
\r
-Spi_GlobalType Spi_Global = { .initRun = FALSE,\r
- .asyncMode = SPI_INTERRUPT_MODE, // TODO: according to SPI151 it should be polling\r
- };\r
+Spi_GlobalType Spi_Global;\r
\r
Spi_UnitType Spi_Unit[4];\r
Spi_SeqUnitType Spi_SeqUnit[SPI_MAX_SEQUENCE];\r
Spi_JobUnitType Spi_JobUnit[SPI_MAX_JOB];\r
\r
+\r
+#if (SPI_IMPLEMENTATION == IMPL_DMA)\r
+/* When using DMA it assumes predefined names */\r
+Spi_DmaConfigType Spi_DmaConfig[4] = {\r
+#if (SPI_USE_HW_UNIT_0 == STD_ON )\r
+ {\r
+ .RxDmaChannel = DMA_DSPI_A_RESULT_CHANNEL,\r
+ .TxDmaChannel = DMA_DSPI_A_COMMAND_CHANNEL,\r
+ },\r
+#else\r
+ { -1, -1 },\r
+#endif\r
+#if (SPI_USE_HW_UNIT_1 == STD_ON )\r
+ {\r
+ .RxDmaChannel = DMA_DSPI_B_RESULT_CHANNEL,\r
+ .TxDmaChannel = DMA_DSPI_B_COMMAND_CHANNEL,\r
+ },\r
+#else\r
+ { -1, -1 },\r
+#endif\r
+#if (SPI_USE_HW_UNIT_2 == STD_ON )\r
+ {\r
+ .RxDmaChannel = DMA_DSPI_C_RESULT_CHANNEL,\r
+ .TxDmaChannel = DMA_DSPI_C_COMMAND_CHANNEL,\r
+ },\r
+#else\r
+ { -1, -1 },\r
+#endif\r
+#if (SPI_USE_HW_UNIT_3 == STD_ON )\r
+ {\r
+ .RxDmaChannel = DMA_DSPI_D_RESULT_CHANNEL,\r
+ .TxDmaChannel = DMA_DSPI_D_COMMAND_CHANNEL,\r
+ }\r
+#else\r
+ { -1, -1 },\r
+#endif\r
+};\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+\r
/* ----------------------------[private functions]---------------------------*/\r
\r
+#if (SPI_IMPLEMENTATION == IMPL_FIFO )\r
/**\r
* Get the buffer for a channel.\r
*
return buf;\r
}\r
\r
+#endif\r
\r
static void Spi_Isr(uint32);\r
\r
\r
#if (SPI_IMPLEMENTATION == IMPL_DMA)\r
// To be 100% sure also wait for the DMA transfer to complete.\r
+#if 0\r
while (!Dma_ChannelDone(\r
Spi_Global.configPtr->SpiHwConfig[unit].RxDmaChannel)) {\r
Spi_Global.totalNbrOfWaitRxDMA++;\r
}\r
+#else\r
+ while (!Dma_ChannelDone(Spi_Unit[unit].dmaRxChannel)) {\r
+ Spi_Global.totalNbrOfWaitRxDMA++;\r
+ }\r
+\r
+#endif\r
#endif\r
\r
/* Halt DSPI unit until we are ready for next transfer. */\r
int i;\r
int j;\r
uint32 tmp;\r
+ McuE_PeriperalClock_t perClock;\r
\r
volatile struct DSPI_tag *spiHw = GET_SPI_HW_PTR(unit);\r
/* BAUDRATE CALCULATION\r
* --> BR=Fsys/(Baudrate.* 2 )\r
*\r
*/\r
- clock = McuE_GetPeripheralClock(\r
- Spi_Global.configPtr->SpiHwConfig[unit].PeripheralClock);\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S)\r
+ switch(unit) {\r
+ case 0:\r
+ perClock = PERIPHERAL_CLOCK_DSPI_A;\r
+ break;\r
+ case 1:\r
+ perClock = PERIPHERAL_CLOCK_DSPI_B;\r
+ break;\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
+ case 2:\r
+ perClock = PERIPHERAL_CLOCK_DSPI_C;\r
+ break;\r
+ case 3:\r
+ perClock = PERIPHERAL_CLOCK_DSPI_D;\r
+ break;\r
+#endif\r
+ default:\r
+ assert(0);\r
+ break;\r
+ }\r
+#else\r
+#error CPU not supported\r
+#endif\r
+ clock = McuE_GetPeripheralClock(perClock);\r
+\r
DEBUG(DEBUG_MEDIUM,"%s: Peripheral clock at %d Mhz\n",MODULE_NAME,clock);\r
\r
DEBUG(DEBUG_MEDIUM,"%s: Want to run at %d Mhz\n",MODULE_NAME,extDev->SpiBaudrate);\r
switch (unit) {\r
#if defined(CFG_MPC5606S)\r
case 0:\r
- ISR_INSTALL_ISR2("SPI_A",Spi_Isr_A, DSPI_0_ISR_EOQF, 1, 0);\r
+ ISR_INSTALL_ISR2("SPI_A",Spi_Isr_A, DSPI_0_ISR_EOQF, 15, 0);\r
break;\r
case 1:\r
- ISR_INSTALL_ISR2("SPI_B",Spi_Isr_B, DSPI_1_ISR_EOQF, 1, 0);\r
+ ISR_INSTALL_ISR2("SPI_B",Spi_Isr_B, DSPI_1_ISR_EOQF, 15, 0);\r
break;\r
#elif defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
case 0:\r
- ISR_INSTALL_ISR2("SPI_A",Spi_Isr_A, DSPI_A_ISR_EOQF, 1, 0);\r
+ ISR_INSTALL_ISR2("SPI_A",Spi_Isr_A, DSPI_A_ISR_EOQF, 15, 0);\r
break;\r
case 1:\r
- ISR_INSTALL_ISR2("SPI_B",Spi_Isr_B, DSPI_B_ISR_EOQF, 1, 0);\r
+ ISR_INSTALL_ISR2("SPI_B",Spi_Isr_B, DSPI_B_ISR_EOQF, 15, 0);\r
break;\r
case 2:\r
- ISR_INSTALL_ISR2("SPI_A",Spi_Isr_C, DSPI_C_ISR_EOQF, 1, 0);\r
+ ISR_INSTALL_ISR2("SPI_A",Spi_Isr_C, DSPI_C_ISR_EOQF, 15, 0);\r
break;\r
case 3:\r
- ISR_INSTALL_ISR2("SPI_B",Spi_Isr_D, DSPI_D_ISR_EOQF, 1, 0);\r
+ ISR_INSTALL_ISR2("SPI_B",Spi_Isr_D, DSPI_D_ISR_EOQF, 15, 0);\r
break;\r
#else\r
#error ISR NOT installed.\r
void Spi_Init(const Spi_ConfigType *ConfigPtr) {\r
\r
const Spi_JobConfigType *jobConfig2;\r
+\r
+ memset(&Spi_Global,0,sizeof(Spi_Global));\r
Spi_Global.configPtr = ConfigPtr;\r
Spi_Global.extBufPtr = Spi_Eb;\r
+\r
+ Spi_Global.asyncMode = SPI_INTERRUPT_MODE;\r
+\r
// Spi_Global.currSeq = SEQ_NOT_VALID;\r
\r
// Set all sequence results to OK\r
//\r
\r
/* Make sure that this channel shall be used. */\r
- assert (ConfigPtr->SpiHwConfig[confNr].Activated);\r
+ //assert (ConfigPtr->SpiHwConfig[confNr].Activated);\r
+ assert(Spi_DmaConfig[confNr].TxDmaChannel != (-1));\r
+ assert(Spi_DmaConfig[confNr].RxDmaChannel != (-1));\r
+\r
+ Spi_Unit[confNr].dmaTxChannel = Spi_DmaConfig[confNr].TxDmaChannel;\r
+ Spi_Unit[confNr].dmaRxChannel = Spi_DmaConfig[confNr].RxDmaChannel;\r
\r
- Spi_Unit[confNr].dmaTxChannel\r
- = ConfigPtr->SpiHwConfig[confNr].TxDmaChannel;\r
- Spi_Unit[confNr].dmaRxChannel\r
- = ConfigPtr->SpiHwConfig[confNr].RxDmaChannel;\r
Spi_DmaSetup(confNr);\r
#endif\r
\r
\r
static inline int osPrioToCpuPio( uint8_t prio ) {\r
assert(prio<32);\r
+ assert(prio>1);\r
return prio>>1; // Os have 32 -> 16\r
}\r
\r
__FLS_ERASE_RAM__ = .;\r
. = . + SIZEOF(.fls_rom);\r
} > ram\r
- \r
- /* Always place last in RAM */\r
- .heap ALIGN(0x4): {\r
- PROVIDE(_heap_start = .);\r
- } > ram\r
- \r
-\r
.ctors :\r
{\r
KEEP (*(SORT(.ctors.*)))\r
}\r
\r
- .uninit ALIGN(0x10): { *(.winidea_port .ramlog .dem_eventmemory_pri) ; } > ram\r
+.uninit ALIGN(0x10): { *(.winidea_port .ramlog .dem_eventmemory_pri) ; } > ram\r
+\r
+ /* Always place last in RAM */\r
+ .heap ALIGN(0x4): {\r
+ PROVIDE(_heap_start = .);\r
+ } > ram\r
+\r
\r
__FLS_SIZE__ = SIZEOF(.fls_rom);\r
__FLS_WRITE_RAM__ = __FLS_ERASE_RAM__ + (__FLS_WRITE_ROM__ - __FLS_ERASE_ROM__);\r
/*
* TODO: probably better to
*/
-#define SPI_SEQ_EEP_CMD SPI_SEQ_E2_CMD
-#define SPI_SEQ_EEP_CMD2 SPI_SEQ_E2_CMD2
-#define SPI_SEQ_EEP_READ SPI_SEQ_E2_READ
-#define SPI_SEQ_EEP_WRITE SPI_SEQ_E2_WRITE
-
-#define SPI_CH_EEP_CMD SPI_CH_E2_CMD
-#define SPI_CH_EEP_ADDR SPI_CH_E2_ADDR
-#define SPI_CH_EEP_WREN SPI_CH_E2_WREN
-#define SPI_CH_EEP_DATA SPI_CH_E2_DATA
+#define SPI_SEQ_EEP_CMD SPI_SEQ_CMD
+#define SPI_SEQ_EEP_CMD2 SPI_SEQ_CMD2
+#define SPI_SEQ_EEP_READ SPI_SEQ_READ
+#define SPI_SEQ_EEP_WRITE SPI_SEQ_WRITE
+
+#define SPI_CH_EEP_CMD SPI_CH_CMD
+#define SPI_CH_EEP_ADDR SPI_CH_ADDR
+#define SPI_CH_EEP_WREN SPI_CH_WREN
+#define SPI_CH_EEP_DATA SPI_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
-/* -------------------------------- Arctic Core ------------------------------
- * Arctic Core - the open source AUTOSAR platform http://arccore.com
- *
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
- *
- * This source code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- * -------------------------------- Arctic Core ------------------------------*/
-
-
-#ifndef SPI_CFG_H_
-#define SPI_CFG_H_
-
-#include "Dma.h"
-#include "mpc55xx.h"
-#include "Mcu.h"
-
-#define DSPI_CTRL_A 0
-#define DSPI_CTRL_B 1
-#define DSPI_CTRL_C 2
-#define DSPI_CTRL_D 3
-
-/*
- * General configuration
- */
-
-// Maximum amount of data that can be written/read in one go.
-#define SPI_EB_MAX_LENGTH 64
-
-// Switches the Spi_Cancel function ON or OFF.
-#define SPI_CANCEL_API STD_OFF
-
-// Selects the SPI Handler/Driver Channel Buffers usage allowed and delivered.
-// LEVEL 0 - Only Internal buffers
-// LEVEL 1 - Only external buffers
-// LEVEL 2 - Both internal/external buffers
-#define SPI_CHANNEL_BUFFERS_ALLOWED 1
-
-#define SPI_DEV_ERROR_DETECT STD_ON
-// Switches the Spi_GetHWUnitStatus function ON or OFF.
-#define SPI_HW_STATUS_API STD_ON
-// Switches the Interruptible Sequences handling functionality ON or OFF.
-#define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_OFF
-
-// LEVEL 0 - Simple sync
-// LEVEL 1 - Basic async
-// LEVEL 2 - Enhanced mode
-#define SPI_LEVEL_DELIVERED 2
-
-#define SPI_VERSION_INFO_API STD_ON
-
-#if 0
-#if SPI_LEVEL_DELIVERED>=1
-#define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_ON
-#endif
-#endif
-
-typedef enum {
- SPI_EXT_DEVICE_A_E2,
-} Spi_ExternalDeviceTypeType;
-
-#define SPI_CH_E2_CMD 0
-#define SPI_CH_E2_ADDR 1
-#define SPI_CH_E2_WREN 2
-#define SPI_CH_E2_DATA 3
-
-#define SPI_JOB_E2_CMD 0
-#define SPI_JOB_E2_CMD2 1
-#define SPI_JOB_E2_DATA 2
-#define SPI_JOB_E2_WREN 3
-
-#define SPI_SEQ_E2_CMD 0
-#define SPI_SEQ_E2_CMD2 1
-#define SPI_SEQ_E2_READ 2
-#define SPI_SEQ_E2_WRITE 3
-
-#define SPI_MAX_JOB 4
-#define SPI_MAX_CHANNEL 4
-#define SPI_MAX_SEQUENCE 4
-
-
-#endif /*SPI_CFG_H_*/
+/*\r
+* Configuration of module: Spi (Spi_Cfg.h)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.13\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+* on Tue Jun 14 20:57:25 CEST 2011\r
+*/\r
+\r
+
+\r
+#ifndef SPI_CFG_H\r
+#define SPI_CFG_H\r
+\r
+#include "Dma.h"\r
+#include "mpc55xx.h"\r
+#include "Mcu.h"\r
+\r
+#define DSPI_CTRL_A 0\r
+#define DSPI_CTRL_B 1\r
+#define DSPI_CTRL_C 2\r
+#define DSPI_CTRL_D 3\r
+\r
+/*\r
+ * General configuration\r
+ */\r
+\r
+// Switches the Spi_Cancel function ON or OFF.\r
+#define SPI_CANCEL_API STD_ON\r
+\r
+// Selects the SPI Handler/Driver Channel Buffers usage allowed and delivered.\r
+// LEVEL 0 - Only Internal buffers\r
+// LEVEL 1 - Only external buffers\r
+// LEVEL 2 - Both internal/external buffers\r
+#define SPI_CHANNEL_BUFFERS_ALLOWED 1\r
+\r
+#define SPI_DEV_ERROR_DETECT STD_ON\r
+// Switches the Spi_GetHWUnitStatus function ON or OFF.\r
+#define SPI_HW_STATUS_API STD_ON\r
+// Switches the Interruptible Sequences handling functionality ON or OFF.\r
+#define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_OFF\r
+\r
+// LEVEL 0 - Simple sync\r
+// LEVEL 1 - Basic async\r
+// LEVEL 2 - Enhanced mode\r
+#define SPI_LEVEL_DELIVERED 2\r
+\r
+#define SPI_VERSION_INFO_API STD_ON\r
+\r
+#if 0\r
+#if SPI_LEVEL_DELIVERED>=1\r
+#define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_ON\r
+#endif\r
+#endif\r
+\r
+// External devices\r
+typedef enum {\r
+ SPI_device_1,\r
+} Spi_ExternalDeviceTypeType;\r
+\r
+// Channels\r
+#define SPI_CH_WREN 0\r
+#define SPI_CH_CMD 1\r
+#define SPI_CH_DATA 2\r
+#define SPI_CH_ADDR 3\r
+\r
+// Jobs\r
+#define SPI_JOB_CMD2 0 \r
+#define SPI_JOB_DATA 1 \r
+#define SPI_JOB_CMD 2 \r
+#define SPI_JOB_WREN 3 \r
+\r
+// Sequences\r
+#define SPI_SEQ_CMD 0\r
+#define SPI_SEQ_WRITE 1\r
+#define SPI_SEQ_READ 2\r
+#define SPI_SEQ_CMD2 3\r
+\r
+\r
+#define SPI_MAX_JOB 4\r
+#define SPI_MAX_CHANNEL 4\r
+#define SPI_MAX_SEQUENCE 4\r
+\r
+#define SPI_USE_HW_UNIT_0 STD_ON\r
+#define SPI_USE_HW_UNIT_1 STD_OFF\r
+#define SPI_USE_HW_UNIT_2 STD_OFF\r
+#define SPI_USE_HW_UNIT_3 STD_OFF\r
+\r
+\r
+#endif /*SPI_CFG_H*/\r
-/* -------------------------------- Arctic Core ------------------------------
- * Arctic Core - the open source AUTOSAR platform http://arccore.com
- *
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
- *
- * This source code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- * -------------------------------- Arctic Core ------------------------------*/
-
-#include "Spi.h"
-#include "Spi_Cfg.h"
-#include <stdlib.h>
-
-
-
-// SPI_0
-//#define SPI_0_CS 1 /* Using PCSB1 */
-#define SPI_0_CS 2 /* Using PCSB2 */
-
-
-#define SPI_SEQ_END_NOTIFICATION NULL
-#define SPI_JOB_END_NOTIFICAITON NULL
-
-// Notifications
-// Seq
-#define SPI_SEQ_E2_CMD_END_NOTIFICATION NULL
-#define SPI_SEQ_E2_CMD2_END_NOTIFICATION NULL
-#define SPI_SEQ_E2_READ_END_NOTIFICATION NULL
-#define SPI_SEQ_E2_WRITE_END_NOTIFICATION NULL
-// Jobs
-#define SPI_JOB_E2_CMD_END_NOTIFICATION NULL
-#define SPI_JOB_E2_CMD2_END_NOTIFICATION NULL
-#define SPI_JOB_E2_DATA_END_NOTIFICATION NULL
-#define SPI_JOB_E2_WREN_END_NOTIFICATION NULL
-
-
-/* SEQUENCES */
-const Spi_SequenceConfigType SpiSequenceConfigData[] =
-{
- {
- .SpiSequenceId = SPI_SEQ_E2_CMD,
- .SpiInterruptibleSequence = 0,
- .SpiSeqEndNotification = SPI_SEQ_E2_CMD_END_NOTIFICATION,
- .JobAssignment = { SPI_JOB_E2_CMD,(-1)},
- },
- {
- .SpiSequenceId = SPI_SEQ_E2_CMD2,
- .SpiInterruptibleSequence = 0,
- .SpiSeqEndNotification = SPI_SEQ_E2_CMD2_END_NOTIFICATION,
- .JobAssignment = { SPI_JOB_E2_CMD2,(-1)},
- },
- {
- .SpiSequenceId = SPI_SEQ_E2_READ,
- .SpiInterruptibleSequence = 0,
- .SpiSeqEndNotification = SPI_SEQ_E2_READ_END_NOTIFICATION,
- .JobAssignment = { SPI_JOB_E2_DATA,(-1)},
- },
- {
- .SpiSequenceId = SPI_SEQ_E2_WRITE,
- .SpiInterruptibleSequence = 0,
- .SpiSeqEndNotification = SPI_SEQ_E2_WRITE_END_NOTIFICATION,
- .JobAssignment = { SPI_JOB_E2_DATA,(-1)},
- },
-
-};
-
-/* JOBS */
-const Spi_JobConfigType SpiJobConfigData[] =
-{
- {
- .SpiJobId = SPI_JOB_E2_CMD,
- .SpiHwUnit = DSPI_CTRL_A,
- .SpiJobPriority = 3,
- .SpiJobEndNotification = SPI_JOB_E2_CMD_END_NOTIFICATION,
- .DeviceAssignment = SPI_EXT_DEVICE_A_E2,
- .ChannelAssignment = { SPI_CH_E2_CMD ,(-1)},
- },
- {
- .SpiJobId = SPI_JOB_E2_CMD2,
- .SpiHwUnit = DSPI_CTRL_A,
- .SpiJobPriority = 3,
- .SpiJobEndNotification = SPI_JOB_E2_CMD2_END_NOTIFICATION,
- .DeviceAssignment = SPI_EXT_DEVICE_A_E2,
- .ChannelAssignment = { SPI_CH_E2_CMD ,SPI_CH_E2_DATA,(-1)},
- },
- {
- .SpiJobId = SPI_JOB_E2_DATA,
- .SpiHwUnit = DSPI_CTRL_A,
- .SpiJobPriority = 2,
- .SpiJobEndNotification = SPI_JOB_E2_DATA_END_NOTIFICATION,
- .DeviceAssignment = SPI_EXT_DEVICE_A_E2,
- .ChannelAssignment = { SPI_CH_E2_CMD, SPI_CH_E2_ADDR ,SPI_CH_E2_DATA,(-1)},
- },
-};
-
-uint32 Spi_GetJobCnt(void ) { return sizeof(SpiJobConfigData)/sizeof(SpiJobConfigData[0]); }
-
-
-/* CHANNELS */
-const Spi_ChannelConfigType SpiChannelConfigData[] =
-{
- {
- .SpiChannelId = SPI_CH_E2_CMD,
- .SpiChannelType = SPI_EB,
- .SpiDataWidth = 8,
- .SpiIbNBuffers = 0,
- .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
- .SpiDefaultData = 0x00,
- },
- {
- .SpiChannelId = SPI_CH_E2_ADDR,
- .SpiChannelType = SPI_EB,
- .SpiDataWidth = 16,
- .SpiIbNBuffers = 0,
- .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
- .SpiDefaultData = 0x0000,
- },
- {
- .SpiChannelId = SPI_CH_E2_WREN,
- .SpiChannelType = SPI_EB,
- .SpiDataWidth = 8,
- .SpiIbNBuffers = 0,
- .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
- .SpiDefaultData = 0x00,
- },
-
- {
- .SpiChannelId = SPI_CH_E2_DATA,
- .SpiChannelType = SPI_EB,
- .SpiDataWidth = 8,
- .SpiIbNBuffers = 0,
- .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
- .SpiDefaultData = 0x00,
- },
-
- {
- .SpiChannelId = (-1),
- }
-};
-
-uint32 Spi_GetChanneCnt(void ) { return sizeof(SpiChannelConfigData)/sizeof(SpiChannelConfigData[0]); }
-
-const Spi_ExternalDeviceType SpiExternalConfigData[] =
-{
-
- // E2
- {
- .SpiBaudrate = 1000000UL,
- .SpiCsIdentifier = SPI_0_CS,
- .SpiCsPolarity = STD_LOW,
- .SpiDataShiftEdge = SPI_EDGE_LEADING,
- .SpiEnableCs = 1,
- .SpiShiftClockIdleLevel = STD_LOW,
- .SpiTimeClk2Cs = 606, // ns
- .SpiTimeCs2Clk = 606, // ns
- },
-};
-
-uint32 Spi_GetExternalDeviceCnt(void ) { return sizeof(SpiExternalConfigData)/sizeof(SpiExternalConfigData[0]); }
-
-const Spi_HwConfigType SpiHwConfig[] =
-{
- {
- .IsrPriority = 1,
- .Activated = TRUE,
- .RxDmaChannel = DMA_DSPI_A_RESULT_CHANNEL,
- .TxDmaChannel = DMA_DSPI_A_COMMAND_CHANNEL,
- .PeripheralClock = PERIPHERAL_CLOCK_DSPI_A,
- },
- {
- .IsrPriority = 1,
- .Activated = FALSE,
- }
-};
-
-const Spi_DriverType SpiConfigData =
-{
- .SpiMaxChannel = SPI_MAX_CHANNEL,
- .SpiMaxJob = SPI_MAX_JOB,
- .SpiMaxSequence = SPI_MAX_SEQUENCE,
- .SpiChannelConfig = &SpiChannelConfigData[0],
- .SpiSequenceConfig = &SpiSequenceConfigData[0],
- .SpiJobConfig = &SpiJobConfigData[0],
- .SpiExternalDevice = &SpiExternalConfigData[0],
- .SpiHwConfig = &SpiHwConfig[0],
-};
-
+/*\r
+* Configuration of module: Spi (Spi_Lcfg.c)\r
+*\r
+* Created by: \r
+* Copyright: \r
+*\r
+* Configured for (MCU): MPC560x\r
+*\r
+* Module vendor: ArcCore\r
+* Generator version: 2.0.13\r
+*\r
+* Generated by Arctic Studio (http://arccore.com) \r
+* on Tue Jun 14 20:57:25 CEST 2011\r
+*/\r
+\r
+\r
+\r
+#include "Spi.h"\r
+#include "Spi_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+\r
+\r
+// SPI_0\r
+//#define SPI_0_CS 1 /* Using PCSB1 */\r
+#define SPI_0_CS 2 /* Using PCSB2 */\r
+\r
+\r
+#define SPI_SEQ_END_NOTIFICATION NULL\r
+#define SPI_JOB_END_NOTIFICAITON NULL\r
+\r
+// Notifications\r
+// Seq\r
+#define SPI_SEQ_CMD_END_NOTIFICATION NULL\r
+#define SPI_SEQ_WRITE_END_NOTIFICATION NULL\r
+#define SPI_SEQ_READ_END_NOTIFICATION NULL\r
+#define SPI_SEQ_CMD2_END_NOTIFICATION NULL\r
+// Jobs\r
+#define SPI_JOB_CMD2_END_NOTIFICATION NULL\r
+#define SPI_JOB_DATA_END_NOTIFICATION NULL\r
+#define SPI_JOB_CMD_END_NOTIFICATION NULL\r
+#define SPI_JOB_WREN_END_NOTIFICATION NULL\r
+\r
+\r
+/*************** Sequences **************/\r
+const Spi_SequenceConfigType SpiSequenceConfigData[] =\r
+{\r
+ {\r
+ .SpiSequenceId = SPI_SEQ_CMD,\r
+ .SpiInterruptibleSequence = false,\r
+ .SpiSeqEndNotification = SPI_SEQ_CMD_END_NOTIFICATION,\r
+ .JobAssignment = { \r
+ SPI_JOB_CMD,\r
+ (-1)\r
+ },\r
+ },\r
+ {\r
+ .SpiSequenceId = SPI_SEQ_WRITE,\r
+ .SpiInterruptibleSequence = false,\r
+ .SpiSeqEndNotification = SPI_SEQ_WRITE_END_NOTIFICATION,\r
+ .JobAssignment = { \r
+ SPI_JOB_WREN,\r
+ SPI_JOB_DATA,\r
+ (-1)\r
+ },\r
+ },\r
+ {\r
+ .SpiSequenceId = SPI_SEQ_READ,\r
+ .SpiInterruptibleSequence = false,\r
+ .SpiSeqEndNotification = SPI_SEQ_READ_END_NOTIFICATION,\r
+ .JobAssignment = { \r
+ SPI_JOB_DATA,\r
+ (-1)\r
+ },\r
+ },\r
+ {\r
+ .SpiSequenceId = SPI_SEQ_CMD2,\r
+ .SpiInterruptibleSequence = false,\r
+ .SpiSeqEndNotification = SPI_SEQ_CMD2_END_NOTIFICATION,\r
+ .JobAssignment = { \r
+ SPI_JOB_CMD2,\r
+ (-1)\r
+ },\r
+ },\r
+};\r
+\r
+/*************** Jobs **************/\r
+const Spi_JobConfigType SpiJobConfigData[] =\r
+{\r
+ {\r
+ .SpiJobId = SPI_JOB_CMD2,\r
+ .SpiHwUnit = CSIB0,\r
+ .SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS\r
+ .SpiJobEndNotification = SPI_JOB_CMD2_END_NOTIFICATION,\r
+ .ChannelAssignment = {\r
+ SPI_CH_CMD,\r
+ SPI_CH_DATA,\r
+ (-1)\r
+ },\r
+ .DeviceAssignment = SPI_device_1,\r
+ },\r
+ {\r
+ .SpiJobId = SPI_JOB_DATA,\r
+ .SpiHwUnit = CSIB0,\r
+ .SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS\r
+ .SpiJobEndNotification = SPI_JOB_DATA_END_NOTIFICATION,\r
+ .ChannelAssignment = {\r
+ SPI_CH_CMD,\r
+ SPI_CH_ADDR,\r
+ SPI_CH_DATA,\r
+ (-1)\r
+ },\r
+ .DeviceAssignment = SPI_device_1,\r
+ },\r
+ {\r
+ .SpiJobId = SPI_JOB_CMD,\r
+ .SpiHwUnit = CSIB0,\r
+ .SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS\r
+ .SpiJobEndNotification = SPI_JOB_CMD_END_NOTIFICATION,\r
+ .ChannelAssignment = {\r
+ SPI_CH_CMD,\r
+ (-1)\r
+ },\r
+ .DeviceAssignment = SPI_device_1,\r
+ },\r
+ {\r
+ .SpiJobId = SPI_JOB_WREN,\r
+ .SpiHwUnit = CSIB0,\r
+ .SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS\r
+ .SpiJobEndNotification = SPI_JOB_WREN_END_NOTIFICATION,\r
+ .ChannelAssignment = {\r
+ SPI_CH_WREN,\r
+ (-1)\r
+ },\r
+ .DeviceAssignment = SPI_device_1,\r
+ },\r
+};\r
+\r
+uint32 Spi_GetJobCnt(void ) { return sizeof(SpiJobConfigData)/sizeof(SpiJobConfigData[0]); }\r
+\r
+\r
+/*************** Channels **************/\r
+const Spi_ChannelConfigType SpiChannelConfigData[] =\r
+{\r
+ {\r
+ .SpiChannelId = SPI_CH_WREN,\r
+ .SpiChannelType = SPI_EB,\r
+ .SpiDataWidth = 8,\r
+ .SpiIbNBuffers = 0,\r
+ .SpiEbMaxLength = 1, \r
+ .SpiDefaultData = 6,\r
+ .SpiTransferStart = SPI_TRANSFER_START_MSB,\r
+ },\r
+ {\r
+ .SpiChannelId = SPI_CH_CMD,\r
+ .SpiChannelType = SPI_EB,\r
+ .SpiDataWidth = 8,\r
+ .SpiIbNBuffers = 0,\r
+ .SpiEbMaxLength = 64, \r
+ .SpiDefaultData = 0,\r
+ .SpiTransferStart = SPI_TRANSFER_START_MSB,\r
+ },\r
+ {\r
+ .SpiChannelId = SPI_CH_DATA,\r
+ .SpiChannelType = SPI_EB,\r
+ .SpiDataWidth = 8,\r
+ .SpiIbNBuffers = 0,\r
+ .SpiEbMaxLength = 64, \r
+ .SpiDefaultData = 0,\r
+ .SpiTransferStart = SPI_TRANSFER_START_MSB,\r
+ },\r
+ {\r
+ .SpiChannelId = SPI_CH_ADDR,\r
+ .SpiChannelType = SPI_EB,\r
+ .SpiDataWidth = 16,\r
+ .SpiIbNBuffers = 0,\r
+ .SpiEbMaxLength = 64, \r
+ .SpiDefaultData = 0,\r
+ .SpiTransferStart = SPI_TRANSFER_START_MSB,\r
+ },\r
+ {\r
+ .SpiChannelId = (-1),\r
+ }\r
+};\r
+\r
+uint32 Spi_GetChanneCnt(void ) { return sizeof(SpiChannelConfigData)/sizeof(SpiChannelConfigData[0]); }\r
+\r
+/*************** External Devices **************/\r
+const Spi_ExternalDeviceType SpiExternalConfigData[] =\r
+{\r
+ {\r
+ .SpiBaudrate = 100000UL,\r
+ .SpiCsIdentifier = 2,\r
+ .SpiCsPolarity = STD_LOW,\r
+ .SpiDataShiftEdge = SPI_EDGE_LEADING,\r
+ .SpiEnableCs = 0, // NOT SUPPORTED IN TOOLS\r
+ .SpiShiftClockIdleLevel = STD_LOW,\r
+ .SpiTimeClk2Cs = 606, // ns\r
+ .SpiTimeCs2Clk = 606, // ns\r
+ },\r
+};\r
+\r
+uint32 Spi_GetExternalDeviceCnt(void ) { return sizeof(SpiExternalConfigData)/sizeof(SpiExternalConfigData[0]); }\r
+\r
+\r
+\r
+const Spi_DriverType SpiConfigData =\r
+{\r
+ .SpiMaxChannel = SPI_MAX_CHANNEL,\r
+ .SpiMaxJob = SPI_MAX_JOB,\r
+ .SpiMaxSequence = SPI_MAX_SEQUENCE,\r
+ .SpiChannelConfig = &SpiChannelConfigData[0],\r
+ .SpiSequenceConfig = &SpiSequenceConfigData[0],\r
+ .SpiJobConfig = &SpiJobConfigData[0],\r
+ .SpiExternalDevice = &SpiExternalConfigData[0],\r
+};\r
+\r
#endif\r
\r
\r
+#define SPI_EB_MAX_LENGTH 64\r
\r
+#define CSIB0 0\r
+#define CSIB1 1\r
+#define CSIB2 2\r
+#define CSIB3 3\r
\r
typedef enum {\r
SPI_UNINIT=0, // The SPI Handler/Driver is not initialized or not usable.\r
typedef struct Spi_HwConfig\r
{\r
/* Interrupt priority level for this SPI channel. */\r
- uint8 IsrPriority;\r
+// uint8 IsrPriority;\r
\r
/* This channel is to be activated for use. */\r
uint8 Activated;\r
Dma_ChannelType TxDmaChannel;\r
\r
/* Peripheral clock source. */\r
- McuE_PeriperalClock_t PeripheralClock;\r
+// McuE_PeriperalClock_t PeripheralClock;\r
}Spi_HwConfigType;\r
\r
\r
// All data needed to configure one SPI-sequence\r
const struct Spi_SequenceConfig * SpiSequenceConfig;\r
\r
- const struct Spi_HwConfig *SpiHwConfig;\r
+// const struct Spi_HwConfig *SpiHwConfig;\r
} Spi_DriverType;\r
\r
typedef Spi_DriverType Spi_ConfigType;\r
projects / arc.git / commitdiff