\r
#define PORT_NOT_CONFIGURED 0x00000000\r
\r
-#define PORT_0_BASE ((Port_RegisterType *)0xFFF7BC30)\r
-#define PORT_1_BASE ((Port_RegisterType *)0xFFF7BC50)\r
-#define PORT_2_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
+#define PORT_0_BASE ((Port_RegisterType *)0xFFF7BC30) // GIO Emulation B register\r
+#define PORT_1_BASE ((Port_RegisterType *)0xFFF7BC50) // GIO Pull Select Register A ??\r
+#define PORT_2_BASE ((Port_RegisterType *)0xFFF7B848) // N2HET1\r
#define PORT_3_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
#define PORT_4_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
#define PORT_5_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
#define PORT_6_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
#define PORT_7_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
-#define PORT_8_BASE ((Port_RegisterType *)0xFFF7DDE0)\r
-#define PORT_9_BASE ((Port_RegisterType *)0xFFF7DFE0)\r
-#define PORT_10_BASE ((Port_RegisterType *)0xFFF7E1E0)\r
+#define PORT_8_BASE ((Port_RegisterType *)0xFFF7DDE0) // DCAN1 TX IO Control Register\r
+#define PORT_9_BASE ((Port_RegisterType *)0xFFF7DFE0) // DCAN2 TX IO Control Register\r
+#define PORT_10_BASE ((Port_RegisterType *)0xFFF7E1E0) // DCAN3 TX IO Control Register\r
#define PORT_NUMBER_OF_PORTS 11\r
\r
static Port_RegisterType * const Port_Base[] =\r
// Bring GIO register out of reset.\r
gioREG->GCR0 = 1;\r
\r
+ /* Hack to connect N2HET1[27] (function 2) to pin A9 */\r
+ *(volatile uint32*)0xFFFFEB10 &= ~0xFF000000;\r
+ *(volatile uint32*)0xFFFFEB10 |= ~0x04000000;\r
+\r
for (uint16 i = 0; i < PORT_NUMBER_OF_PINS; i++) {\r
Port_RefreshPin(i);\r
}\r