#endif\r
\r
\r
-#define CORE_CPUID_CORTEX_M3 0x411FC231UL\r
+#define CORE_MIDR_CORTEX_R4 0x411FC141UL // c0, Main ID Register\r
+\r
\r
typedef struct {\r
uint32 lossOfLockCnt;\r
\r
\r
\r
-\r
-\r
-\r
/**\r
* Type that holds all global data for Mcu\r
*/\r
\r
\r
\r
-/* Haven't found any ID accessable from memory.\r
- * There is the DBGMCU_IDCODE (0xe0042000) found in RM0041 but it\r
- * you can't read from that address..\r
- */\r
+// see tech.ref.manual for Debug Reference Register\r
#if 0\r
cpu_info_t cpu_info_list[] = {\r
{\r
*/\r
core_info_t core_info_list[] = {\r
{\r
- .name = "CORE_ARM_CORTEX_M3",\r
- .pvr = CORE_CPUID_CORTEX_M3,\r
+ .name = "CORE_ARM_CORTEX_R4",\r
+ .pvr = CORE_MIDR_CORTEX_R4,\r
},\r
};\r
\r
/** - Setup pll control register 1:\r
* - Setup reset on oscillator slip\r
* - Setup bypass on pll slip\r
+ * - Setup Pll output clock divider\r
* - Setup reset on oscillator fail\r
- * - Setup Pll output clock divider\r
* - Setup reference clock divider\r
* - Setup Pll multiplier*\r
+ *\r
*/\r
systemREG1->PLLCTL1 =\r
(MCU_RESET_ON_SLIP << MCU_RESET_ON_SLIP_OFFSET)\r
| (((clockSettingsPtr->Pll2 - 1) * 256) << MCU_PLLMUL_OFFSET)\r
| ((clockSettingsPtr->Pll4 - 1) << MCU_PLLDIV_OFFSET);\r
\r
-\r
/** Setup PLLCTL2\r
* - Setup internal Pll output divider\r
* - Enable/Disable frequency modulation (NOT USED)\r
* - Setup bandwidth adjustment (NOT USED)\r
* - Setup spreading amount (NOT USED)\r
*/\r
- systemREG1->PLLCTL2 =\r
+ /*systemREG1->PLLCTL2 =\r
(MCU_FM_ENABLE << MCU_FM_ENABLE_OFFSET)\r
| (MCU_SPREADING_RATE << MCU_SPREADING_RATE_OFFSET)\r
| (MCU_BWADJ << MCU_BWADJ_OFFSET)\r
| (MCU_SPREADING_AMOUNT << MCU_SPREADING_AMOUT_OFFSET)\r
- | ((clockSettingsPtr->Pll3 - 1) << MCU_ODPLL_OFFSET);\r
+ | ((clockSettingsPtr->Pll3 - 1) << MCU_ODPLL_OFFSET);*/\r
+\r
+ systemREG1->PLLCTL2 = 0x00000000U\r
+ | (255U << 22U)\r
+ | (7U << 12U)\r
+ | ((2U - 1U)<< 9U)\r
+ | 61U;\r
+\r
+ /** @b Initialize @b Pll2: */\r
+\r
+ /** - Setup pll2 control register :\r
+ * - setup Pll output clock divider to max before Lock\r
+ * - Setup reference clock divider\r
+ * - Setup internal Pll output divider\r
+ * - Setup Pll multiplier\r
+ */\r
+ systemREG2->PLLCTL3 = ((2U - 1U) << 29U)\r
+ | ((0x1F)<< 24U)\r
+ | ((6U - 1U)<< 16U)\r
+ | ((135U - 1U) << 8U);\r
+\r
+ /** - Enable PLL(s) to start up or Lock */\r
+ systemREG1->CSDIS = 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000008U\r
+ | 0x00000080U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U;\r
+\r
\r
/** - Wait for until clocks are locked */\r
while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) ;\r
while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) ;\r
\r
/** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */\r
- systemREG1->GHVSRC = (SYS_PLL << 24U) // Selectes PLL clock (clock source 1) as wakeup clock source.\r
+ systemREG1->GHVSRC = (SYS_PLL << 24U) // Selectes PLL clock (clock source 1) as wakeup clock source. (Use main oscillator as wake up source for GHV CLK)\r
| (SYS_PLL << 16U) // Select PLL clock (clock source 1) as wakeup when GCLK is off as clock source.\r
| SYS_PLL; // Select PLL clock (clock source 1) as current clock source.\r
\r
+ /** - Disable Peripherals before peripheral powerup*/\r
+ systemREG1->PENA = 0U;\r
+\r
/** - Power-up clocks to all peripharals */\r
pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;\r
pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;\r