* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
- .syntax unified\r
+\r
+ .syntax unified\r
.cpu cortex-r4\r
.fpu softvfp\r
.thumb\r
\r
-.global g_pfnVectors\r
.global Default_Handler\r
\r
+/* Addresses used to setup RAM */\r
.word _sidata\r
.word _sdata\r
.word _edata\r
.word _sbss\r
.word _ebss\r
\r
+/* The address of the stack to use in all modes. */\r
+.word _estack\r
+\r
+\r
/**\r
* @brief This is the code that gets called when the processor first\r
* starts execution following a reset event. Only the absolutely\r
.section .text.Reset_Handler\r
.weak Reset_Handler\r
.type Reset_Handler, %function\r
-Reset_Handler: \r
+\r
+Reset_Handler:\r
\r
/* Set big endian state */\r
SETEND BE\r
\r
-/* Copy the data segment initializers from flash to SRAM */\r
- movs r1, #0\r
-\r
-\r
-Init_Registers:\r
-\r
- mov r0, #0x0000\r
- mov r1, #0x0000\r
- mov r2, #0x0000\r
- mov r3, #0x0000\r
- mov r4, #0x0000\r
- mov r5, #0x0000\r
- mov r6, #0x0000\r
- mov r7, #0x0000\r
- mov r8, #0x0000\r
- mov r9, #0x0000\r
- mov r10, #0x0000\r
- mov r11, #0x0000\r
- mov r12, #0x0000\r
- mov r1, #0x03D0\r
- orr r2, r1, #0x0001\r
- msr cpsr_cxsf, r2\r
- msr spsr_cxsf, r2\r
- mov r8, #0x0000\r
- mov r9, #0x0000\r
- mov r10, #0x0000\r
- mov r11, #0x0000\r
- mov r12, #0x0000\r
- orr r12, r1, #0x0002\r
- msr cpsr_c, r12\r
- msr spsr_cxsf, r12\r
- orr r12, r1, #0x0007\r
- msr cpsr_c, r12\r
- msr spsr_cxsf, r12\r
- orr r12, r1, #0x000B\r
- msr cpsr_c, r12\r
- msr spsr_cxsf, r12\r
- orr r12, r1, #0x0003\r
- msr cpsr_c, r12\r
- msr spsr_cxsf, r12\r
-\r
- /* System level configuration */\r
- mrc p15,0,r11,c1,c0,0 /* Read current system configuration */\r
- mov r12, #0x40000000 /* Set THUMB instruction set mode for interrupts and exceptions */\r
- orr r12, r12, r11\r
- mcr p15,0,r12,c1,c0,0 /* Write new configuration */\r
-\r
-\r
-Init_Stack_Pointers:\r
-\r
-user: .word _estack\r
-svc: .word _estack\r
-fiq: .word _estack\r
-irq: .word _estack\r
-abort: .word _estack\r
-undef: .word _estack\r
-\r
- mov r2, #0xD1\r
- msr cpsr_c, r2\r
- ldr sp, fiq\r
-\r
- mov r2, #0xD2\r
- msr cpsr_c, r2\r
- ldr sp, irq\r
-\r
- mov r2, #0xD7\r
- msr cpsr_c, r2\r
- ldr sp, abort\r
-\r
- mov r2, #0xDB\r
- msr cpsr_c, r2\r
- ldr sp, undef\r
-\r
- mov r2, #0xDF\r
- msr cpsr_c, r2\r
- ldr sp, user\r
-\r
- mov r2, #0xD3\r
- msr cpsr_c, r2\r
- ldr sp, svc\r
-\r
-\r
-CopyInitializedData:\r
+/* Initialize core registers.\r
+ This is done to avoid mismatch between lockstep CPU and ordinary CPU\r
+*/\r
+ mov r0, #0x0000\r
+ mov r1, #0x0000\r
+ mov r2, #0x0000\r
+ mov r3, #0x0000\r
+ mov r4, #0x0000\r
+ mov r5, #0x0000\r
+ mov r6, #0x0000\r
+ mov r7, #0x0000\r
+ mov r8, #0x0000\r
+ mov r9, #0x0000\r
+ mov r10, #0x0000\r
+ mov r11, #0x0000\r
+ mov r12, #0x0000\r
+ mov r1, #0x03D0\r
+ orr r2, r1, #0x0001\r
+ msr cpsr_cxsf, r2\r
+ msr spsr_cxsf, r2\r
+ mov r8, #0x0000\r
+ mov r9, #0x0000\r
+ mov r10, #0x0000\r
+ mov r11, #0x0000\r
+ mov r12, #0x0000\r
+ orr r12, r1, #0x0002\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+ orr r12, r1, #0x0007\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+ orr r12, r1, #0x000B\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+ orr r12, r1, #0x0003\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+\r
+/* System level configuration\r
+ This mainly involves setting instruction mode for exceptions and interrupts.\r
+*/\r
+ mrc p15,0,r11,c1,c0,0 /* Read current system configuration */ /* read System Control Register (SCTLR) */\r
+ mov r12, #0x40000000 /* Set THUMB instruction set mode for interrupts and exceptions */\r
+ orr r12, r12, r11\r
+ mcr p15,0,r12,c1,c0,0 /* Write new configuration */ /* write SCTLR */\r
+\r
+\r
+/* Initialize stack pointers.\r
+ This is done for all processor modes. Note that we only use one stack pointer.\r
+ In reality this means that no mode except USER and SYS is allowed to do anythin on the stack.\r
+ IRQ mode handles its own stack in the interrupt routine.\r
+*/\r
+ mov r2, #0xD1\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xD2\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xD7\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xDB\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xDF\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xD3\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+\r
+/* Initialize RAM.\r
+ First the initialized RAM is copied from flash to RAM.\r
+ Then the zeroed RAM is erased.\r
+*/\r
ldr r0, =_sdata /* r0 holds start of data in ram */\r
ldr r3, =_edata /* r3 holds end of data in ram */\r
ldr r5, =_sidata /* r5 start of data in flash */\r
bcc FillZero\r
bx lr\r
\r
-Dummy_Irq:\r
- nop\r
- nop\r
- b Dummy_Irq\r
-\r
.size Reset_Handler, .-Reset_Handler\r
\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
+\r
\r
\r
/******************************************************************************\r
******************************************************************************/ \r
.section .int_vecs,"ax",%progbits\r
.extern Irq_Handler\r
-\r
- b Dummy_Irq /* Reset? */\r
- b Dummy_Irq /* Undef? */\r
- b Dummy_Irq /* SVC */\r
- b Dummy_Irq /* Prefetch */\r
- b Dummy_Irq /* data */\r
- b Dummy_Irq /* ? */\r
- b Irq_Handler /* IRQ */\r
- b Irq_Handler /* FIR */\r
+ .extern Svc_Handler\r
+ .extern Data_Exc_Handler\r
+ .extern Prefetch_Exc_Handler\r
+ .extern Dummy_Irq\r
+\r
+ /* This is the reset handler. Since the CPU is in ARM mode when this instruction is executed\r
+ it has to be hard coded (otherwise it will compile wrong).\r
+ Instruction branches to address 0x22 while changing instruction mode to THUMB. */\r
+ .word 0xfb000006\r
+\r
+ b Dummy_Irq /* Undefined instruction exception */\r
+ b Dummy_Irq /* SVC */\r
+ b Prefetch_Exc_Handler /* Prefetch exception */\r
+ b Data_Exc_Handler /* Data exception */\r
+ b Dummy_Irq /* Reserved */\r
+ b Irq_Handler /* Ordinary interrupts (IRQ) */\r
+ b Dummy_Irq /* Fast interrupts (FIR) */\r
+\r
+ nop\r
+ b Reset_Handler /* Branch to the real reset handler. */\r
\r
projects / arc.git / blobdiff