1 /* -------------------------------- Arctic Core ------------------------------
2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
6 * This source code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by the
8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * -------------------------------- Arctic Core ------------------------------*/
30 * General configuration
33 // Maximum amount of data that can be written/read in one go.
34 #define SPI_EB_MAX_LENGTH 64
36 // Switches the Spi_Cancel function ON or OFF.
37 #define SPI_CANCEL_API STD_OFF
39 // Selects the SPI Handler/Driver Channel Buffers usage allowed and delivered.
40 // LEVEL 0 - Only Internal buffers
41 // LEVEL 1 - Only external buffers
42 // LEVEL 2 - Both internal/external buffers
43 #define SPI_CHANNEL_BUFFERS_ALLOWED 1
45 #define SPI_DEV_ERROR_DETECT STD_ON
46 // Switches the Spi_GetHWUnitStatus function ON or OFF.
47 #define SPI_HW_STATUS_API STD_ON
48 // Switches the Interruptible Sequences handling functionality ON or OFF.
49 #define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_OFF
51 // LEVEL 0 - Simple sync
52 // LEVEL 1 - Basic async
53 // LEVEL 2 - Enhanced mode
54 #define SPI_LEVEL_DELIVERED 2
56 #define SPI_VERSION_INFO_API STD_ON
59 #if SPI_LEVEL_DELIVERED>=1
60 #define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_ON
66 } Spi_ExternalDeviceTypeType;
68 #define SPI_CH_E2_CMD 0
69 #define SPI_CH_E2_ADDR 1
70 #define SPI_CH_E2_WREN 2
71 #define SPI_CH_E2_DATA 3
73 #define SPI_JOB_E2_CMD 0
74 #define SPI_JOB_E2_CMD2 1
75 #define SPI_JOB_E2_DATA 2
76 #define SPI_JOB_E2_WREN 3
78 #define SPI_SEQ_E2_CMD 0
79 #define SPI_SEQ_E2_CMD2 1
80 #define SPI_SEQ_E2_READ 2
81 #define SPI_SEQ_E2_WRITE 3
84 #define SPI_MAX_CHANNEL 4
85 #define SPI_MAX_SEQUENCE 4