4 #if defined(CFG_MPC5604B)
\r
5 flash: org = 0x00000000, len = 0x00080000
\r
6 #elif defined(CFG_MPC5607B)
\r
7 flash: org = 0x00000000, len = 0x00180000
\r
9 flash: org = 0x00000000, len = 0x00100000
\r
11 #if defined(CFG_MPC5606B)
\r
12 sram: org = 0x40000000, len = 0x00014000
\r
13 #elif defined(CFG_MPC5607B)
\r
14 sram: org = 0x40000000, len = 0x00018000
\r
16 sram: org = 0x40000000, len = 0x0000c000
\r
25 .exception_tbl (VLECODE) : {}
\r
26 #if defined(CFG_VLE)
\r
27 .text_vle (VLECODE) ALIGN(0x1000): {
\r
34 .init_vle (VLECODE) : {
\r
59 .sdata2 : {} /* SHF_ALLOC + possibly SHF_WRITE (prob. ReadOnly)*/
\r
60 .sbss2 : {} /* SHF_ALLOC + SHF_WRITE , e.g const int apa = 0;*/
\r
61 . = ALIGN(0x10); /* Section alignment is 0x10 */
\r
64 . = ALIGN(0x10); /* Section alignment is 0x10 */
\r
67 . = ALIGN(0x10); /* Section alignment is 0x10 */
\r
69 .=.+SIZEOF(.PPC.EMB.sdata0);
\r
76 .data (DATA) LOAD(ADDR(__DATA_ROM)) : {}
\r
77 .sdata (DATA) LOAD(ADDR(__SDATA)): {} /* .sdata - Initialized small data */
\r
83 .sbss : {} /* sbss - un-initialized small data */
\r
86 .PPC.EMB.sdata0 LOAD(ADDR(__SDATA0)) : {} /* Small data with offset to 0 */
\r
88 .ramlog : { *(.ramlog_data) *(.ramlog_bss) }
\r
89 .dem : { *(.dem_eventmemory_pri) }
\r
95 _heap_end = ADDR(sram)+SIZEOF(sram);
\r
96 _heap_size = _heap_end - _heap_addr;
\r
97 __SP_INIT = _heap_end;
\r