1 /* -------------------------------- Arctic Core ------------------------------
\r
2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
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4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
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6 * This source code is free software; you can redistribute it and/or modify it
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7 * under the terms of the GNU General Public License version 2 as published by the
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8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
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10 * This program is distributed in the hope that it will be useful, but
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11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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14 * -------------------------------- Arctic Core ------------------------------*/
\r
24 * End-Of-Interrupt. Called by the OS it wants to clear the interrupt.
\r
26 void Irq_EOI( void );
\r
31 /* Software interrupts. */
\r
32 INTC_SSCIR0_CLR0, // 0
\r
33 INTC_SSCIR0_CLR1, // 1
\r
34 INTC_SSCIR0_CLR2, // 2
\r
35 INTC_SSCIR0_CLR3, // 3
\r
36 INTC_SSCIR0_CLR4, // 4
\r
37 INTC_SSCIR0_CLR5, // 5
\r
38 INTC_SSCIR0_CLR6, // 6
\r
39 INTC_SSCIR0_CLR7, // 7
\r
40 #if defined(CFG_MPC560X)
\r
41 RESERVED0, // 5606-8
\r
45 DMA_COMBINED_ERROR_INT, // 5606-10
\r
46 DMA_CH0_INT, // 5606-11
\r
47 DMA_CH1_INT, // 5606-12
\r
48 DMA_CH2_INT, // 5606-13
\r
49 DMA_CH3_INT, // 5606-14
\r
50 DMA_CH4_INT, // 5606-15
\r
51 DMA_CH5_INT, // 5606-16
\r
52 DMA_CH6_INT, // 5606-17
\r
53 DMA_CH7_INT, // 5606-18
\r
54 DMA_CH8_INT, // 5606-19
\r
55 DMA_CH9_INT, // 5606-20
\r
56 DMA_CH10_INT, // 5606-21
\r
57 DMA_CH11_INT, // 5606-22
\r
58 DMA_CH12_INT, // 5606-23
\r
59 DMA_CH13_INT, // 5606-24
\r
60 DMA_CH14_INT, // 5606-25
\r
61 DMA_CH15_INT, // 5606-26
\r
63 RESERVED1, // 5606-27
\r
65 SWT_TIMEOUT, // 5606-28
\r
67 RESERVED2, // 5606-29
\r
69 STM_CH0_INT, // 5606-30
\r
70 STM_CH1_INT, // 5606-31
\r
71 STM_CH2_INT, // 5606-32
\r
72 STM_CH3_INT, // 5606-33
\r
74 RESERVED3, // 5606-34
\r
76 ECC_DBD_INT, // 5606-35
\r
77 ECC_SBC_INT, // 5606-36
\r
79 RESERVED4, // 5606-37
\r
84 RESERVED5, // 5606-40
\r
86 SIU_EXT_IRQ0, // 5606-41
\r
87 SIU_EXT_IRQ1, // 5606-42
\r
89 RESERVED6, // 5606-43
\r
90 RESERVED7, // 5606-44
\r
91 RESERVED8, // 5606-45
\r
93 WAKEUP_IRQ0, // 5606-46
\r
94 WAKEUP_IRQ1, // 5606-47
\r
95 WAKEUP_IRQ2, // 5606-48
\r
97 RESERVED9, // 5606-49
\r
98 RESERVED10, // 5606-50
\r
100 SAFE_MODE_INT, // 5606-51
\r
101 MODE_TRAS_INT, // 5606-52
\r
102 INV_MODE_INT, // 5606-53
\r
103 INV_MODE_CONF_INT, // 5606-54
\r
105 RESERVED11, // 5606-55
\r
107 RESET_ALT_EVENT_INT, // 5606-56
\r
109 FXOSC_COUNTER_EXPIRED, // 5606-57
\r
111 RESERVED12, // 5606-58
\r
113 PIT_INT0, // 5606-59
\r
114 PIT_INT1, // 5606-60
\r
115 PIT_INT2, // 5606-61
\r
117 ADC_EOC_INT, // 5606-62
\r
118 ADC_ER_INT, // 5606-63
\r
119 ADC_WD_INT, // 5606-64
\r
121 FLEXCAN_0_ESR_ERR_INT, // 5606-65
\r
122 FLEXCAN_0_ESR_BOFF_INT, // 5606-66
\r
124 RESERVED13, // 5606-67
\r
126 FLEXCAN_0_BUF_00_03, // 5606-68
\r
127 FLEXCAN_0_BUF_04_07, // 5606-69
\r
128 FLEXCAN_0_BUF_08_11, // 5606-70
\r
129 FLEXCAN_0_BUF_12_15, // 5606-71
\r
130 FLEXCAN_0_BUF_16_31, // 5606-72
\r
131 FLEXCAN_0_BUF_32_63, // 5606-73
\r
133 DSPI_0_ISR_TFUF_RFOF, // 5606-74
\r
134 DSPI_0_ISR_EOQF, // 5606-75
\r
135 DSPI_0_ISR_TFFF, // 5606-76
\r
136 DSPI_0_ISR_TCF, // 5606-77
\r
137 DSPI_0_ISR_RFDF, // 5606-78
\r
139 LINFLEX_0_RXI, // 5606-79
\r
140 LINFLEX_0_TXI, // 5606-80
\r
141 LINFLEX_0_ERR, // 5606-81
\r
143 RESERVED14, // 5606-82
\r
144 RESERVED15, // 5606-83
\r
145 RESERVED16, // 5606-84
\r
147 FLEXCAN_1_ESR_ERR_INT, // 5606-85
\r
148 FLEXCAN_1_ESR_BOFF_INT, // 5606-86
\r
150 RESERVED17, // 5606-87
\r
152 FLEXCAN_1_BUF_00_03, // 5606-88
\r
153 FLEXCAN_1_BUF_04_07, // 5606-89
\r
154 FLEXCAN_1_BUF_08_11, // 5606-90
\r
155 FLEXCAN_1_BUF_12_15, // 5606-91
\r
156 FLEXCAN_1_BUF_16_31, // 5606-92
\r
157 FLEXCAN_1_BUF_32_63, // 5606-93
\r
159 DSPI_1_ISR_TFUF_RFOF, // 5606-94
\r
160 DSPI_1_ISR_EOQF, // 5606-95
\r
161 DSPI_1_ISR_TFFF, // 5606-96
\r
162 DSPI_1_ISR_TCF, // 5606-97
\r
163 DSPI_1_ISR_RFDF, // 5606-98
\r
165 LINFLEX_1_RXI, // 5606-99
\r
166 LINFLEX_1_TXI, // 5606-100
\r
167 LINFLEX_1_ERR, // 5606-101
\r
169 RESERVED18, // 5606-102
\r
170 RESERVED19, // 5606-103
\r
171 RESERVED20, // 5606-104
\r
172 FLEXCAN_2_ESR_ERR_INT, // 5606-105
\r
173 FLEXCAN_2_ESR_BOFF_INT, // 5606-106
\r
175 RESERVED21, // 5606-107
\r
177 FLEXCAN_2_BUF_00_03, // 5606-108
\r
178 FLEXCAN_2_BUF_04_07, // 5606-109
\r
179 FLEXCAN_2_BUF_08_11, // 5606-110
\r
180 FLEXCAN_2_BUF_12_15, // 5606-111
\r
181 FLEXCAN_2_BUF_16_31, // 5606-112
\r
182 FLEXCAN_2_BUF_32_63, // 5606-113
\r
183 DSPI_2_ISR_TFUF_RFOF, // 5606-114
\r
184 DSPI_2_ISR_EOQF, // 5606-115
\r
185 DSPI_2_ISR_TFFF, // 5606-116
\r
186 DSPI_2_ISR_TCF, // 5606-117
\r
187 DSPI_2_ISR_RFDF, // 5606-118
\r
189 LINFLEX_2_RXI, // 5606-119
\r
190 LINFLEX_2_TXI, // 5606-120
\r
191 LINFLEX_2_ERR, // 5606-121
\r
192 LINFLEX_3_RXI, // 5606-122
\r
193 LINFLEX_3_TXI, // 5606-123
\r
194 LINFLEX_3_ERR, // 5606-124
\r
195 I2C_0_INT, // 5606-125
\r
196 I2C_1_INT, // 5606-126
\r
198 PIT_INT3, // 5606-127
\r
200 PIT_INT4, // 5606-128
\r
201 PIT_INT5, // 5606-129
\r
202 RESERVED43, // 5606-130
\r
203 RESERVED44, // 5606-131
\r
204 RESERVED45, // 5606-132
\r
205 RESERVED46, // 5606-133
\r
206 RESERVED47, // 5606-134
\r
207 RESERVED48, // 5606-135
\r
208 RESERVED49, // 5606-136
\r
209 RESERVED50, // 5606-137
\r
210 RESERVED51, // 5606-138
\r
211 RESERVED52, // 5606-139
\r
212 RESERVED53, // 5606-140
\r
213 #if defined (CFG_MPC5604B)
\r
214 EMIOS_0_GFR_F0_F1, // 5606-141
\r
215 EMIOS_0_GFR_F2_F3, // 5606-142
\r
216 EMIOS_0_GFR_F4_F5, // 5606-143
\r
217 EMIOS_0_GFR_F6_F7, // 5606-144
\r
218 EMIOS_0_GFR_F8_F9, // 5606-145
\r
219 EMIOS_0_GFR_F10_F11, // 5606-146
\r
220 EMIOS_0_GFR_F12_F13, // 5606-147
\r
221 EMIOS_0_GFR_F14_F15, // 5606-148
\r
222 EMIOS_0_GFR_F16_F17, // 5606-149
\r
223 EMIOS_0_GFR_F18_F19, // 5606-150
\r
224 EMIOS_0_GFR_F20_F21, // 5606-151
\r
225 EMIOS_0_GFR_F22_F23, // 5606-152
\r
226 EMIOS_0_GFR_F24_F25, // 5606-153
\r
227 EMIOS_0_GFR_F26_F27, // 5606-154
\r
228 RESERVED54, // 5606-155
\r
229 RESERVED55, // 5606-156
\r
230 EMIOS_1_GFR_F0_F1, // 5606-157
\r
231 EMIOS_1_GFR_F2_F3, // 5606-158
\r
232 EMIOS_1_GFR_F4_F5, // 5606-159
\r
233 EMIOS_1_GFR_F6_F7, // 5606-160
\r
234 EMIOS_1_GFR_F8_F9, // 5606-161
\r
235 EMIOS_1_GFR_F10_F11, // 5606-162
\r
236 EMIOS_1_GFR_F12_F13, // 5606-163
\r
237 EMIOS_1_GFR_F14_F15, // 5606-164
\r
238 EMIOS_1_GFR_F16_F17, // 5606-165
\r
239 EMIOS_1_GFR_F18_F19, // 5606-166
\r
240 EMIOS_1_GFR_F20_F21, // 5606-167
\r
241 EMIOS_1_GFR_F22_F23, // 5606-168
\r
242 EMIOS_1_GFR_F24_F25, // 5606-169
\r
243 EMIOS_1_GFR_F26_F27, // 5606-170
\r
245 RESERVED56, // 5606-171
\r
246 RESERVED57, // 5606-172
\r
248 FLEXCAN_3_ESR_ERR_INT, // 5606-173
\r
249 FLEXCAN_3_ESR_BOFF_INT, // 5606-174
\r
251 RESERVED58, // 5606-175
\r
253 FLEXCAN_3_BUF_00_03, // 5606-176
\r
254 FLEXCAN_3_BUF_04_07, // 5606-177
\r
255 FLEXCAN_3_BUF_08_11, // 5606-178
\r
256 FLEXCAN_3_BUF_12_15, // 5606-179
\r
257 FLEXCAN_3_BUF_16_31, // 5606-180
\r
258 FLEXCAN_3_BUF_32_63, // 5606-181
\r
259 RESERVED59, // 5606-182
\r
260 RESERVED60, // 5606-183
\r
261 RESERVED61, // 5606-184
\r
262 RESERVED62, // 5606-185
\r
263 RESERVED63, // 5606-186
\r
264 RESERVED64, // 5606-187
\r
265 RESERVED65, // 5606-188
\r
266 RESERVED66, // 5606-189
\r
267 FLEXCAN_4_ESR_ERR_INT, // 5606-190
\r
268 FLEXCAN_4_ESR_BOFF_INT, // 5606-191
\r
270 RESERVED67, // 5606-192
\r
272 FLEXCAN_4_BUF_00_03, // 5606-193
\r
273 FLEXCAN_4_BUF_04_07, // 5606-194
\r
274 FLEXCAN_4_BUF_08_11, // 5606-195
\r
275 FLEXCAN_4_BUF_12_15, // 5606-196
\r
276 FLEXCAN_4_BUF_16_31, // 5606-197
\r
277 FLEXCAN_4_BUF_32_63, // 5606-198
\r
278 RESERVED68, // 5606-199
\r
279 RESERVED69, // 5606-200
\r
280 RESERVED70, // 5606-201
\r
281 FLEXCAN_5_ESR_ERR_INT, // 5606-202
\r
282 FLEXCAN_5_ESR_BOFF_INT, // 5606-203
\r
283 RESERVED71, // 5606-204
\r
284 FLEXCAN_5_BUF_00_03, // 5606-205
\r
285 FLEXCAN_5_BUF_04_07, // 5606-206
\r
286 FLEXCAN_5_BUF_08_11, // 5606-207
\r
287 FLEXCAN_5_BUF_12_15, // 5606-208
\r
288 FLEXCAN_5_BUF_16_31, // 5606-209
\r
289 FLEXCAN_5_BUF_32_63, // 5606-210
\r
290 RESERVED72, // 5606-211
\r
291 RESERVED73, // 5606-212
\r
292 RESERVED74, // 5606-213
\r
293 RESERVED75, // 5606-214
\r
294 RESERVED76, // 5606-215
\r
295 RESERVED77, // 5606-216
\r
296 #elif defined (CFG_MPC5606S)
\r
297 EMIOS_0_GFR_F8_F9, // 5606-141
\r
298 EMIOS_0_GFR_F10_F11, // 5606-142
\r
299 EMIOS_0_GFR_F12_F13, // 5606-143
\r
300 EMIOS_0_GFR_F14_F15, // 5606-144
\r
301 EMIOS_0_GFR_F16_F17, // 5606-145
\r
302 EMIOS_0_GFR_F18_F19, // 5606-146
\r
303 EMIOS_0_GFR_F20_F21, // 5606-147
\r
304 EMIOS_0_GFR_F22_F23, // 5606-148
\r
306 RESERVED54, // 5606-149
\r
307 RESERVED55, // 5606-150
\r
308 RESERVED56, // 5606-151
\r
309 RESERVED57, // 5606-152
\r
310 RESERVED58, // 5606-153
\r
311 RESERVED59, // 5606-154
\r
312 RESERVED60, // 5606-155
\r
313 RESERVED61, // 5606-156
\r
315 EMIOS_1_GFR_F16_F17, // 5606-157
\r
316 EMIOS_1_GFR_F18_F19, // 5606-158
\r
317 EMIOS_1_GFR_F20_F21, // 5606-159
\r
318 EMIOS_1_GFR_F22_F23, // 5606-160
\r
320 RESERVED62, // 5606-161
\r
321 RESERVED63, // 5606-162
\r
322 RESERVED64, // 5606-163
\r
323 RESERVED65, // 5606-164
\r
324 RESERVED66, // 5606-165
\r
325 RESERVED67, // 5606-166
\r
326 RESERVED68, // 5606-167
\r
327 RESERVED69, // 5606-168
\r
328 RESERVED70, // 5606-169
\r
329 RESERVED71, // 5606-170
\r
330 RESERVED72, // 5606-171
\r
331 RESERVED73, // 5606-172
\r
333 I2C_2_INT, // 5606-173
\r
334 I2C_3_INT, // 5606-174
\r
336 RESERVED74, // 5606-175
\r
337 RESERVED75, // 5606-176
\r
338 RESERVED76, // 5606-177
\r
339 RESERVED77, // 5606-178
\r
340 RESERVED78, // 5606-179
\r
341 RESERVED79, // 5606-180
\r
342 RESERVED80, // 5606-181
\r
343 RESERVED81, // 5606-182
\r
345 SDCI_INT, // 5606-183
\r
346 DCUN0_VSYNC_INT, // 5606-184
\r
347 DCUN0_UNDRUN, // 5606-185
\r
348 DCUN0_PARERR, // 5606-186
\r
349 DCUN0_PDI, // 5606-187
\r
351 RESERVED82, // 5606-188
\r
352 RESERVED83, // 5606-189
\r
353 RESERVED84, // 5606-190
\r
354 RESERVED85, // 5606-191
\r
356 SMD0_INT, // 5606-192
\r
357 SSD0_INT, // 5606-193
\r
358 SSD1_INT, // 5606-194
\r
359 SSD2_INT, // 5606-195
\r
360 SSD3_INT, // 5606-196
\r
361 SSD4_INT, // 5606-197
\r
362 SSD5_INT, // 5606-198
\r
364 LCD0_EOF_INT, // 5606-199
\r
366 RESERVED86, // 5606-200
\r
368 QSPI0_TFUF, // 5606-201
\r
369 QSPI0_EOQF, // 5606-202
\r
370 QSPI0_TFFF, // 5606-203
\r
371 QSPI0_TCF, // 5606-204
\r
372 QSPI0_RFDF, // 5606-205
\r
373 QSPI0_IPAEF, // 5606-206
\r
376 INTC_NUMBER_OF_INTERRUPTS,
\r
378 MCM_MSWTIR_SWTIC, // 8
\r
379 ECC_ERROR, // 9, some variant call it MCM_ESR_COMB
\r
381 EDMA_ERRL_ERR31_0, // 10
\r
382 EDMA_INTL_INT0, // 11
\r
397 EDMA_INTL_INT15, // 26
\r
398 #if defined(CFG_MPC5554)||defined(CFG_MPC5567) ||defined(CFG_MPC5668)
\r
402 EDMA_INTL_INT19, // 30
\r
414 EDMA_INTL_INT31, // 42
\r
434 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
436 SEMAPHORE_INT0, // 43
\r
439 CRP_INTERRUPT, // API/RTC interrupt
\r
444 PLL_SYNSR_LOCF, // 54-43, 16-50
\r
445 PLL_SYNSR_LOLF, // 54-44, 16-51
\r
447 /* External interrupts */
\r
448 SIU_EISR_EIF0, // 53
\r
452 SIU_EISR_EIF15_4, // 54-50, 57
\r
455 EMISOS200_FLAG_F0, // 58
\r
465 EMISOS200_FLAG_F10,
\r
466 EMISOS200_FLAG_F11,
\r
467 EMISOS200_FLAG_F12,
\r
468 EMISOS200_FLAG_F13,
\r
469 EMISOS200_FLAG_F14,
\r
470 EMISOS200_FLAG_F15, // 73
\r
471 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
472 EMISOS200_FLAG_F16,
\r
473 EMISOS200_FLAG_F17,
\r
474 EMISOS200_FLAG_F18,
\r
475 EMISOS200_FLAG_F19,
\r
476 EMISOS200_FLAG_F20,
\r
477 EMISOS200_FLAG_F21,
\r
478 EMISOS200_FLAG_F22,
\r
479 EMISOS200_FLAG_F23, // 16-81
\r
480 #elif defined(CFG_MPC5554)||defined(CFG_MPC5567)
\r
481 ETPU_GLOBAL, // 54-67
\r
484 ETPU_A_CIS_2, // 54-70
\r
494 ETPU_A_CIS_12, // 54-80
\r
504 ETPU_A_CIS_22, // 54-90
\r
513 ETPU_A_CIS_31, // 99
\r
515 #if defined(CFG_MPC5668)
\r
550 EQADC_FISR_OVER, // 54-100, 16-82
\r
560 EQADC_FISR1_RFDF1, // 110, 92
\r
570 EQADC_FISR3_RFDF3, // 120, 102
\r
580 EQADC_FISR5_RFDF5, // 130, 112
\r
583 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
585 SCI_A_COMB, // 16-113
\r
595 DSPI_B_ISR_OVER, // 16-122
\r
600 #elif defined(CFG_MPC5554)||defined(CFG_MPC5567)
\r
601 DSPI_B_COMB, // 54-131
\r
605 DSPI_B_ISR_RFDF, // 54-135
\r
610 DSPI_C_ISR_RFDF, // 54-140
\r
615 DSPI_D_ISR_RFDF, // 54-145
\r
622 RESERVED3, // 54-151
\r
626 #if defined(CFG_MPC5516) || defined(CFG_MPC5554)||defined(CFG_MPC5567) || defined(CFG_MPC5668)
\r
627 FLEXCAN_A_ESR_BOFF_INT, // 54-152, 16-127
\r
628 FLEXCAN_A_ESR_ERR_INT,
\r
630 FLEXCAN_A_IFLAG1_BUF0I,
\r
631 FLEXCAN_A_IFLAG1_BUF1I,
\r
632 FLEXCAN_A_IFLAG1_BUF2I,
\r
633 FLEXCAN_A_IFLAG1_BUF3I,
\r
634 FLEXCAN_A_IFLAG1_BUF4I,
\r
635 FLEXCAN_A_IFLAG1_BUF5I,
\r
636 FLEXCAN_A_IFLAG1_BUF6I,
\r
637 FLEXCAN_A_IFLAG1_BUF7I,
\r
638 FLEXCAN_A_IFLAG1_BUF8I,
\r
639 FLEXCAN_A_IFLAG1_BUF9I,
\r
640 FLEXCAN_A_IFLAG1_BUF10I,
\r
641 FLEXCAN_A_IFLAG1_BUF11I,
\r
642 FLEXCAN_A_IFLAG1_BUF12I,
\r
643 FLEXCAN_A_IFLAG1_BUF13I,
\r
644 FLEXCAN_A_IFLAG1_BUF14I,
\r
645 FLEXCAN_A_IFLAG1_BUF15I,
\r
646 FLEXCAN_A_IFLAG1_BUF31_16I,
\r
647 FLEXCAN_A_IFLAG1_BUF63_32I, // 16 - 147
\r
650 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
651 /* Periodic interrupt timer */
\r
652 PIT_PITFLG_RTIF, // 16 - 148
\r
663 FLEXCAN_B_ESR_BOFF_INT,
\r
664 FLEXCAN_B_ESR_ERR_INT,
\r
666 FLEXCAN_B_IFLAG1_BUF0I,
\r
667 FLEXCAN_B_IFLAG1_BUF1I,
\r
668 FLEXCAN_B_IFLAG1_BUF2I,
\r
669 FLEXCAN_B_IFLAG1_BUF3I,
\r
670 FLEXCAN_B_IFLAG1_BUF4I,
\r
671 FLEXCAN_B_IFLAG1_BUF5I,
\r
672 FLEXCAN_B_IFLAG1_BUF6I,
\r
673 FLEXCAN_B_IFLAG1_BUF7I,
\r
674 FLEXCAN_B_IFLAG1_BUF8I,
\r
675 FLEXCAN_B_IFLAG1_BUF9I,
\r
676 FLEXCAN_B_IFLAG1_BUF10I,
\r
677 FLEXCAN_B_IFLAG1_BUF11I,
\r
678 FLEXCAN_B_IFLAG1_BUF12I,
\r
679 FLEXCAN_B_IFLAG1_BUF13I,
\r
680 FLEXCAN_B_IFLAG1_BUF14I,
\r
681 FLEXCAN_B_IFLAG1_BUF15I,
\r
682 FLEXCAN_B_IFLAG1_BUF31_16I,
\r
683 FLEXCAN_B_IFLAG1_BUF63_32I,
\r
685 FLEXCAN_C_ESR_BOFF_INT,
\r
686 FLEXCAN_C_ESR_ERR_INT,
\r
688 FLEXCAN_C_IFLAG1_BUF0I,
\r
689 FLEXCAN_C_IFLAG1_BUF1I,
\r
690 FLEXCAN_C_IFLAG1_BUF2I,
\r
691 FLEXCAN_C_IFLAG1_BUF3I,
\r
692 FLEXCAN_C_IFLAG1_BUF4I,
\r
693 FLEXCAN_C_IFLAG1_BUF5I,
\r
694 FLEXCAN_C_IFLAG1_BUF6I,
\r
695 FLEXCAN_C_IFLAG1_BUF7I,
\r
696 FLEXCAN_C_IFLAG1_BUF8I,
\r
697 FLEXCAN_C_IFLAG1_BUF9I,
\r
698 FLEXCAN_C_IFLAG1_BUF10I,
\r
699 FLEXCAN_C_IFLAG1_BUF11I,
\r
700 FLEXCAN_C_IFLAG1_BUF12I,
\r
701 FLEXCAN_C_IFLAG1_BUF13I,
\r
702 FLEXCAN_C_IFLAG1_BUF14I,
\r
703 FLEXCAN_C_IFLAG1_BUF15I,
\r
704 FLEXCAN_C_IFLAG1_BUF31_16I,
\r
705 FLEXCAN_C_IFLAG1_BUF63_32I,
\r
707 FLEXCAN_D_ESR_BOFF_INT,
\r
708 FLEXCAN_D_ESR_ERR_INT,
\r
710 FLEXCAN_D_IFLAG1_BUF0I,
\r
711 FLEXCAN_D_IFLAG1_BUF1I,
\r
712 FLEXCAN_D_IFLAG1_BUF2I,
\r
713 FLEXCAN_D_IFLAG1_BUF3I,
\r
714 FLEXCAN_D_IFLAG1_BUF4I,
\r
715 FLEXCAN_D_IFLAG1_BUF5I,
\r
716 FLEXCAN_D_IFLAG1_BUF6I,
\r
717 FLEXCAN_D_IFLAG1_BUF7I,
\r
718 FLEXCAN_D_IFLAG1_BUF8I,
\r
719 FLEXCAN_D_IFLAG1_BUF9I,
\r
720 FLEXCAN_D_IFLAG1_BUF10I,
\r
721 FLEXCAN_D_IFLAG1_BUF11I,
\r
722 FLEXCAN_D_IFLAG1_BUF12I,
\r
723 FLEXCAN_D_IFLAG1_BUF13I,
\r
724 FLEXCAN_D_IFLAG1_BUF14I,
\r
725 FLEXCAN_D_IFLAG1_BUF15I,
\r
726 FLEXCAN_D_IFLAG1_BUF31_16I,
\r
727 FLEXCAN_D_IFLAG1_BUF63_32I,
\r
729 FLEXCAN_E_ESR_BOFF_INT,
\r
730 FLEXCAN_E_ESR_ERR_INT,
\r
732 FLEXCAN_E_IFLAG1_BUF0I,
\r
733 FLEXCAN_E_IFLAG1_BUF1I,
\r
734 FLEXCAN_E_IFLAG1_BUF2I,
\r
735 FLEXCAN_E_IFLAG1_BUF3I,
\r
736 FLEXCAN_E_IFLAG1_BUF4I,
\r
737 FLEXCAN_E_IFLAG1_BUF5I,
\r
738 FLEXCAN_E_IFLAG1_BUF6I,
\r
739 FLEXCAN_E_IFLAG1_BUF7I,
\r
740 FLEXCAN_E_IFLAG1_BUF8I,
\r
741 FLEXCAN_E_IFLAG1_BUF9I,
\r
742 FLEXCAN_E_IFLAG1_BUF10I,
\r
743 FLEXCAN_E_IFLAG1_BUF11I,
\r
744 FLEXCAN_E_IFLAG1_BUF12I,
\r
745 FLEXCAN_E_IFLAG1_BUF13I,
\r
746 FLEXCAN_E_IFLAG1_BUF14I,
\r
747 FLEXCAN_E_IFLAG1_BUF15I,
\r
748 FLEXCAN_E_IFLAG1_BUF31_16I,
\r
749 FLEXCAN_E_IFLAG1_BUF63_32I,
\r
751 FLEXCAN_F_ESR_BOFF_INT,
\r
752 FLEXCAN_F_ESR_ERR_INT,
\r
754 FLEXCAN_F_IFLAG1_BUF0I,
\r
755 FLEXCAN_F_IFLAG1_BUF1I,
\r
756 FLEXCAN_F_IFLAG1_BUF2I,
\r
757 FLEXCAN_F_IFLAG1_BUF3I,
\r
758 FLEXCAN_F_IFLAG1_BUF4I,
\r
759 FLEXCAN_F_IFLAG1_BUF5I,
\r
760 FLEXCAN_F_IFLAG1_BUF6I,
\r
761 FLEXCAN_F_IFLAG1_BUF7I,
\r
762 FLEXCAN_F_IFLAG1_BUF8I,
\r
763 FLEXCAN_F_IFLAG1_BUF9I,
\r
764 FLEXCAN_F_IFLAG1_BUF10I,
\r
765 FLEXCAN_F_IFLAG1_BUF11I,
\r
766 FLEXCAN_F_IFLAG1_BUF12I,
\r
767 FLEXCAN_F_IFLAG1_BUF13I,
\r
768 FLEXCAN_F_IFLAG1_BUF14I,
\r
769 FLEXCAN_F_IFLAG1_BUF15I,
\r
770 FLEXCAN_F_IFLAG1_BUF31_16I,
\r
771 FLEXCAN_F_IFLAG1_BUF63_32I,
\r
772 #if defined(CFG_MPC5668)
\r
792 SCI_E_COMB, // 68-270
\r
817 MLB_SERVICE_REQUEST,
\r
818 #if defined(MPC5668)
\r
842 INTC_NUMBER_OF_INTERRUPTS,
\r
845 #if defined(CFG_MPC5554)||defined(CFG_MPC5567)
\r
847 FLEXCAN_C_ESR_BOFF_INT = 173,
\r
848 FLEXCAN_C_ESR_ERR_INT,
\r
850 FLEXCAN_C_IFLAG1_BUF0I,
\r
851 FLEXCAN_C_IFLAG1_BUF1I,
\r
852 FLEXCAN_C_IFLAG1_BUF2I,
\r
853 FLEXCAN_C_IFLAG1_BUF3I,
\r
854 FLEXCAN_C_IFLAG1_BUF4I,
\r
855 FLEXCAN_C_IFLAG1_BUF5I,
\r
856 FLEXCAN_C_IFLAG1_BUF6I,
\r
857 FLEXCAN_C_IFLAG1_BUF7I,
\r
858 FLEXCAN_C_IFLAG1_BUF8I,
\r
859 FLEXCAN_C_IFLAG1_BUF9I,
\r
860 FLEXCAN_C_IFLAG1_BUF10I,
\r
861 FLEXCAN_C_IFLAG1_BUF11I,
\r
862 FLEXCAN_C_IFLAG1_BUF12I,
\r
863 FLEXCAN_C_IFLAG1_BUF13I,
\r
864 FLEXCAN_C_IFLAG1_BUF14I,
\r
865 FLEXCAN_C_IFLAG1_BUF15I,
\r
866 FLEXCAN_C_IFLAG1_BUF31_16I,
\r
867 FLEXCAN_C_IFLAG1_BUF63_32I, // 193
\r
870 #if defined(CFG_MPC5567)
\r
877 DSPI_A_COMB = 275, // 54-131
\r
881 DSPI_A_ISR_RFDF, // 54-135
\r
884 FLEXCAN_B_ESR_BOFF_INT = 280,
\r
885 FLEXCAN_B_ESR_ERR_INT,
\r
887 FLEXCAN_B_IFLAG1_BUF0I,
\r
888 FLEXCAN_B_IFLAG1_BUF1I,
\r
889 FLEXCAN_B_IFLAG1_BUF2I,
\r
890 FLEXCAN_B_IFLAG1_BUF3I,
\r
891 FLEXCAN_B_IFLAG1_BUF4I,
\r
892 FLEXCAN_B_IFLAG1_BUF5I,
\r
893 FLEXCAN_B_IFLAG1_BUF6I,
\r
894 FLEXCAN_B_IFLAG1_BUF7I,
\r
895 FLEXCAN_B_IFLAG1_BUF8I,
\r
896 FLEXCAN_B_IFLAG1_BUF9I,
\r
897 FLEXCAN_B_IFLAG1_BUF10I,
\r
898 FLEXCAN_B_IFLAG1_BUF11I,
\r
899 FLEXCAN_B_IFLAG1_BUF12I,
\r
900 FLEXCAN_B_IFLAG1_BUF13I,
\r
901 FLEXCAN_B_IFLAG1_BUF14I,
\r
902 FLEXCAN_B_IFLAG1_BUF15I,
\r
903 FLEXCAN_B_IFLAG1_BUF31_16I,
\r
904 FLEXCAN_B_IFLAG1_BUF63_32I,
\r
907 FLEXCAN_D_ESR_BOFF_INT = 308,
\r
908 FLEXCAN_D_ESR_ERR_INT,
\r
910 FLEXCAN_D_IFLAG1_BUF0I,
\r
911 FLEXCAN_D_IFLAG1_BUF1I,
\r
912 FLEXCAN_D_IFLAG1_BUF2I,
\r
913 FLEXCAN_D_IFLAG1_BUF3I,
\r
914 FLEXCAN_D_IFLAG1_BUF4I,
\r
915 FLEXCAN_D_IFLAG1_BUF5I,
\r
916 FLEXCAN_D_IFLAG1_BUF6I,
\r
917 FLEXCAN_D_IFLAG1_BUF7I,
\r
918 FLEXCAN_D_IFLAG1_BUF8I,
\r
919 FLEXCAN_D_IFLAG1_BUF9I,
\r
920 FLEXCAN_D_IFLAG1_BUF10I,
\r
921 FLEXCAN_D_IFLAG1_BUF11I,
\r
922 FLEXCAN_D_IFLAG1_BUF12I,
\r
923 FLEXCAN_D_IFLAG1_BUF13I,
\r
924 FLEXCAN_D_IFLAG1_BUF14I,
\r
925 FLEXCAN_D_IFLAG1_BUF15I,
\r
926 FLEXCAN_D_IFLAG1_BUF31_16I,
\r
927 FLEXCAN_D_IFLAG1_BUF63_32I,
\r
930 FLEXCAN_E_ESR_BOFF_INT = 329,
\r
931 FLEXCAN_E_ESR_ERR_INT,
\r
933 FLEXCAN_E_IFLAG1_BUF0I,
\r
934 FLEXCAN_E_IFLAG1_BUF1I,
\r
935 FLEXCAN_E_IFLAG1_BUF2I,
\r
936 FLEXCAN_E_IFLAG1_BUF3I,
\r
937 FLEXCAN_E_IFLAG1_BUF4I,
\r
938 FLEXCAN_E_IFLAG1_BUF5I,
\r
939 FLEXCAN_E_IFLAG1_BUF6I,
\r
940 FLEXCAN_E_IFLAG1_BUF7I,
\r
941 FLEXCAN_E_IFLAG1_BUF8I,
\r
942 FLEXCAN_E_IFLAG1_BUF9I,
\r
943 FLEXCAN_E_IFLAG1_BUF10I,
\r
944 FLEXCAN_E_IFLAG1_BUF11I,
\r
945 FLEXCAN_E_IFLAG1_BUF12I,
\r
946 FLEXCAN_E_IFLAG1_BUF13I,
\r
947 FLEXCAN_E_IFLAG1_BUF14I,
\r
948 FLEXCAN_E_IFLAG1_BUF15I,
\r
949 FLEXCAN_E_IFLAG1_BUF31_16I,
\r
950 FLEXCAN_E_IFLAG1_BUF63_32I,
\r
952 INTC_NUMBER_OF_INTERRUPTS,
\r
954 #endif /* defined(CFG_MPC5554)||defined(CFG_MPC5567) */
\r
956 CRITICAL_INPUT_EXCEPTION,
\r
957 MACHINE_CHECK_EXCEPTION,
\r
958 DATA_STORAGE_EXCEPTION,
\r
959 INSTRUCTION_STORAGE_EXCEPTION,
\r
960 EXTERNAL_INTERRUPT, /* This is the place where the "normal" interrupts will hit the CPU... */
\r
961 ALIGNMENT_EXCEPTION,
\r
963 FLOATING_POINT_EXCEPTION,
\r
964 SYSTEM_CALL_EXCEPTION,
\r
966 DECREMENTER_EXCEPTION,
\r
967 FIXED_INTERVAL_TIMER_EXCEPTION,
\r
968 WATCHDOG_TIMER_EXCEPTION,
\r
969 DATA_TLB_EXCEPTION,
\r
970 INSTRUCTION_TLB_EXCEPTION,
\r
972 NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS
\r
978 PERIPHERAL_CLOCK_FLEXCAN_A,
\r
979 PERIPHERAL_CLOCK_FLEXCAN_B,
\r
980 PERIPHERAL_CLOCK_FLEXCAN_C,
\r
981 PERIPHERAL_CLOCK_FLEXCAN_D,
\r
982 PERIPHERAL_CLOCK_FLEXCAN_E,
\r
983 PERIPHERAL_CLOCK_FLEXCAN_F,
\r
984 PERIPHERAL_CLOCK_PIT,
\r
985 PERIPHERAL_CLOCK_DSPI_A,
\r
986 PERIPHERAL_CLOCK_DSPI_B,
\r
987 PERIPHERAL_CLOCK_DSPI_C,
\r
988 PERIPHERAL_CLOCK_DSPI_D,
\r
989 #if defined(CFG_MPC560X)
\r
990 PERIPHERAL_CLOCK_EMIOS_0,
\r
991 PERIPHERAL_CLOCK_EMIOS_1,
\r
993 PERIPHERAL_CLOCK_EMIOS,
\r
995 PERIPHERAL_CLOCK_ESCI_A,
\r
996 PERIPHERAL_CLOCK_ESCI_B,
\r
997 PERIPHERAL_CLOCK_ESCI_C,
\r
998 PERIPHERAL_CLOCK_ESCI_D,
\r
999 PERIPHERAL_CLOCK_ESCI_E,
\r
1000 PERIPHERAL_CLOCK_ESCI_F,
\r
1001 PERIPHERAL_CLOCK_ESCI_G,
\r
1002 PERIPHERAL_CLOCK_ESCI_H,
\r
1003 #if defined(CFG_MPC560X)
\r
1004 PERIPHERAL_CLOCK_LIN_A,
\r
1005 PERIPHERAL_CLOCK_LIN_B,
\r
1006 PERIPHERAL_CLOCK_LIN_C,
\r
1007 PERIPHERAL_CLOCK_LIN_D,
\r
1009 PERIPHERAL_CLOCK_IIC_A,
\r
1010 PERIPHERAL_CLOCK_IIC_B,
\r
1011 PERIPHERAL_CLOCK_MLB,
\r
1012 PERIPHERAL_CLOCK_ADC_A,
\r
1013 } McuE_PeriperalClock_t;
\r
1022 /* Offset from exceptions to interrupts */
\r
1023 #define IRQ_INTERRUPT_OFFSET 0
\r
1025 #endif /* IRQ_H_ */
\r