1 /* -------------------------------- Arctic Core ------------------------------
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2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
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4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
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6 * This source code is free software; you can redistribute it and/or modify it
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7 * under the terms of the GNU General Public License version 2 as published by the
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8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
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10 * This program is distributed in the hope that it will be useful, but
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11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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14 * -------------------------------- Arctic Core ------------------------------*/
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17 /* ----------------------------[includes]------------------------------------*/
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20 #include "Std_Types.h"
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23 #if defined(USE_DEM)
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26 #include "mpc55xx.h"
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33 //#define USE_LDEBUG_PRINTF 1
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36 /* ----------------------------[private define]------------------------------*/
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38 #define SYSCLOCK_SELECT_PLL 0x2
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41 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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42 #define CRP_BASE (0xFFFEC000ul)
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44 #error Please define CRP_BASE
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47 #define CRP_CLKSRC (CRP_BASE+0x0)
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48 #define CRP_RTCSC (CRP_BASE+0x10)
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49 #define CRP_RTCCNT (CRP_BASE+0x14)
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50 /* 40--4F differs ALOT */
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51 #define CRP_Z1VEC (CRP_BASE+0x50)
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52 #define CRP_Z6VEC (CRP_BASE+0x50)
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53 #define CRP_Z0VEC (CRP_BASE+0x54)
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54 #define CRP_RECPTR (CRP_BASE+0x58)
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55 #define CRP_PSCR (CRP_BASE+0x60)
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57 #define xVEC_xVEC(_x)
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58 #define PSCR_SLEEP 0x00008000ul
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59 #define PSCR_SLP12EN 0x00000800ul
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60 #define PCSR_RAMSEL(_x) ((_x)<<8)
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61 #define xVEC_VLE 0x00000001ul
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62 #define xVEC_xRST 0x00000002ul
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64 #define RECPTR_FASTREC 0x00000002ul
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67 #if defined(CFG_VLE)
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68 #define VLE_VAL xVEC_VLE
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73 #if defined(CFG_MPC5516 )
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74 #define RAMSEL_VAL 0x7
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75 #elif defined(CFG_MPC5668)
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76 #define RAMSEL_VAL 0x3
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78 #error Please define RAMSEL_VAL
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82 /* ----------------------------[private macro]-------------------------------*/
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85 #if defined(CFG_MPC5567)
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86 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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87 ( (_extal) * ((_emfd)+4) / (((_eprediv)+1)*(1<<(_erfd))) )
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88 #elif defined(CFG_MPC560X)
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89 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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90 ( (_extal)*(_emfd) / ((_eprediv+1)*(2<<(_erfd))) )
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92 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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93 ( (_extal) * ((_emfd)+16) / (((_eprediv)+1)*((_erfd)+1)) )
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96 /* ----------------------------[private typedef]-----------------------------*/
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99 typedef void (*vfunc_t)();
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102 /* ----------------------------[private function prototypes]-----------------*/
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103 /* ----------------------------[private variables]---------------------------*/
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105 #if defined(CFG_MPC5516)
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106 static uint32 Mcu_SavedHaltFlags;
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108 static uint32 Mcu_SavedHaltFlags[2];
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113 /* ----------------------------[private functions]---------------------------*/
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114 /* ----------------------------[public functions]----------------------------*/
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116 /* Function declarations. */
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117 static void Mcu_ConfigureFlash(void);
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120 uint32 lossOfLockCnt;
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121 uint32 lossOfClockCnt;
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125 * Type that holds all global data for Mcu
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129 // Set if Mcu_Init() have been called
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132 const Mcu_ConfigType *config;
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133 Mcu_ClockType clockSetting;
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137 /* Development error macros. */
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138 #if ( MCU_DEV_ERROR_DETECT == STD_ON )
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139 #define VALIDATE(_exp,_api,_err ) \
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141 Det_ReportError(MODULE_ID_MCU,0,_api,_err); \
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145 #define VALIDATE_W_RV(_exp,_api,_err,_rv ) \
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147 Det_ReportError(MODULE_ID_MCU,0,_api,_err); \
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151 #define VALIDATE(_exp,_api,_err )
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152 #define VALIDATE_W_RV(_exp,_api,_err,_rv )
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156 Mcu_GlobalType Mcu_Global =
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159 .config = &McuConfigData[0],
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162 //-------------------------------------------------------------------
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164 void Mcu_LossOfLock( void ){
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165 #if defined(USE_DEM)
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166 Dem_ReportErrorStatus(MCU_E_CLOCK_FAILURE, DEM_EVENT_STATUS_FAILED);
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171 * This interrupt may be triggered more than expected.
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172 * If you are going to use this interrupt, see [Freescale Device Errata MPC5510ACE, Rev. 10 APR 2009, errata ID: 6764].
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175 #if defined(CFG_MPC560X)
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178 Mcu_Global.stats.lossOfLockCnt++;
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180 FMPLL.SYNSR.B.LOLF = 1;
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184 //-------------------------------------------------------------------
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186 void Mcu_LossOfClock( void ){
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187 /* Should report MCU_E_CLOCK_FAILURE with DEM here */
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188 #if defined(CFG_MPC560X)
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191 Mcu_Global.stats.lossOfClockCnt++;
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193 FMPLL.SYNSR.B.LOCF = 1;
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197 #define SPR_PIR 286
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198 #define SPR_PVR 287
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200 #define CORE_PVR_E200Z1 0x81440000UL
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201 #define CORE_PVR_E200Z0 0x81710000UL
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202 #define CORE_PVR_E200Z3 0x81120000UL
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203 #define CORE_PVR_E200Z6 0x81170000UL
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204 #define CORE_PVR_E200Z65 0x81150000UL /* Is actually a 5668 */
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205 #define CORE_PVR_E200Z0H 0x817F0000UL
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217 const cpu_info_t cpu_info_list[] = {
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218 #if defined(CFG_MPC5516)
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221 .pvr = CORE_PVR_E200Z1,
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225 .pvr = CORE_PVR_E200Z0,
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227 #elif defined(CFG_MPC5567)
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230 .pvr = CORE_PVR_E200Z6,
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232 #elif defined(CFG_MPC5633)
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235 .pvr = CORE_PVR_E200Z3,
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237 #elif defined(CFG_MPC5604B)
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239 .name = "MPC5604B",
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240 .pvr = CORE_PVR_E200Z0H,
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242 #elif defined(CFG_MPC5606B)
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244 .name = "MPC5606B",
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245 .pvr = CORE_PVR_E200Z0H,
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247 #elif defined(CFG_MPC5606S)
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249 .name = "MPC5606S",
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250 .pvr = CORE_PVR_E200Z0H,
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252 #elif defined(CFG_MPC5668)
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255 .pvr = CORE_PVR_E200Z65,
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259 .pvr = CORE_PVR_E200Z0,
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264 const core_info_t core_info_list[] = {
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265 #if defined(CFG_MPC5516)
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267 .name = "CORE_E200Z1",
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268 .pvr = CORE_PVR_E200Z1,
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271 .name = "CORE_E200Z1",
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272 .pvr = CORE_PVR_E200Z1,
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274 #elif defined(CFG_MPC5567)
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276 .name = "CORE_E200Z6",
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277 .pvr = CORE_PVR_E200Z6,
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279 #elif defined(CFG_MPC5633)
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281 .name = "CORE_E200Z3",
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282 .pvr = CORE_PVR_E200Z3,
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284 #elif defined(CFG_MPC5604B)
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286 .name = "MPC5604B",
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287 .pvr = CORE_PVR_E200Z0H,
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289 #elif defined(CFG_MPC5606B)
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291 .name = "MPC5606B",
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292 .pvr = CORE_PVR_E200Z0H,
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294 #elif defined(CFG_MPC5606S)
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296 .name = "MPC5606S",
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297 .pvr = CORE_PVR_E200Z0H,
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299 #elif defined(CFG_MPC5668)
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301 .name = "CORE_E200Z65",
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302 .pvr = CORE_PVR_E200Z65,
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305 .name = "CORE_E200Z0",
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306 .pvr = CORE_PVR_E200Z1,
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312 #if !defined(ARRAY_SIZE)
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313 #define ARRAY_SIZE(_x) (sizeof(_x)/sizeof((_x)[0]))
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316 static const cpu_info_t *Mcu_IdentifyCpu(uint32 pvr)
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320 for (i = 0; i < ARRAY_SIZE(cpu_info_list); i++) {
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321 if (cpu_info_list[i].pvr == pvr) {
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322 return &cpu_info_list[i];
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329 static const core_info_t *Mcu_IdentifyCore(uint32 pvr)
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333 for (i = 0; i < ARRAY_SIZE(core_info_list); i++) {
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334 if (core_info_list[i].pvr == pvr) {
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335 return &core_info_list[i];
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342 static uint32 Mcu_CheckCpu( void ) {
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345 const cpu_info_t *cpuType;
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346 const core_info_t *coreType;
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348 // We have to registers to read here, PIR and PVR
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349 // pir = get_spr(SPR_PIR);
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350 pvr = get_spr(SPR_PVR);
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352 cpuType = Mcu_IdentifyCpu(pvr);
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353 coreType = Mcu_IdentifyCore(pvr);
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355 if( (cpuType == NULL) || (coreType == NULL) ) {
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360 //DEBUG(DEBUG_HIGH,"/drivers/mcu: Cpu: %s( 0x%08x )\n",cpuType->name,pvr);
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361 //DEBUG(DEBUG_HIGH,"/drivers/mcu: Core: %s( 0x%08x )\n",coreType->name,pvr);
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366 //-------------------------------------------------------------------
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368 void Mcu_Init(const Mcu_ConfigType *configPtr)
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370 VALIDATE( ( NULL != configPtr ), MCU_INIT_SERVICE_ID, MCU_E_PARAM_CONFIG );
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372 #if defined(CFG_MPC560X)
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373 /* Disable watchdog. Watchdog is enabled default after reset.*/
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374 SWT.SR.R = 0x0000c520; /* Write keys to clear soft lock bit */
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375 SWT.SR.R = 0x0000d928;
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376 SWT.CR.R = 0x8000010A; /* Disable watchdog */
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377 #if defined(USE_WDG)
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378 SWT.TO.R = 0xfa00; /* set the timout to 500ms */
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379 SWT.CR.R = 0x8000011B; /* enable watchdog */
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383 if( !SIMULATOR() ) {
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387 memset(&Mcu_Global.stats,0,sizeof(Mcu_Global.stats));
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390 Mcu_ConfigureFlash();
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392 Mcu_Global.config = configPtr;
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394 #if defined(CFG_MPC560X)
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395 /* Enable DRUN, RUN0, SAFE, RESET modes */
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396 ME.MER.R = 0x0000001D;
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399 Mcu_Global.initRun = 1;
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401 if( Mcu_Global.config->McuClockSrcFailureNotification == TRUE ) {
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402 #if defined(CFG_MPC560X)
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405 ISR_INSTALL_ISR1("LossOfLock", Mcu_LossOfLock, PLL_SYNSR_LOLF, 10 , 0 );
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406 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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407 FMPLL.ESYNCR2.B.LOLIRQ = 1;
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408 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
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409 FMPLL.SYNCR.B.LOLIRQ = 1;
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411 ISR_INSTALL_ISR1("LossOfClock", Mcu_LossOfClock, PLL_SYNSR_LOLF, 10 , 0 );
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412 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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413 FMPLL.ESYNCR2.B.LOCIRQ = 1;
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414 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
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415 FMPLL.SYNCR.B.LOCIRQ = 1;
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421 //-------------------------------------------------------------------
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425 Mcu_Global.initRun = FALSE; // Very simple Deinit. Should we do more?
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428 //-------------------------------------------------------------------
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430 Std_ReturnType Mcu_InitRamSection(const Mcu_RamSectionType RamSection)
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432 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );
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433 VALIDATE_W_RV( ( RamSection <= Mcu_Global.config->McuRamSectors ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_PARAM_RAMSECTION, E_NOT_OK );
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435 /* NOT SUPPORTED, reason: no support for external RAM */
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440 //-------------------------------------------------------------------
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442 Std_ReturnType Mcu_InitClock(const Mcu_ClockType ClockSetting)
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444 Mcu_ClockSettingConfigType *clockSettingsPtr;
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445 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITCLOCK_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );
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446 VALIDATE_W_RV( ( ClockSetting < Mcu_Global.config->McuClockSettings ), MCU_INITCLOCK_SERVICE_ID, MCU_E_PARAM_CLOCK, E_NOT_OK );
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448 Mcu_Global.clockSetting = ClockSetting;
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449 clockSettingsPtr = &Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting];
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451 // TODO: find out if the 5554 really works like the 5516 here
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452 // All three (16, 54, 67) used to run the same code here though, so i'm sticking it with 5516
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453 #if defined(CFG_SIMULATOR)
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455 #elif defined(CFG_MPC5516) || defined(CFG_MPC5554) || defined(CFG_MPC5668)
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457 * Fsys - System frequency ( CPU + all periperals? )
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459 * Fsys = EXTAL_FREQ *( (emfd+16) / ( (eprediv+1) * ( erfd+1 )) ) )
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462 assert((clockSettingsPtr->Pll2>=32) && (clockSettingsPtr->Pll2<=132));
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463 assert( (clockSettingsPtr->Pll1 != 6) &&
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464 (clockSettingsPtr->Pll1 != 8) &&
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465 (clockSettingsPtr->Pll1 < 10) );
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466 assert( clockSettingsPtr->Pll3 & 1); // Must be odd
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467 #elif defined(CFG_MPC5567)
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468 /* 5567 clock info:
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469 * Fsys = EXTAL_FREQ *( (emfd+4) / ( (eprediv+1) * ( 2^erfd )) ) )
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472 assert(clockSettingsPtr->Pll2 < 16);
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473 assert(clockSettingsPtr->Pll1 <= 4);
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474 assert(clockSettingsPtr->Pll3 < 8);
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477 #if defined(USE_LDEBUG_PRINTF)
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479 uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;
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482 f_sys = CALC_SYSTEM_CLOCK( extal,
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483 clockSettingsPtr->Pll2,
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484 clockSettingsPtr->Pll1,
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485 clockSettingsPtr->Pll3 );
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487 //DEBUG(DEBUG_HIGH,"/drivers/mcu: F_sys will be:%08d Hz\n",f_sys);
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491 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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493 // set post divider to next valid value to ensure that an overshoot during lock phase
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494 // won't result in a too high freq
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495 FMPLL.ESYNCR2.B.ERFD = (clockSettingsPtr->Pll3 + 1) | 1;
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497 // External crystal PLL mode.
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498 FMPLL.ESYNCR1.B.CLKCFG = 7; //TODO: Hur ställa detta för 5567?
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500 // Write pll parameters.
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501 FMPLL.ESYNCR1.B.EPREDIV = clockSettingsPtr->Pll1;
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502 FMPLL.ESYNCR1.B.EMFD = clockSettingsPtr->Pll2;
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504 while(FMPLL.SYNSR.B.LOCK != 1) {};
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506 FMPLL.ESYNCR2.B.ERFD = clockSettingsPtr->Pll3;
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507 // Connect SYSCLK to FMPLL
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508 SIU.SYSCLK.B.SYSCLKSEL = SYSCLOCK_SELECT_PLL;
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509 #elif defined(CFG_MPC5604B) || defined(CFG_MPC5606B)
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510 // Write pll parameters.
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511 CGM.FMPLL_CR.B.IDF = clockSettingsPtr->Pll1;
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512 CGM.FMPLL_CR.B.NDIV = clockSettingsPtr->Pll2;
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513 CGM.FMPLL_CR.B.ODF = clockSettingsPtr->Pll3;
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515 /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL0 */
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516 ME.RUN[0].R = 0x001F0074;
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517 /* Peri. Cfg. 1 settings: only run in RUN0 mode */
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518 ME.RUNPC[1].R = 0x00000010;
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519 /* MPC56xxB/S: select ME.RUNPC[1] */
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520 ME.PCTL[68].R = 0x01; //SIUL control
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521 ME.PCTL[91].R = 0x01; //RTC/API control
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522 ME.PCTL[92].R = 0x01; //PIT_RTI control
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523 ME.PCTL[72].R = 0x01; //eMIOS0 control
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524 ME.PCTL[73].R = 0x01; //eMIOS1 control
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525 ME.PCTL[16].R = 0x01; //FlexCAN0 control
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526 ME.PCTL[17].R = 0x01; //FlexCAN1 control
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527 ME.PCTL[4].R = 0x01; /* MPC56xxB/P/S DSPI0 */
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528 ME.PCTL[5].R = 0x01; /* MPC56xxB/P/S DSPI1: */
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529 ME.PCTL[32].R = 0x01; //ADC0 control
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530 #if defined(CFG_MPC5606B)
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531 ME.PCTL[33].R = 0x01; //ADC1 control
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533 ME.PCTL[23].R = 0x01; //DMAMUX control
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534 ME.PCTL[48].R = 0x01; /* MPC56xxB/P/S LINFlex */
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535 ME.PCTL[49].R = 0x01; /* MPC56xxB/P/S LINFlex */
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536 /* Mode Transition to enter RUN0 mode: */
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537 /* Enter RUN0 Mode & Key */
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538 ME.MCTL.R = 0x40005AF0;
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539 /* Enter RUN0 Mode & Inverted Key */
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540 ME.MCTL.R = 0x4000A50F;
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542 /* Wait for mode transition to complete */
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543 while (ME.GS.B.S_MTRANS) {}
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544 /* Verify RUN0 is the current mode */
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545 while(ME.GS.B.S_CURRENTMODE != 4) {}
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547 CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */
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548 CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */
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549 CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */
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551 SIU.PSMI[0].R = 0x01; /* CAN1RX on PCR43 */
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552 SIU.PSMI[6].R = 0x01; /* CS0/DSPI_0 on PCR15 */
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554 #elif defined(CFG_MPC5606S)
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555 // Write pll parameters.
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556 CGM.FMPLL[0].CR.B.IDF = clockSettingsPtr->Pll1;
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557 CGM.FMPLL[0].CR.B.NDIV = clockSettingsPtr->Pll2;
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558 CGM.FMPLL[0].CR.B.ODF = clockSettingsPtr->Pll3;
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560 /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL0 */
\r
561 ME.RUN[0].R = 0x001F0074;
\r
562 /* Peri. Cfg. 1 settings: only run in RUN0 mode */
\r
563 ME.RUNPC[1].R = 0x00000010;
\r
564 /* MPC56xxB/S: select ME.RUNPC[1] */
\r
565 ME.PCTL[68].R = 0x01; //SIUL control
\r
566 ME.PCTL[91].R = 0x01; //RTC/API control
\r
567 ME.PCTL[92].R = 0x01; //PIT_RTI control
\r
568 ME.PCTL[72].R = 0x01; //eMIOS0 control
\r
569 ME.PCTL[73].R = 0x01; //eMIOS1 control
\r
570 ME.PCTL[16].R = 0x01; //FlexCAN0 control
\r
571 ME.PCTL[17].R = 0x01; //FlexCAN1 control
\r
572 ME.PCTL[4].R = 0x01; /* MPC56xxB/P/S DSPI0 */
\r
573 ME.PCTL[5].R = 0x01; /* MPC56xxB/P/S DSPI1: */
\r
574 ME.PCTL[32].R = 0x01; //ADC0 control
\r
575 ME.PCTL[23].R = 0x01; //DMAMUX control
\r
576 ME.PCTL[48].R = 0x01; /* MPC56xxB/P/S LINFlex */
\r
577 ME.PCTL[49].R = 0x01; /* MPC56xxB/P/S LINFlex */
\r
578 /* Mode Transition to enter RUN0 mode: */
\r
579 /* Enter RUN0 Mode & Key */
\r
580 ME.MCTL.R = 0x40005AF0;
\r
581 /* Enter RUN0 Mode & Inverted Key */
\r
582 ME.MCTL.R = 0x4000A50F;
\r
584 /* Wait for mode transition to complete */
\r
585 while (ME.GS.B.S_MTRANS) {}
\r
586 /* Verify RUN0 is the current mode */
\r
587 while(ME.GS.B.S_CURRENTMODE != 4) {}
\r
589 CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */
\r
590 CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */
\r
591 CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */
\r
593 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
\r
594 // Partially following the steps in MPC5567 RM..
\r
595 FMPLL.SYNCR.B.DEPTH = 0;
\r
596 FMPLL.SYNCR.B.LOLRE = 0;
\r
597 FMPLL.SYNCR.B.LOLIRQ = 0;
\r
599 FMPLL.SYNCR.B.PREDIV = clockSettingsPtr->Pll1;
\r
600 FMPLL.SYNCR.B.MFD = clockSettingsPtr->Pll2;
\r
601 FMPLL.SYNCR.B.RFD = clockSettingsPtr->Pll3;
\r
603 // Wait for PLL to sync.
\r
604 while (Mcu_GetPllStatus() != MCU_PLL_LOCKED) ;
\r
606 FMPLL.SYNCR.B.LOLIRQ = 1;
\r
612 //-------------------------------------------------------------------
\r
614 void Mcu_DistributePllClock(void)
\r
616 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_UNINIT );
\r
617 #if defined(CFG_MPC560XB)
\r
618 VALIDATE( ( CGM.FMPLL_CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );
\r
619 #elif defined(CFG_MPC5606S)
\r
620 VALIDATE( ( CGM.FMPLL[0].CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );
\r
622 VALIDATE( ( FMPLL.SYNSR.B.LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );
\r
624 /* NOT IMPLEMENTED due to pointless function on this hardware */
\r
628 //-------------------------------------------------------------------
\r
630 Mcu_PllStatusType Mcu_GetPllStatus(void)
\r
632 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETPLLSTATUS_SERVICE_ID, MCU_E_UNINIT, MCU_PLL_STATUS_UNDEFINED );
\r
633 Mcu_PllStatusType rv;
\r
637 #if defined(CFG_MPC560XB)
\r
638 if ( !CGM.FMPLL_CR.B.S_LOCK )
\r
640 rv = MCU_PLL_UNLOCKED;
\r
643 rv = MCU_PLL_LOCKED;
\r
645 #elif defined(CFG_MPC5606S)
\r
646 if ( !CGM.FMPLL[0].CR.B.S_LOCK )
\r
648 rv = MCU_PLL_UNLOCKED;
\r
651 rv = MCU_PLL_LOCKED;
\r
654 if ( !FMPLL.SYNSR.B.LOCK )
\r
656 rv = MCU_PLL_UNLOCKED;
\r
659 rv = MCU_PLL_LOCKED;
\r
665 /* We are running on instruction set simulator. PLL is then always in sync... */
\r
666 rv = MCU_PLL_LOCKED;
\r
672 //-------------------------------------------------------------------
\r
674 Mcu_ResetType Mcu_GetResetReason(void)
\r
678 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_RESET_UNDEFINED );
\r
680 #if defined(CFG_MPC560X)
\r
681 if( RGM.FES.B.F_SOFT ) {
\r
683 } else if( RGM.DES.B.F_SWT ) {
\r
684 rv = MCU_WATCHDOG_RESET;
\r
685 } else if( RGM.DES.B.F_POR ) {
\r
686 rv = MCU_POWER_ON_RESET;
\r
688 rv = MCU_RESET_UNDEFINED;
\r
691 if( SIU.RSR.B.SSRS ) {
\r
693 } else if( SIU.RSR.B.WDRS ) {
\r
694 rv = MCU_WATCHDOG_RESET;
\r
695 } else if( SIU.RSR.B.PORS || SIU.RSR.B.ERS ) {
\r
696 rv = MCU_POWER_ON_RESET;
\r
698 rv = MCU_RESET_UNDEFINED;
\r
705 //-------------------------------------------------------------------
\r
707 Mcu_RawResetType Mcu_GetResetRawValue(void)
\r
709 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_GETRESETRAWVALUE_UNINIT_RV );
\r
711 if( !Mcu_Global.initRun ) {
\r
712 return MCU_GETRESETRAWVALUE_UNINIT_RV;
\r
715 #if defined(CFG_MPC560X)
\r
726 //-------------------------------------------------------------------
\r
728 #if ( MCU_PERFORM_RESET_API == STD_ON )
\r
729 void Mcu_PerformReset(void)
\r
731 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_PERFORMRESET_SERVICE_ID, MCU_E_UNINIT );
\r
734 #if defined(CFG_MPC560X)
\r
735 ME.MCTL.R = 0x00005AF0;
\r
736 ME.MCTL.R = 0x0000A50F;
\r
738 while (ME.GS.B.S_MTRANS) {}
\r
739 while(ME.GS.B.S_CURRENTMODE != 0) {}
\r
741 SIU.SRCR.B.SSR = 1;
\r
747 //-------------------------------------------------------------------
\r
749 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
753 * Application Notes!
\r
754 * - AN3584, "MPC5510 Family Low Power Features"
\r
755 * Since it's not complete also check MPC5668
\r
756 * - AN4150 , "Using Sleep Mode on the MPC5668x" and it's code
\r
761 static void enterLowPower (Mcu_ModeType mcuMode )
\r
766 /* - Set the sleep bit; following a WAIT instruction, the device will go to sleep
\r
767 * - enable the 1.2V internal regulator when in sleep mode only
\r
769 * - 0x1 8k, 0x2 16k, 0x3 32k, 0x6 64k -- RAMs maintain power
\r
771 * - 0x1 32k, 0x2 64k, 0x3 128k
\r
773 WRITE32(CRP_PSCR, PSCR_SLEEP | PSCR_SLP12EN | PCSR_RAMSEL(RAMSEL_VAL));
\r
775 /* Set Recover Vector */
\r
776 #if defined(CFG_MPC5516)
\r
778 WRITE32(CRP_Z1VEC, ((uint32)&McuE_LowPowerRecoverFlash) | VLE_VAL );
\r
779 READWRITE32( CRP_RECPTR, RECPTR_FASTREC, 0 );
\r
781 Mcu_SavedHaltFlags = SIU.HLT.R;
\r
782 /* Halt everything */
\r
783 SIU.HLT.R = 0x3FFFFFFF;
\r
784 while((SIU.HLTACK.R != 0x3FFFFFFF) && (timeout<3000)) {}
\r
786 /* put Z0 in reset if not used for wakeup */
\r
787 CRP.Z0VEC.B.Z0RST = 1;
\r
789 #elif defined(CFG_MPC5668)
\r
791 WRITE32(CRP_Z6VEC, ((uint32)&McuE_LowPowerRecoverFlash) | VLE_VAL );
\r
792 READWRITE32(CRP_RECPTR,RECPTR_FASTREC,0 );
\r
794 Mcu_SavedHaltFlags[0] = SIU.HLT0.R;
\r
795 Mcu_SavedHaltFlags[1] = SIU.HLT1.R;
\r
796 /* Halt everything */
\r
797 SIU.HLT0.R = 0x037FFF3D;
\r
798 SIU.HLT1.R = 0x18000F3C;
\r
799 while((SIU.HLTACK0.R != 0x037FFF3D) && (SIU.HLTACK1.R != 0x18000F3C) && (timeout<3000)){}
\r
801 #error CPU not defined
\r
804 /* put Z0 in reset if not used for wakeup */
\r
805 CRP.Z0VEC.B.Z0RST = 1;
\r
807 /* Save context and execute wait instruction.
\r
809 * Things that matter here are
\r
810 * - Z1VEC, determines where TLB0 will point. TLB0 is written with a
\r
811 * value at startup that 4K aligned to this address.
\r
812 * - LowPower_Sleep() will save a interrupt context so we will return
\r
814 * - For devices with little RAM we don't want to impose the alignment
\r
815 * requirements there. Almost as we have to occupy a 4K block for this..
\r
816 * although the code does not take that much space.
\r
818 McuE_EnterLowPower(mcuMode);
\r
820 /* Clear sleep flags to allow pads to operate */
\r
821 CRP.PSCR.B.SLEEPF = 0x1;
\r
826 void Mcu_SetMode( Mcu_ModeType mcuMode)
\r
828 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_SETMODE_SERVICE_ID, MCU_E_UNINIT );
\r
829 // VALIDATE( ( McuMode <= Mcu_Global.config->McuNumberOfMcuModes ), MCU_SETMODE_SERVICE_ID, MCU_E_PARAM_MODE );
\r
832 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
833 if( MCU_MODE_RUN == mcuMode ) {
\r
835 /* Get back to "normal" halt flags */
\r
836 #if defined(CFG_MPC5516)
\r
837 SIU.HLT.R = Mcu_SavedHaltFlags;
\r
838 #elif defined(CFG_MPC5668)
\r
839 SIU.HLT0.R = Mcu_SavedHaltFlags[0];
\r
840 SIU.HLT1.R = Mcu_SavedHaltFlags[1];
\r
843 } else if( MCU_MODE_SLEEP == mcuMode ) {
\r
845 * Follows the AN3548 from Freescale
\r
848 #if defined(USE_DMA)
\r
853 /* Set system clock to 16Mhz IRC */
\r
854 SIU.SYSCLK.B.SYSCLKSEL = 0;
\r
856 /* Put flash in low-power mode */
\r
859 /* Put QQADC in low-power mode */
\r
862 /* Set us in SLEEP mode */
\r
863 CRP.PSCR.B.SLEEP = 1;
\r
866 enterLowPower(mcuMode);
\r
869 /* NOT SUPPORTED */
\r
874 //-------------------------------------------------------------------
\r
877 * Get the system clock in Hz. It calculates the clock from the
\r
878 * different register settings in HW.
\r
880 uint32_t McuE_GetSystemClock(void)
\r
883 * System clock calculation
\r
885 * 5516 - f_sys = extal * (emfd+16) / ( (eprediv+1) * ( erfd+1 ));
\r
886 * 5567 - f_sys = extal * (emfd+4) / ( (eprediv+1) * ( 2^erfd ));
\r
887 * 563x - We run in legacy mode = 5567
\r
888 * 5606s - f_sys = extal * emfd / ((eprediv+1)*(2<<(erfd)));
\r
890 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
891 uint32_t eprediv = FMPLL.ESYNCR1.B.EPREDIV;
\r
892 uint32_t emfd = FMPLL.ESYNCR1.B.EMFD;
\r
893 uint32_t erfd = FMPLL.ESYNCR2.B.ERFD;
\r
894 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567) || defined(CFG_MPC5633)
\r
895 uint32_t eprediv = FMPLL.SYNCR.B.PREDIV;
\r
896 uint32_t emfd = FMPLL.SYNCR.B.MFD;
\r
897 uint32_t erfd = FMPLL.SYNCR.B.RFD;
\r
898 #elif defined(CFG_MPC560XB)
\r
899 uint32_t eprediv = CGM.FMPLL_CR.B.IDF;
\r
900 uint32_t emfd = CGM.FMPLL_CR.B.NDIV;
\r
901 uint32_t erfd = CGM.FMPLL_CR.B.ODF;
\r
902 #elif defined(CFG_MPC5606S)
\r
903 uint32_t eprediv = CGM.FMPLL[0].CR.B.IDF;
\r
904 uint32_t emfd = CGM.FMPLL[0].CR.B.NDIV;
\r
905 uint32_t erfd = CGM.FMPLL[0].CR.B.ODF;
\r
909 uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;
\r
911 f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);
\r
916 #if defined(CFG_MPC5668)
\r
917 uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type) {
\r
918 uint32_t sysClock = McuE_GetSystemClock();
\r
919 vuint32_t prescaler;
\r
923 case PERIPHERAL_CLOCK_FLEXCAN_A:
\r
924 case PERIPHERAL_CLOCK_FLEXCAN_B:
\r
925 case PERIPHERAL_CLOCK_FLEXCAN_C:
\r
926 case PERIPHERAL_CLOCK_FLEXCAN_D:
\r
927 case PERIPHERAL_CLOCK_FLEXCAN_E:
\r
928 case PERIPHERAL_CLOCK_FLEXCAN_F:
\r
929 case PERIPHERAL_CLOCK_DSPI_A:
\r
930 case PERIPHERAL_CLOCK_DSPI_B:
\r
931 case PERIPHERAL_CLOCK_DSPI_C:
\r
932 case PERIPHERAL_CLOCK_DSPI_D:
\r
933 prescaler = SIU.SYSCLK.B.LPCLKDIV1;
\r
935 case PERIPHERAL_CLOCK_ESCI_A:
\r
936 case PERIPHERAL_CLOCK_ESCI_B:
\r
937 case PERIPHERAL_CLOCK_ESCI_C:
\r
938 case PERIPHERAL_CLOCK_ESCI_D:
\r
939 case PERIPHERAL_CLOCK_ESCI_E:
\r
940 case PERIPHERAL_CLOCK_ESCI_F:
\r
941 case PERIPHERAL_CLOCK_IIC_A:
\r
942 case PERIPHERAL_CLOCK_IIC_B:
\r
943 prescaler = SIU.SYSCLK.B.LPCLKDIV0;
\r
945 case PERIPHERAL_CLOCK_ADC_A:
\r
946 prescaler = SIU.SYSCLK.B.LPCLKDIV2;
\r
948 case PERIPHERAL_CLOCK_EMIOS:
\r
949 prescaler = SIU.SYSCLK.B.LPCLKDIV3;
\r
956 return sysClock/(1<<prescaler);
\r
963 * Get the peripheral clock in Hz for a specific device
\r
965 uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type)
\r
967 #if defined(CFG_MPC5567)
\r
968 // No peripheral dividers on 5567.
\r
969 return McuE_GetSystemClock();
\r
971 uint32_t sysClock = McuE_GetSystemClock();
\r
972 vuint32_t prescaler;
\r
974 // See table 3.1, section 3.4.5 Peripheral Clock dividers
\r
977 case PERIPHERAL_CLOCK_FLEXCAN_A:
\r
978 case PERIPHERAL_CLOCK_DSPI_A:
\r
979 #if defined(CFG_MPC5516)
\r
980 prescaler = SIU.SYSCLK.B.LPCLKDIV0;
\r
982 #elif defined(CFG_MPC560X)
\r
983 prescaler = CGM.SC_DC[1].B.DIV;
\r
987 case PERIPHERAL_CLOCK_PIT:
\r
988 case PERIPHERAL_CLOCK_ESCI_A:
\r
989 case PERIPHERAL_CLOCK_IIC_A:
\r
990 #if defined(CFG_MPC5516)
\r
991 prescaler = SIU.SYSCLK.B.LPCLKDIV1;
\r
995 case PERIPHERAL_CLOCK_FLEXCAN_B:
\r
996 case PERIPHERAL_CLOCK_FLEXCAN_C:
\r
997 case PERIPHERAL_CLOCK_FLEXCAN_D:
\r
998 case PERIPHERAL_CLOCK_FLEXCAN_E:
\r
999 case PERIPHERAL_CLOCK_FLEXCAN_F:
\r
1000 #if defined(CFG_MPC5516)
\r
1001 prescaler = SIU.SYSCLK.B.LPCLKDIV2;
\r
1003 #elif defined(CFG_MPC560X)
\r
1004 prescaler = CGM.SC_DC[1].B.DIV;
\r
1008 case PERIPHERAL_CLOCK_DSPI_B:
\r
1009 case PERIPHERAL_CLOCK_DSPI_C:
\r
1010 case PERIPHERAL_CLOCK_DSPI_D:
\r
1011 case PERIPHERAL_CLOCK_DSPI_E:
\r
1012 case PERIPHERAL_CLOCK_DSPI_F:
\r
1013 #if defined(CFG_MPC5516)
\r
1014 prescaler = SIU.SYSCLK.B.LPCLKDIV3;
\r
1018 case PERIPHERAL_CLOCK_ESCI_B:
\r
1019 case PERIPHERAL_CLOCK_ESCI_C:
\r
1020 case PERIPHERAL_CLOCK_ESCI_D:
\r
1021 case PERIPHERAL_CLOCK_ESCI_E:
\r
1022 case PERIPHERAL_CLOCK_ESCI_F:
\r
1023 case PERIPHERAL_CLOCK_ESCI_G:
\r
1024 case PERIPHERAL_CLOCK_ESCI_H:
\r
1025 #if defined(CFG_MPC5516)
\r
1026 prescaler = SIU.SYSCLK.B.LPCLKDIV4;
\r
1030 #if defined(CFG_MPC560X)
\r
1031 case PERIPHERAL_CLOCK_LIN_A:
\r
1032 case PERIPHERAL_CLOCK_LIN_B:
\r
1033 #if defined(CFG_MPC560XB)
\r
1034 case PERIPHERAL_CLOCK_LIN_C:
\r
1035 case PERIPHERAL_CLOCK_LIN_D:
\r
1037 prescaler = CGM.SC_DC[0].B.DIV;
\r
1039 case PERIPHERAL_CLOCK_EMIOS_0:
\r
1040 prescaler = CGM.SC_DC[2].B.DIV;
\r
1042 case PERIPHERAL_CLOCK_EMIOS_1:
\r
1043 prescaler = CGM.SC_DC[2].B.DIV;
\r
1046 case PERIPHERAL_CLOCK_EMIOS:
\r
1047 #if defined(CFG_MPC5516)
\r
1048 prescaler = SIU.SYSCLK.B.LPCLKDIV5;
\r
1053 case PERIPHERAL_CLOCK_MLB:
\r
1054 #if defined(CFG_MPC5516)
\r
1055 prescaler = SIU.SYSCLK.B.LPCLKDIV6;
\r
1064 return sysClock/(1<<prescaler);
\r
1070 * Function to setup the internal flash for optimal performance
\r
1073 static void Mcu_ConfigureFlash(void)
\r
1075 /* These flash settings increases the CPU performance of 7 times compared
\r
1076 to reset default settings!! */
\r
1078 #if defined(CFG_MPC5516)
\r
1079 /* Disable pipelined reads when flash options are changed. */
\r
1080 FLASH.MCR.B.PRD = 1;
\r
1082 /* Enable master prefetch for e200z1 and eDMA. */
\r
1083 FLASH.PFCRP0.B.M0PFE = 1;
\r
1084 FLASH.PFCRP0.B.M2PFE = 1;
\r
1086 /* Address pipelining control. Must be set to the same value as RWSC. */
\r
1087 FLASH.PFCRP0.B.APC = 2;
\r
1088 FLASH.PFCRP0.B.RWSC = 2;
\r
1090 /* Write wait states. */
\r
1091 FLASH.PFCRP0.B.WWSC = 1;
\r
1093 /* Enable data prefetch. */
\r
1094 FLASH.PFCRP0.B.DPFEN = 1;
\r
1096 /* Enable instruction prefetch. */
\r
1097 FLASH.PFCRP0.B.IPFEN = 1;
\r
1099 /* Prefetch algorithm. */
\r
1100 /* TODO: Ask Freescale about this option. */
\r
1101 FLASH.PFCRP0.B.PFLIM = 2;
\r
1103 /* Enable line read buffers. */
\r
1104 FLASH.PFCRP0.B.BFEN = 1;
\r
1106 /* Enable pipelined reads again. */
\r
1107 FLASH.MCR.B.PRD = 0;
\r
1108 #elif defined(CFG_MPC5668)
\r
1109 /* Check values from cookbook and MPC5668x Microcontroller Data Sheet */
\r
1111 /* Should probably trim this values */
\r
1112 const typeof(FLASH.PFCRP0.B) val = {.M0PFE = 1, .M2PFE=1, .APC=3,
\r
1113 .RWSC=3, .WWSC =1, .DPFEN =1, .IPFEN = 1, .PFLIM =2,
\r
1115 FLASH.PFCRP0.B = val;
\r
1117 /* Enable pipelined reads again. */
\r
1118 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
\r
1119 //TODO: Lägg till flash för mpc5554 &67
\r