2 /**************************************************************************/
\r
3 /* FILE NAME: mpc5567.h COPYRIGHT (c) Freescale 2007 */
\r
4 /* VERSION: 1.6 All Rights Reserved */
\r
7 /* This file contain all of the register and bit field definitions for */
\r
9 /*========================================================================*/
\r
10 /* UPDATE HISTORY */
\r
11 /* REV AUTHOR DATE DESCRIPTION OF CHANGE */
\r
12 /* --- ----------- --------- --------------------- */
\r
13 /* 1.0 G. Emerson 03/Jan/06 Initial version. */
\r
14 /* 1.1 G. Emerson 27/Mar/06 Fix issue with Flexcan BCC field. */
\r
15 /* 1.2 S. Mathieson 28/Jul/06 Change Flexcan BCC bit to MBFEN */
\r
16 /* Add Flexcan bits WRNEN, SRXDIS, */
\r
17 /* TWRNMSK, RWRNMSK,TWRNINT,RWRNINT */
\r
18 /* 1.3 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */
\r
19 /* to DPB to align with documentation. */
\r
20 /* 1.4 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */
\r
21 /* alternate configuration. */
\r
22 /* INTC, correction to the number of PSR */
\r
24 /* Updates to bitfield sizes in MBSSUTR, */
\r
25 /* MBIVEC, MBIDX & RSBIR. RSBIR, SELEC */
\r
26 /* changed to SEL & RFRFCFR, FNUM changed */
\r
27 /* to SEL to align with documentation. */
\r
28 /* Various register/ bitfield updates to */
\r
29 /* correct errors (MCR, TMODE bit removed.*/
\r
30 /* PADR register removed. PIER1, DRDIE bit*/
\r
31 /* removed & PIFR1, DRDIF removed. PCR1, */
\r
32 /* Filter bypass bit removed). */
\r
33 /* 1.5 S. Mathieson 25/Apr/07 SRAM size changed from 64K to 80K. */
\r
35 /* 1.6 G. Emerson 26/Oct/07 All module instantiations now volatile */
\r
36 /* All registers/bit fields now volatile */
\r
37 /**************************************************************************/
\r
38 /*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
\r
43 #include "Compiler.h"
\r
44 #include "typedefs.h"
\r
52 #pragma ANSI_strict off
\r
55 /****************************************************************************/
\r
56 /* MODULE : PBRIDGE_A Peripheral Bridge */
\r
57 /****************************************************************************/
\r
58 CC_EXTENSION struct PBRIDGE_A_tag {
\r
79 vuint32_t MBW4:1; /* FEC */
\r
86 vuint32_t MBW6:1; /* FLEXRAY */
\r
93 } MPCR; /* Master Privilege Control Register */
\r
95 uint32_t pbridge_a_reserved2[7];
\r
108 uint32_t pbridge_a_reserved3[7];
\r
138 vuint32_t BW0:1; /* EMIOS */
\r
173 /****************************************************************************/
\r
174 /* MODULE : PBRIDGE_B Peripheral Bridge */
\r
175 /****************************************************************************/
\r
176 CC_EXTENSION struct PBRIDGE_B_tag {
\r
197 vuint32_t MBW4:1; /* FEC */
\r
204 vuint32_t MBW6:1; /* FLEXRAY */
\r
211 } MPCR; /* Master Privilege Control Register */
\r
213 uint32_t pbridge_b_reserved2[7];
\r
230 uint32_t pbridge_b_reserved3;
\r
248 vuint32_t BW3:1; /* FEC */
\r
258 uint32_t pbridge_b_reserved4[5];
\r
271 vuint32_t BW5:1; /* DSPI_B */
\r
296 vuint32_t BW5:1; /* ESCI_B */
\r
313 vuint32_t BW1:1; /* CAN_B */
\r
323 vuint32_t BW3:1; /* CAN_D */
\r
328 vuint32_t BW4:1; /* CAN_E */
\r
341 vuint32_t BW0:1; /* FLEXRAY */
\r
355 /****************************************************************************/
\r
356 /* MODULE : FMPLL */
\r
357 /****************************************************************************/
\r
358 CC_EXTENSION struct FMPLL_tag {
\r
363 vuint32_t PREDIV:3;
\r
370 vuint32_t DISCLK:1;
\r
371 vuint32_t LOLIRQ:1;
\r
372 vuint32_t LOCIRQ:1;
\r
386 vuint32_t PLLSEL:1;
\r
387 vuint32_t PLLREF:1;
\r
391 vuint32_t CALDONE:1;
\r
392 vuint32_t CALPASS:1;
\r
397 /****************************************************************************/
\r
398 /* MODULE : External Bus Interface (EBI) */
\r
399 /****************************************************************************/
\r
400 CC_EXTENSION struct CS_tag {
\r
401 union { /* Base Register Bank */
\r
417 union { /* Option Register Bank */
\r
430 struct CAL_CS_tag {
\r
431 union { /* Calibration Base Register Bank */
\r
447 union { /* Calibration Option Register Bank */
\r
461 union { /* Module Configuration Register */
\r
465 vuint32_t SIZEEN:1;
\r
479 uint32_t EBI_reserved1;
\r
481 union { /* Transfer Error Status Register */
\r
490 union { /* Bus Monitor Control Register */
\r
500 struct CS_tag CS[4];
\r
502 /* Calibration registers */
\r
503 uint32_t EBI_reserved2[4];
\r
504 struct CAL_CS_tag CAL_CS[4];
\r
507 /****************************************************************************/
\r
508 /* MODULE : FLASH */
\r
509 /****************************************************************************/
\r
510 CC_EXTENSION struct FLASH_tag {
\r
511 union { /* Module Configuration Register */
\r
540 union { /* LML Register */
\r
547 vuint32_t LLOCK:16;
\r
551 union { /* HL Register */
\r
556 vuint32_t HBLOCK:28;
\r
560 union { /* SLML Register */
\r
565 vuint32_t SSLOCK:1;
\r
566 vuint32_t SMLOCK:4;
\r
567 vuint32_t SLLOCK:16;
\r
571 union { /* LMS Register */
\r
584 vuint32_t HBSEL:28;
\r
602 vuint32_t M6PFE:1; /* Flexray */
\r
605 vuint32_t M4PFE:1; /* FEC */
\r
628 vuint32_t M6AP:2; /* Flexray */
\r
631 vuint32_t M4AP:2; /* FEC */
\r
640 /****************************************************************************/
\r
642 /****************************************************************************/
\r
643 CC_EXTENSION struct SIU_tag {
\r
644 int32_t SIU_reserved0;
\r
646 union { /* MCU ID Register */
\r
649 vuint32_t PARTNUM:16;
\r
650 vuint32_t MASKNUM:16;
\r
653 int32_t SIU_reserved00;
\r
655 union { /* Reset Status Register */
\r
667 vuint32_t WKPCFG:1;
\r
669 vuint32_t BOOTCFG:2;
\r
674 union { /* System Reset Control Register */
\r
685 union { /* External Interrupt Status Register */
\r
708 union { /* DMA/Interrupt Request Enable Register */
\r
712 vuint32_t EIRE15:1;
\r
713 vuint32_t EIRE14:1;
\r
714 vuint32_t EIRE13:1;
\r
715 vuint32_t EIRE12:1;
\r
716 vuint32_t EIRE11:1;
\r
717 vuint32_t EIRE10:1;
\r
731 union { /* DMA/Interrupt Select Register */
\r
742 union { /* Overrun Status Register */
\r
765 union { /* Overrun Request Enable Register */
\r
788 union { /* External IRQ Rising-Edge Event Enable Register */
\r
792 vuint32_t IREE15:1;
\r
793 vuint32_t IREE14:1;
\r
794 vuint32_t IREE13:1;
\r
795 vuint32_t IREE12:1;
\r
796 vuint32_t IREE11:1;
\r
797 vuint32_t IREE10:1;
\r
811 union { /* External IRQ Falling-Edge Event Enable Register */
\r
815 vuint32_t IFEE15:1;
\r
816 vuint32_t IFEE14:1;
\r
817 vuint32_t IFEE13:1;
\r
818 vuint32_t IFEE12:1;
\r
819 vuint32_t IFEE11:1;
\r
820 vuint32_t IFEE10:1;
\r
834 union { /* External IRQ Digital Filter Register */
\r
842 int32_t SIU_reserved1[3];
\r
844 union { /* Pad Configuration Registers */
\r
860 int16_t SIU_reserved_0[224];
\r
862 union { /* GPIO Pin Data Output Registers */
\r
870 int32_t SIU_reserved_3[64];
\r
872 union { /* GPIO Pin Data Input Registers */
\r
880 union { /* IMUX Register */
\r
893 union { /* IMUX Register */
\r
896 vuint32_t ESEL15:2;
\r
897 vuint32_t ESEL14:2;
\r
898 vuint32_t ESEL13:2;
\r
899 vuint32_t ESEL12:2;
\r
900 vuint32_t ESEL11:2;
\r
901 vuint32_t ESEL10:2;
\r
915 union { /* IMUX Register */
\r
918 vuint32_t SINSELA:2;
\r
919 vuint32_t SSSELA:2;
\r
920 vuint32_t SCKSELA:2;
\r
921 vuint32_t TRIGSELA:2;
\r
922 vuint32_t SINSELB:2;
\r
923 vuint32_t SSSELB:2;
\r
924 vuint32_t SCKSELB:2;
\r
925 vuint32_t TRIGSELB:2;
\r
926 vuint32_t SINSELC:2;
\r
927 vuint32_t SSSELC:2;
\r
928 vuint32_t SCKSELC:2;
\r
929 vuint32_t TRIGSELC:2;
\r
930 vuint32_t SINSELD:2;
\r
931 vuint32_t SSSELD:2;
\r
932 vuint32_t SCKSELD:2;
\r
933 vuint32_t TRIGSELD:2;
\r
937 int32_t SIU_reserved2[29];
\r
939 union { /* Chip Configuration Register Register */
\r
944 vuint32_t DISNEX:1;
\r
949 union { /* External Clock Configuration Register Register */
\r
953 vuint32_t ENGDIV:6;
\r
978 /****************************************************************************/
\r
979 /* MODULE : EMIOS */
\r
980 /****************************************************************************/
\r
981 CC_EXTENSION struct EMIOS_tag {
\r
996 } MCR; /* Module Configuration Register */
\r
1027 } GFR; /* Global FLAG Register */
\r
1058 } OUDR; /* Output Update Disable Register */
\r
1060 uint32_t emios_reserved[5];
\r
1064 vuint32_t R; /* Channel A Data Register */
\r
1068 vuint32_t R; /* Channel B Data Register */
\r
1072 vuint32_t R; /* Channel Counter Register */
\r
1080 vuint32_t ODISSL:2;
\r
1081 vuint32_t UCPRE:2;
\r
1082 vuint32_t UCPREN:1;
\r
1089 vuint32_t FORCMA:1;
\r
1090 vuint32_t FORCMB:1;
\r
1093 vuint32_t EDSEL:1;
\r
1094 vuint32_t EDPOL:1;
\r
1097 } CCR; /* Channel Control Register */
\r
1107 vuint32_t UCOUT:1;
\r
1110 } CSR; /* Channel Status Register */
\r
1113 vuint32_t R; /* Alternate Channel A Data Register */
\r
1116 uint32_t emios_channel_reserved[2];
\r
1121 /****************************************************************************/
\r
1122 /* MODULE :ETPU */
\r
1123 /****************************************************************************/
\r
1125 /***************************Configuration Registers**************************/
\r
1127 CC_EXTENSION struct ETPU_tag {
\r
1128 union { /* MODULE CONFIGURATION REGISTER */
\r
1131 vuint32_t GEC:1; /* Global Exception Clear */
\r
1133 vuint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */
\r
1135 vuint32_t:1; /* For single ETPU implementations */
\r
1137 vuint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */
\r
1139 vuint32_t:1; /* For single ETPU implementations */
\r
1142 vuint32_t SCMSIZE:5; /* Shared Code Memory size */
\r
1144 vuint32_t SCMMISF:1; /* SCM MISC Flag */
\r
1145 vuint32_t SCMMISEN:1; /* SCM MISC Enable */
\r
1147 vuint32_t VIS:1; /* SCM Visability */
\r
1149 vuint32_t GTBE:1; /* Global Time Base Enable */
\r
1153 union { /* COHERENT DUAL-PARAMETER CONTROL */
\r
1156 vuint32_t STS:1; /* Start Status bit */
\r
1157 vuint32_t CTBASE:5; /* Channel Transfer Base */
\r
1158 vuint32_t PBASE:10; /* Parameter Buffer Base Address */
\r
1159 vuint32_t PWIDTH:1; /* Parameter Width */
\r
1160 vuint32_t PARAM0:7; /* Channel Parameter 0 */
\r
1162 vuint32_t PARAM1:7; /* Channel Parameter 1 */
\r
1166 uint32_t etpu_reserved1;
\r
1168 union { /* MISC Compare Register */
\r
1172 union { /* SCM off-range Date Register */
\r
1176 union { /* ETPU_A Configuration Register */
\r
1179 vuint32_t FEND:1; /* Force END */
\r
1180 vuint32_t MDIS:1; /* Low power Stop */
\r
1182 vuint32_t STF:1; /* Stop Flag */
\r
1184 vuint32_t HLTF:1; /* Halt Mode Flag */
\r
1186 vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */
\r
1189 vuint32_t ETB:5; /* Entry Table Base */
\r
1192 uint32_t etpu_reserved3; /* For single ETPU implementations */
\r
1194 uint32_t etpu_reserved4;
\r
1196 union { /* ETPU_A Timebase Configuration Register */
\r
1199 vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
\r
1200 vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
\r
1202 vuint32_t AM:1; /* Angle Mode */
\r
1204 vuint32_t TCR2P:6; /* TCR2 Prescaler Control */
\r
1205 vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
\r
1207 vuint32_t TCR1P:8; /* TCR1 Prescaler Control */
\r
1211 union { /* ETPU_A TCR1 Visibility Register */
\r
1215 union { /* ETPU_A TCR2 Visibility Register */
\r
1219 union { /* ETPU_A STAC Configuration Register */
\r
1222 vuint32_t REN1:1; /* Resource Enable TCR1 */
\r
1223 vuint32_t RSC1:1; /* Resource Control TCR1 */
\r
1225 vuint32_t SERVER_ID1:4;
\r
1227 vuint32_t SRV1:4; /* Resource Server Slot */
\r
1228 vuint32_t REN2:1; /* Resource Enable TCR2 */
\r
1229 vuint32_t RSC2:1; /* Resource Control TCR2 */
\r
1231 vuint32_t SERVER_ID2:4;
\r
1233 vuint32_t SRV2:4; /* Resource Server Slot */
\r
1237 uint32_t etpu_reserved5[4];
\r
1238 uint32_t etpu_reserved6[4]; /* For single ETPU implementations */
\r
1240 uint32_t etpu_reserved7[108];
\r
1242 /*****************************Status and Control Registers**************************/
\r
1244 union { /* ETPU_A Channel Interrut Status */
\r
1247 vuint32_t CIS31:1; /* Channel 31 Interrut Status */
\r
1248 vuint32_t CIS30:1; /* Channel 30 Interrut Status */
\r
1249 vuint32_t CIS29:1; /* Channel 29 Interrut Status */
\r
1250 vuint32_t CIS28:1; /* Channel 28 Interrut Status */
\r
1251 vuint32_t CIS27:1; /* Channel 27 Interrut Status */
\r
1252 vuint32_t CIS26:1; /* Channel 26 Interrut Status */
\r
1253 vuint32_t CIS25:1; /* Channel 25 Interrut Status */
\r
1254 vuint32_t CIS24:1; /* Channel 24 Interrut Status */
\r
1255 vuint32_t CIS23:1; /* Channel 23 Interrut Status */
\r
1256 vuint32_t CIS22:1; /* Channel 22 Interrut Status */
\r
1257 vuint32_t CIS21:1; /* Channel 21 Interrut Status */
\r
1258 vuint32_t CIS20:1; /* Channel 20 Interrut Status */
\r
1259 vuint32_t CIS19:1; /* Channel 19 Interrut Status */
\r
1260 vuint32_t CIS18:1; /* Channel 18 Interrut Status */
\r
1261 vuint32_t CIS17:1; /* Channel 17 Interrut Status */
\r
1262 vuint32_t CIS16:1; /* Channel 16 Interrut Status */
\r
1263 vuint32_t CIS15:1; /* Channel 15 Interrut Status */
\r
1264 vuint32_t CIS14:1; /* Channel 14 Interrut Status */
\r
1265 vuint32_t CIS13:1; /* Channel 13 Interrut Status */
\r
1266 vuint32_t CIS12:1; /* Channel 12 Interrut Status */
\r
1267 vuint32_t CIS11:1; /* Channel 11 Interrut Status */
\r
1268 vuint32_t CIS10:1; /* Channel 10 Interrut Status */
\r
1269 vuint32_t CIS9:1; /* Channel 9 Interrut Status */
\r
1270 vuint32_t CIS8:1; /* Channel 8 Interrut Status */
\r
1271 vuint32_t CIS7:1; /* Channel 7 Interrut Status */
\r
1272 vuint32_t CIS6:1; /* Channel 6 Interrut Status */
\r
1273 vuint32_t CIS5:1; /* Channel 5 Interrut Status */
\r
1274 vuint32_t CIS4:1; /* Channel 4 Interrut Status */
\r
1275 vuint32_t CIS3:1; /* Channel 3 Interrut Status */
\r
1276 vuint32_t CIS2:1; /* Channel 2 Interrut Status */
\r
1277 vuint32_t CIS1:1; /* Channel 1 Interrut Status */
\r
1278 vuint32_t CIS0:1; /* Channel 0 Interrut Status */
\r
1281 uint32_t etpu_reserved8; /* For single ETPU implementations */
\r
1283 uint32_t etpu_reserved9[2];
\r
1285 union { /* ETPU_A Data Transfer Request Status */
\r
1288 vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
\r
1289 vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
\r
1290 vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
\r
1291 vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
\r
1292 vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
\r
1293 vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
\r
1294 vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
\r
1295 vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
\r
1296 vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
\r
1297 vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
\r
1298 vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
\r
1299 vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
\r
1300 vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
\r
1301 vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
\r
1302 vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
\r
1303 vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
\r
1304 vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
\r
1305 vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
\r
1306 vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
\r
1307 vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
\r
1308 vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
\r
1309 vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
\r
1310 vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
\r
1311 vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
\r
1312 vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
\r
1313 vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
\r
1314 vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
\r
1315 vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
\r
1316 vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
\r
1317 vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
\r
1318 vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
\r
1319 vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
\r
1322 uint32_t etpu_reserved10; /* For single ETPU implementations */
\r
1324 uint32_t etpu_reserved11[2];
\r
1326 union { /* ETPU_A Interruput Overflow Status */
\r
1329 vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
\r
1330 vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
\r
1331 vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
\r
1332 vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
\r
1333 vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
\r
1334 vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
\r
1335 vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
\r
1336 vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
\r
1337 vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
\r
1338 vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
\r
1339 vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
\r
1340 vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
\r
1341 vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
\r
1342 vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
\r
1343 vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
\r
1344 vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
\r
1345 vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
\r
1346 vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
\r
1347 vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
\r
1348 vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
\r
1349 vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
\r
1350 vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
\r
1351 vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
\r
1352 vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
\r
1353 vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
\r
1354 vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
\r
1355 vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
\r
1356 vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
\r
1357 vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
\r
1358 vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
\r
1359 vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
\r
1360 vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
\r
1363 uint32_t etpu_reserved12; /* For single ETPU implementations */
\r
1365 uint32_t etpu_reserved13[2];
\r
1367 union { /* ETPU_A Data Transfer Overflow Status */
\r
1370 vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
\r
1371 vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
\r
1372 vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
\r
1373 vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
\r
1374 vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
\r
1375 vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
\r
1376 vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
\r
1377 vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
\r
1378 vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
\r
1379 vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
\r
1380 vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
\r
1381 vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
\r
1382 vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
\r
1383 vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
\r
1384 vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
\r
1385 vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
\r
1386 vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
\r
1387 vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
\r
1388 vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
\r
1389 vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
\r
1390 vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
\r
1391 vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
\r
1392 vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
\r
1393 vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
\r
1394 vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
\r
1395 vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
\r
1396 vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
\r
1397 vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
\r
1398 vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
\r
1399 vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
\r
1400 vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
\r
1401 vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
\r
1404 uint32_t etpu_reserved14; /* For single ETPU implementations */
\r
1406 uint32_t etpu_reserved15[2];
\r
1408 union { /* ETPU_A Channel Interruput Enable */
\r
1411 vuint32_t CIE31:1; /* Channel 31 Interruput Enable */
\r
1412 vuint32_t CIE30:1; /* Channel 30 Interruput Enable */
\r
1413 vuint32_t CIE29:1; /* Channel 29 Interruput Enable */
\r
1414 vuint32_t CIE28:1; /* Channel 28 Interruput Enable */
\r
1415 vuint32_t CIE27:1; /* Channel 27 Interruput Enable */
\r
1416 vuint32_t CIE26:1; /* Channel 26 Interruput Enable */
\r
1417 vuint32_t CIE25:1; /* Channel 25 Interruput Enable */
\r
1418 vuint32_t CIE24:1; /* Channel 24 Interruput Enable */
\r
1419 vuint32_t CIE23:1; /* Channel 23 Interruput Enable */
\r
1420 vuint32_t CIE22:1; /* Channel 22 Interruput Enable */
\r
1421 vuint32_t CIE21:1; /* Channel 21 Interruput Enable */
\r
1422 vuint32_t CIE20:1; /* Channel 20 Interruput Enable */
\r
1423 vuint32_t CIE19:1; /* Channel 19 Interruput Enable */
\r
1424 vuint32_t CIE18:1; /* Channel 18 Interruput Enable */
\r
1425 vuint32_t CIE17:1; /* Channel 17 Interruput Enable */
\r
1426 vuint32_t CIE16:1; /* Channel 16 Interruput Enable */
\r
1427 vuint32_t CIE15:1; /* Channel 15 Interruput Enable */
\r
1428 vuint32_t CIE14:1; /* Channel 14 Interruput Enable */
\r
1429 vuint32_t CIE13:1; /* Channel 13 Interruput Enable */
\r
1430 vuint32_t CIE12:1; /* Channel 12 Interruput Enable */
\r
1431 vuint32_t CIE11:1; /* Channel 11 Interruput Enable */
\r
1432 vuint32_t CIE10:1; /* Channel 10 Interruput Enable */
\r
1433 vuint32_t CIE9:1; /* Channel 9 Interruput Enable */
\r
1434 vuint32_t CIE8:1; /* Channel 8 Interruput Enable */
\r
1435 vuint32_t CIE7:1; /* Channel 7 Interruput Enable */
\r
1436 vuint32_t CIE6:1; /* Channel 6 Interruput Enable */
\r
1437 vuint32_t CIE5:1; /* Channel 5 Interruput Enable */
\r
1438 vuint32_t CIE4:1; /* Channel 4 Interruput Enable */
\r
1439 vuint32_t CIE3:1; /* Channel 3 Interruput Enable */
\r
1440 vuint32_t CIE2:1; /* Channel 2 Interruput Enable */
\r
1441 vuint32_t CIE1:1; /* Channel 1 Interruput Enable */
\r
1442 vuint32_t CIE0:1; /* Channel 0 Interruput Enable */
\r
1445 uint32_t etpu_reserved16; /* For single ETPU implementations */
\r
1447 uint32_t etpu_reserved17[2];
\r
1449 union { /* ETPU_A Channel Data Transfer Request Enable */
\r
1452 vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
\r
1453 vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
\r
1454 vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
\r
1455 vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
\r
1456 vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
\r
1457 vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
\r
1458 vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
\r
1459 vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
\r
1460 vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
\r
1461 vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
\r
1462 vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
\r
1463 vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
\r
1464 vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
\r
1465 vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
\r
1466 vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
\r
1467 vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
\r
1468 vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
\r
1469 vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
\r
1470 vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
\r
1471 vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
\r
1472 vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
\r
1473 vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
\r
1474 vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
\r
1475 vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
\r
1476 vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
\r
1477 vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
\r
1478 vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
\r
1479 vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
\r
1480 vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
\r
1481 vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
\r
1482 vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
\r
1483 vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
\r
1486 uint32_t etpu_reserved19; /* For single ETPU implementations */
\r
1488 uint32_t etpu_reserved20[10];
\r
1489 union { /* ETPU_A Channel Pending Service Status */
\r
1492 vuint32_t SR31:1; /* Channel 31 Pending Service Status */
\r
1493 vuint32_t SR30:1; /* Channel 30 Pending Service Status */
\r
1494 vuint32_t SR29:1; /* Channel 29 Pending Service Status */
\r
1495 vuint32_t SR28:1; /* Channel 28 Pending Service Status */
\r
1496 vuint32_t SR27:1; /* Channel 27 Pending Service Status */
\r
1497 vuint32_t SR26:1; /* Channel 26 Pending Service Status */
\r
1498 vuint32_t SR25:1; /* Channel 25 Pending Service Status */
\r
1499 vuint32_t SR24:1; /* Channel 24 Pending Service Status */
\r
1500 vuint32_t SR23:1; /* Channel 23 Pending Service Status */
\r
1501 vuint32_t SR22:1; /* Channel 22 Pending Service Status */
\r
1502 vuint32_t SR21:1; /* Channel 21 Pending Service Status */
\r
1503 vuint32_t SR20:1; /* Channel 20 Pending Service Status */
\r
1504 vuint32_t SR19:1; /* Channel 19 Pending Service Status */
\r
1505 vuint32_t SR18:1; /* Channel 18 Pending Service Status */
\r
1506 vuint32_t SR17:1; /* Channel 17 Pending Service Status */
\r
1507 vuint32_t SR16:1; /* Channel 16 Pending Service Status */
\r
1508 vuint32_t SR15:1; /* Channel 15 Pending Service Status */
\r
1509 vuint32_t SR14:1; /* Channel 14 Pending Service Status */
\r
1510 vuint32_t SR13:1; /* Channel 13 Pending Service Status */
\r
1511 vuint32_t SR12:1; /* Channel 12 Pending Service Status */
\r
1512 vuint32_t SR11:1; /* Channel 11 Pending Service Status */
\r
1513 vuint32_t SR10:1; /* Channel 10 Pending Service Status */
\r
1514 vuint32_t SR9:1; /* Channel 9 Pending Service Status */
\r
1515 vuint32_t SR8:1; /* Channel 8 Pending Service Status */
\r
1516 vuint32_t SR7:1; /* Channel 7 Pending Service Status */
\r
1517 vuint32_t SR6:1; /* Channel 6 Pending Service Status */
\r
1518 vuint32_t SR5:1; /* Channel 5 Pending Service Status */
\r
1519 vuint32_t SR4:1; /* Channel 4 Pending Service Status */
\r
1520 vuint32_t SR3:1; /* Channel 3 Pending Service Status */
\r
1521 vuint32_t SR2:1; /* Channel 2 Pending Service Status */
\r
1522 vuint32_t SR1:1; /* Channel 1 Pending Service Status */
\r
1523 vuint32_t SR0:1; /* Channel 0 Pending Service Status */
\r
1526 uint32_t etpu_reserved22; /* For single ETPU implementations */
\r
1528 uint32_t etpu_reserved20a[2];
\r
1530 union { /* ETPU_A Channel Service Status */
\r
1533 vuint32_t SS31:1; /* Channel 31 Service Status */
\r
1534 vuint32_t SS30:1; /* Channel 30 Service Status */
\r
1535 vuint32_t SS29:1; /* Channel 29 Service Status */
\r
1536 vuint32_t SS28:1; /* Channel 28 Service Status */
\r
1537 vuint32_t SS27:1; /* Channel 27 Service Status */
\r
1538 vuint32_t SS26:1; /* Channel 26 Service Status */
\r
1539 vuint32_t SS25:1; /* Channel 25 Service Status */
\r
1540 vuint32_t SS24:1; /* Channel 24 Service Status */
\r
1541 vuint32_t SS23:1; /* Channel 23 Service Status */
\r
1542 vuint32_t SS22:1; /* Channel 22 Service Status */
\r
1543 vuint32_t SS21:1; /* Channel 21 Service Status */
\r
1544 vuint32_t SS20:1; /* Channel 20 Service Status */
\r
1545 vuint32_t SS19:1; /* Channel 19 Service Status */
\r
1546 vuint32_t SS18:1; /* Channel 18 Service Status */
\r
1547 vuint32_t SS17:1; /* Channel 17 Service Status */
\r
1548 vuint32_t SS16:1; /* Channel 16 Service Status */
\r
1549 vuint32_t SS15:1; /* Channel 15 Service Status */
\r
1550 vuint32_t SS14:1; /* Channel 14 Service Status */
\r
1551 vuint32_t SS13:1; /* Channel 13 Service Status */
\r
1552 vuint32_t SS12:1; /* Channel 12 Service Status */
\r
1553 vuint32_t SS11:1; /* Channel 11 Service Status */
\r
1554 vuint32_t SS10:1; /* Channel 10 Service Status */
\r
1555 vuint32_t SS9:1; /* Channel 9 Service Status */
\r
1556 vuint32_t SS8:1; /* Channel 8 Service Status */
\r
1557 vuint32_t SS7:1; /* Channel 7 Service Status */
\r
1558 vuint32_t SS6:1; /* Channel 6 Service Status */
\r
1559 vuint32_t SS5:1; /* Channel 5 Service Status */
\r
1560 vuint32_t SS4:1; /* Channel 4 Service Status */
\r
1561 vuint32_t SS3:1; /* Channel 3 Service Status */
\r
1562 vuint32_t SS2:1; /* Channel 2 Service Status */
\r
1563 vuint32_t SS1:1; /* Channel 1 Service Status */
\r
1564 vuint32_t SS0:1; /* Channel 0 Service Status */
\r
1567 uint32_t etpu_reserved22a; /* For single ETPU implementations */
\r
1569 uint32_t etpu_reserved23[90];
\r
1571 /*****************************Channels********************************/
\r
1575 vuint32_t R; /* Channel Configuration Register */
\r
1577 vuint32_t CIE:1; /* Channel Interruput Enable */
\r
1578 vuint32_t DTRE:1; /* Data Transfer Request Enable */
\r
1579 vuint32_t CPR:2; /* Channel Priority */
\r
1581 vuint32_t ETCS:1; /* Entry Table Condition Select */
\r
1583 vuint32_t CFS:5; /* Channel Function Select */
\r
1584 vuint32_t ODIS:1; /* Output disable */
\r
1585 vuint32_t OPOL:1; /* output polarity */
\r
1587 vuint32_t CPBA:11; /* Channel Parameter Base Address */
\r
1591 vuint32_t R; /* Channel Status Control Register */
\r
1593 vuint32_t CIS:1; /* Channel Interruput Status */
\r
1594 vuint32_t CIOS:1; /* Channel Interruput Overflow Status */
\r
1596 vuint32_t DTRS:1; /* Data Transfer Status */
\r
1597 vuint32_t DTROS:1; /* Data Transfer Overflow Status */
\r
1599 vuint32_t IPS:1; /* Input Pin State */
\r
1600 vuint32_t OPS:1; /* Output Pin State */
\r
1601 vuint32_t OBE:1; /* Output Buffer Enable */
\r
1603 vuint32_t FM1:1; /* Function mode */
\r
1604 vuint32_t FM0:1; /* Function mode */
\r
1608 vuint32_t R; /* Channel Host Service Request Register */
\r
1610 vuint32_t:29; /* Host Service Request */
\r
1614 uint32_t etpu_reserved23;
\r
1618 /****************************************************************************/
\r
1619 /* MODULE : XBAR CrossBar */
\r
1620 /****************************************************************************/
\r
1621 CC_EXTENSION struct XBAR_tag {
\r
1628 vuint32_t MSTR6:3; /* FLEXRAY */
\r
1635 vuint32_t MSTR3:3; /* FEC */
\r
1638 vuint32_t MSTR2:3;
\r
1640 vuint32_t MSTR1:3;
\r
1642 vuint32_t MSTR0:3;
\r
1644 } MPR0; /* Master Priority Register for Slave Port 0 */
\r
1646 uint32_t xbar_reserved1[3];
\r
1659 } SGPCR0; /* General Purpose Control Register for Slave Port 0 */
\r
1661 uint32_t xbar_reserved2[59];
\r
1669 vuint32_t MSTR6:3; /* FLEXRAY */
\r
1676 vuint32_t MSTR3:3; /* FEC */
\r
1679 vuint32_t MSTR2:3;
\r
1681 vuint32_t MSTR1:3;
\r
1683 vuint32_t MSTR0:3;
\r
1685 } MPR1; /* Master Priority Register for Slave Port 1 */
\r
1687 uint32_t xbar_reserved3[3];
\r
1700 } SGPCR1; /* General Purpose Control Register for Slave Port 1 */
\r
1702 uint32_t xbar_reserved4[123];
\r
1710 vuint32_t MSTR6:3; /* FLEXRAY */
\r
1717 vuint32_t MSTR3:3; /* FEC */
\r
1720 vuint32_t MSTR2:3;
\r
1722 vuint32_t MSTR1:3;
\r
1724 vuint32_t MSTR0:3;
\r
1726 } MPR3; /* Master Priority Register for Slave Port 3 */
\r
1728 uint32_t xbar_reserved5[3];
\r
1741 } SGPCR3; /* General Purpose Control Register for Slave Port 3 */
\r
1742 uint32_t xbar_reserved6[187];
\r
1750 vuint32_t MSTR6:3; /* FLEXRAY */
\r
1757 vuint32_t MSTR3:3; /* FEC */
\r
1760 vuint32_t MSTR2:3;
\r
1762 vuint32_t MSTR1:3;
\r
1764 vuint32_t MSTR0:3;
\r
1766 } MPR6; /* Master Priority Register for Slave Port 6 */
\r
1768 uint32_t xbar_reserved7[3];
\r
1781 } SGPCR6; /* General Purpose Control Register for Slave Port 6 */
\r
1783 uint32_t xbar_reserved8[59];
\r
1791 vuint32_t MSTR6:3; /* FLEXRAY */
\r
1798 vuint32_t MSTR3:3; /* FEC */
\r
1801 vuint32_t MSTR2:3;
\r
1803 vuint32_t MSTR1:3;
\r
1805 vuint32_t MSTR0:3;
\r
1807 } MPR7; /* Master Priority Register for Slave Port 7 */
\r
1809 uint32_t xbar_reserved9[3];
\r
1822 } SGPCR7; /* General Purpose Control Register for Slave Port 7 */
\r
1825 /****************************************************************************/
\r
1826 /* MODULE : ECSM */
\r
1827 /****************************************************************************/
\r
1828 CC_EXTENSION struct ECSM_tag {
\r
1830 uint32_t ecsm_reserved1[5];
\r
1832 uint16_t ecsm_reserved2;
\r
1836 } SWTCR; //Software Watchdog Timer Control
\r
1838 uint8_t ecsm_reserved3[3];
\r
1842 } SWTSR; //SWT Service Register
\r
1844 uint8_t ecsm_reserved4[3];
\r
1848 } SWTIR; //SWT Interrupt Register
\r
1850 uint32_t ecsm_reserved5a[1];
\r
1855 vuint32_t FSBCR0:1;
\r
1856 vuint32_t FSBCR1:1;
\r
1857 vuint32_t FSBCR2:1;
\r
1858 vuint32_t FSBCR3:1;
\r
1859 vuint32_t FSBCR4:1;
\r
1860 vuint32_t FSBCR5:1;
\r
1861 vuint32_t FSBCR6:1;
\r
1862 vuint32_t FSBCR7:1;
\r
1865 vuint32_t ACCERR:1;
\r
1868 } FSBMCR; /* FEC System Bus Master Control Register */
\r
1870 uint32_t ecsm_reserved5c[6];
\r
1872 uint8_t ecsm_reserved6[3];
\r
1881 } ECR; //ECC Configuration Register
\r
1883 uint8_t mcm_reserved8[3];
\r
1892 } ESR; //ECC Status Register
\r
1894 uint16_t ecsm_reserved9;
\r
1900 vuint16_t FRCNCI:1;
\r
1901 vuint16_t FR1NCI:1;
\r
1903 vuint16_t ERRBIT:7;
\r
1905 } EEGR; //ECC Error Generation Register
\r
1907 uint32_t ecsm_reserved10;
\r
1912 vuint32_t FEAR:32;
\r
1914 } FEAR; //Flash ECC Address Register
\r
1916 uint16_t ecsm_reserved11;
\r
1924 } FEMR; //Flash ECC Master Register
\r
1936 } FEAT; //Flash ECC Attributes Register
\r
1941 vuint32_t FEDH:32;
\r
1943 } FEDRH; //Flash ECC Data High Register
\r
1948 vuint32_t FEDL:32;
\r
1950 } FEDRL; //Flash ECC Data Low Register
\r
1955 vuint32_t REAR:32;
\r
1957 } REAR; //RAM ECC Address
\r
1959 uint8_t ecsm_reserved12[2];
\r
1967 } REMR; //RAM ECC Master
\r
1979 } REAT; // RAM ECC Attributes Register
\r
1984 vuint32_t REDH:32;
\r
1986 } REDRH; //RAM ECC Data High Register
\r
1991 vuint32_t REDL:32;
\r
1993 } REDRL; //RAMECC Data Low Register
\r
1996 /****************************************************************************/
\r
1997 /* MODULE : eDMA */
\r
1998 /****************************************************************************/
\r
1999 #include "ip_edma.h"
\r
2001 /****************************************************************************/
\r
2002 /* MODULE : INTC */
\r
2003 /****************************************************************************/
\r
2004 CC_EXTENSION struct INTC_tag {
\r
2013 } MCR; /* Module Configuration Register */
\r
2015 int32_t INTC_reserved00;
\r
2023 } CPR; /* Current Priority Register */
\r
2025 uint32_t intc_reserved1;
\r
2030 vuint32_t VTBA:21;
\r
2031 vuint32_t INTVEC:9;
\r
2034 } IACKR; /* Interrupt Acknowledge Register */
\r
2036 uint32_t intc_reserved2;
\r
2043 } EOIR; /* End of Interrupt Register */
\r
2045 uint32_t intc_reserved3;
\r
2054 } SSCIR[8]; /* Software Set/Clear Interruput Register */
\r
2056 uint32_t intc_reserved4[6];
\r
2064 } PSR[358]; /* Software Set/Clear Interrupt Register */
\r
2067 /****************************************************************************/
\r
2068 /* MODULE : EQADC */
\r
2069 /****************************************************************************/
\r
2070 CC_EXTENSION struct EQADC_tag {
\r
2075 vuint32_t ESSIE:2;
\r
2079 } MCR; /* Module Configuration Register */
\r
2081 int32_t EQADC_reserved00;
\r
2089 } NMSFR; /* Null Message Send Format Register */
\r
2097 } ETDFR; /* External Trigger Digital Filter Register */
\r
2102 vuint32_t CFPUSH:32;
\r
2104 } CFPR[6]; /* CFIFO Push Registers */
\r
2106 uint32_t eqadc_reserved1;
\r
2108 uint32_t eqadc_reserved2;
\r
2114 vuint32_t RFPOP:16;
\r
2116 } RFPR[6]; /* Result FIFO Pop Registers */
\r
2118 uint32_t eqadc_reserved3;
\r
2120 uint32_t eqadc_reserved4;
\r
2127 vuint16_t CFINV:1;
\r
2132 } CFCR[6]; /* CFIFO Control Registers */
\r
2134 uint32_t eqadc_reserved5;
\r
2140 vuint16_t TORIE:1;
\r
2142 vuint16_t EOQIE:1;
\r
2143 vuint16_t CFUIE:1;
\r
2148 vuint16_t RFOIE:1;
\r
2153 } IDCR[6]; /* Interrupt and DMA Control Registers */
\r
2155 uint32_t eqadc_reserved6;
\r
2172 vuint32_t CFCTR:4;
\r
2173 vuint32_t TNXTPTR:4;
\r
2174 vuint32_t RFCTR:4;
\r
2175 vuint32_t POPNXTPTR:4;
\r
2177 } FISR[6]; /* FIFO and Interrupt Status Registers */
\r
2179 uint32_t eqadc_reserved7;
\r
2181 uint32_t eqadc_reserved8;
\r
2187 vuint16_t TCCF:11;
\r
2189 } CFTCR[6]; /* CFIFO Transfer Counter Registers */
\r
2191 uint32_t eqadc_reserved9;
\r
2203 vuint32_t LCFTCB0:4;
\r
2204 vuint32_t TC_LCFTCB0:11;
\r
2206 } CFSSR0; /* CFIFO Status Register 0 */
\r
2218 vuint32_t LCFTCB1:4;
\r
2219 vuint32_t TC_LCFTCB1:11;
\r
2221 } CFSSR1; /* CFIFO Status Register 1 */
\r
2233 vuint32_t ECBNI:1;
\r
2234 vuint32_t LCFTSSI:4;
\r
2235 vuint32_t TC_LCFTSSI:11;
\r
2237 } CFSSR2; /* CFIFO Status Register 2 */
\r
2252 uint32_t eqadc_reserved11;
\r
2262 } SSICR; /* SSI Control Register */
\r
2269 vuint32_t RDATA:26;
\r
2271 } SSIRDR; /* SSI Recieve Data Register */
\r
2273 uint32_t eqadc_reserved12[17];
\r
2283 uint32_t eqadc_reserved13[12];
\r
2287 uint32_t eqadc_reserved14[32];
\r
2297 uint32_t eqadc_reserved15[12];
\r
2302 /****************************************************************************/
\r
2303 /* MODULE : DSPI */
\r
2304 /****************************************************************************/
\r
2310 vuint32_t CONT_SCKE:1;
\r
2311 vuint32_t DCONF:2;
\r
2314 vuint32_t PCSSE:1;
\r
2317 vuint32_t PCSIS5:1;
\r
2318 vuint32_t PCSIS4:1;
\r
2319 vuint32_t PCSIS3:1;
\r
2320 vuint32_t PCSIS2:1;
\r
2321 vuint32_t PCSIS1:1;
\r
2322 vuint32_t PCSIS0:1;
\r
2325 vuint32_t DIS_TXF:1;
\r
2326 vuint32_t DIS_RXF:1;
\r
2327 vuint32_t CLR_TXF:1;
\r
2328 vuint32_t CLR_RXF:1;
\r
2329 vuint32_t SMPL_PT:2;
\r
2333 } MCR; /* Module Configuration Register */
\r
2335 uint32_t dspi_reserved1;
\r
2340 vuint32_t TCNT:16;
\r
2352 vuint32_t LSBFE:1;
\r
2353 vuint32_t PCSSCK:2;
\r
2357 vuint32_t CSSCK:4;
\r
2362 } CTAR[8]; /* Clock and Transfer Attributes Registers */
\r
2368 vuint32_t TXRXS:1;
\r
2379 vuint32_t TXCTR:4;
\r
2380 vuint32_t TXNXTPTR:4;
\r
2381 vuint32_t RXCTR:4;
\r
2382 vuint32_t POPNXTPTR:4;
\r
2384 } SR; /* Status Register */
\r
2389 vuint32_t TCFRE:1;
\r
2391 vuint32_t EOQFRE:1;
\r
2392 vuint32_t TFUFRE:1;
\r
2394 vuint32_t TFFFRE:1;
\r
2395 vuint32_t TFFFDIRS:1;
\r
2397 vuint32_t RFOFRE:1;
\r
2399 vuint32_t RFDFRE:1;
\r
2400 vuint32_t RFDFDIRS:1;
\r
2403 } RSER; /* DMA/Interrupt Request Select and Enable Register */
\r
2411 vuint32_t CTCNT:1;
\r
2419 vuint32_t TXDATA:16;
\r
2421 } PUSHR; /* PUSH TX FIFO Register */
\r
2427 vuint32_t RXDATA:16;
\r
2429 } POPR; /* POP RX FIFO Register */
\r
2434 vuint32_t TXCMD:16;
\r
2435 vuint32_t TXDATA:16;
\r
2437 } TXFR[4]; /* Transmit FIFO Registers */
\r
2439 vuint32_t DSPI_reserved_txf[12];
\r
2445 vuint32_t RXDATA:16;
\r
2447 } RXFR[4]; /* Transmit FIFO Registers */
\r
2449 vuint32_t DSPI_reserved_rxf[12];
\r
2456 vuint32_t MTOCNT:6;
\r
2462 vuint32_t DCONT:1;
\r
2463 vuint32_t DSICTAS:3;
\r
2465 vuint32_t DPCS5:1;
\r
2466 vuint32_t DPCS4:1;
\r
2467 vuint32_t DPCS3:1;
\r
2468 vuint32_t DPCS2:1;
\r
2469 vuint32_t DPCS1:1;
\r
2470 vuint32_t DPCS0:1;
\r
2472 } DSICR; /* DSI Configuration Register */
\r
2478 vuint32_t SER_DATA:16;
\r
2480 } SDR; /* DSI Serialization Data Register */
\r
2486 vuint32_t ASER_DATA:16;
\r
2488 } ASDR; /* DSI Alternate Serialization Data Register */
\r
2494 vuint32_t COMP_DATA:16;
\r
2496 } COMPR; /* DSI Transmit Comparison Register */
\r
2502 vuint32_t DESER_DATA:16;
\r
2504 } DDR; /* DSI deserialization Data Register */
\r
2507 /****************************************************************************/
\r
2508 /* MODULE : eSCI */
\r
2509 /****************************************************************************/
\r
2510 CC_EXTENSION struct ESCI_tag {
\r
2516 vuint32_t LOOPS:1;
\r
2517 vuint32_t SCISDOZ:1;
\r
2533 } CR1; /* Control Register 1 */
\r
2541 vuint16_t IEBERR:1;
\r
2542 vuint16_t RXDMA:1;
\r
2543 vuint16_t TXDMA:1;
\r
2544 vuint16_t BRK13:1;
\r
2546 vuint16_t BESM13:1;
\r
2547 vuint16_t SBSTP:1;
\r
2554 } CR2; /* Control Register 2 */
\r
2564 } DR; /* Data Register */
\r
2581 vuint32_t RXRDY:1;
\r
2582 vuint32_t TXRDY:1;
\r
2583 vuint32_t LWAKE:1;
\r
2585 vuint32_t PBERR:1;
\r
2587 vuint32_t CKERR:1;
\r
2592 } SR; /* Status Register */
\r
2617 } LCR; /* LIN Control Register */
\r
2621 } LTR; /* LIN Transmit Register */
\r
2625 } LRR; /* LIN Recieve Register */
\r
2629 } LPR; /* LIN CRC Polynom Register */
\r
2632 /****************************************************************************/
\r
2633 /* MODULE : FlexCAN */
\r
2634 /****************************************************************************/
\r
2635 CC_EXTENSION struct FLEXCAN2_tag {
\r
2643 vuint32_t NOTRDY:1;
\r
2645 vuint32_t SOFTRST:1;
\r
2646 vuint32_t FRZACK:1;
\r
2650 vuint32_t WRNEN:1;
\r
2652 vuint32_t MDISACK:1;
\r
2656 vuint32_t SRXDIS:1;
\r
2657 vuint32_t MBFEN:1;
\r
2660 vuint32_t MAXMB:6;
\r
2662 } MCR; /* Module Configuration Register */
\r
2667 vuint32_t PRESDIV:8;
\r
2669 vuint32_t PSEG1:3;
\r
2670 vuint32_t PSEG2:3;
\r
2671 vuint32_t BOFFMSK:1;
\r
2672 vuint32_t ERRMSK:1;
\r
2673 vuint32_t CLKSRC:1;
\r
2676 vuint32_t TWRNMSK:1;
\r
2677 vuint32_t RWRNMSK:1;
\r
2681 vuint32_t BOFFREC:1;
\r
2685 vuint32_t PROPSEG:3;
\r
2687 } CR; /* Control Register */
\r
2691 } TIMER; /* Free Running Timer */
\r
2692 int32_t FLEXCAN_reserved00;
\r
2700 } RXGMASK; /* RX Global Mask */
\r
2708 } RX14MASK; /* RX 14 Mask */
\r
2716 } RX15MASK; /* RX 15 Mask */
\r
2722 vuint32_t RXECNT:8;
\r
2723 vuint32_t TXECNT:8;
\r
2725 } ECR; /* Error Counter Register */
\r
2732 vuint32_t TWRNINT:1;
\r
2733 vuint32_t RWRNINT:1;
\r
2735 vuint32_t BIT1ERR:1;
\r
2736 vuint32_t BIT0ERR:1;
\r
2737 vuint32_t ACKERR:1;
\r
2738 vuint32_t CRCERR:1;
\r
2739 vuint32_t FRMERR:1;
\r
2740 vuint32_t STFERR:1;
\r
2741 vuint32_t TXWRN:1;
\r
2742 vuint32_t RXWRN:1;
\r
2745 vuint32_t FLTCONF:2;
\r
2747 vuint32_t BOFFINT:1;
\r
2748 vuint32_t ERRINT:1;
\r
2751 } ESR; /* Error and Status Register */
\r
2756 vuint32_t BUF63M:1;
\r
2757 vuint32_t BUF62M:1;
\r
2758 vuint32_t BUF61M:1;
\r
2759 vuint32_t BUF60M:1;
\r
2760 vuint32_t BUF59M:1;
\r
2761 vuint32_t BUF58M:1;
\r
2762 vuint32_t BUF57M:1;
\r
2763 vuint32_t BUF56M:1;
\r
2764 vuint32_t BUF55M:1;
\r
2765 vuint32_t BUF54M:1;
\r
2766 vuint32_t BUF53M:1;
\r
2767 vuint32_t BUF52M:1;
\r
2768 vuint32_t BUF51M:1;
\r
2769 vuint32_t BUF50M:1;
\r
2770 vuint32_t BUF49M:1;
\r
2771 vuint32_t BUF48M:1;
\r
2772 vuint32_t BUF47M:1;
\r
2773 vuint32_t BUF46M:1;
\r
2774 vuint32_t BUF45M:1;
\r
2775 vuint32_t BUF44M:1;
\r
2776 vuint32_t BUF43M:1;
\r
2777 vuint32_t BUF42M:1;
\r
2778 vuint32_t BUF41M:1;
\r
2779 vuint32_t BUF40M:1;
\r
2780 vuint32_t BUF39M:1;
\r
2781 vuint32_t BUF38M:1;
\r
2782 vuint32_t BUF37M:1;
\r
2783 vuint32_t BUF36M:1;
\r
2784 vuint32_t BUF35M:1;
\r
2785 vuint32_t BUF34M:1;
\r
2786 vuint32_t BUF33M:1;
\r
2787 vuint32_t BUF32M:1;
\r
2789 } IMRH; /* Interruput Masks Register */
\r
2794 vuint32_t BUF31M:1;
\r
2795 vuint32_t BUF30M:1;
\r
2796 vuint32_t BUF29M:1;
\r
2797 vuint32_t BUF28M:1;
\r
2798 vuint32_t BUF27M:1;
\r
2799 vuint32_t BUF26M:1;
\r
2800 vuint32_t BUF25M:1;
\r
2801 vuint32_t BUF24M:1;
\r
2802 vuint32_t BUF23M:1;
\r
2803 vuint32_t BUF22M:1;
\r
2804 vuint32_t BUF21M:1;
\r
2805 vuint32_t BUF20M:1;
\r
2806 vuint32_t BUF19M:1;
\r
2807 vuint32_t BUF18M:1;
\r
2808 vuint32_t BUF17M:1;
\r
2809 vuint32_t BUF16M:1;
\r
2810 vuint32_t BUF15M:1;
\r
2811 vuint32_t BUF14M:1;
\r
2812 vuint32_t BUF13M:1;
\r
2813 vuint32_t BUF12M:1;
\r
2814 vuint32_t BUF11M:1;
\r
2815 vuint32_t BUF10M:1;
\r
2816 vuint32_t BUF09M:1;
\r
2817 vuint32_t BUF08M:1;
\r
2818 vuint32_t BUF07M:1;
\r
2819 vuint32_t BUF06M:1;
\r
2820 vuint32_t BUF05M:1;
\r
2821 vuint32_t BUF04M:1;
\r
2822 vuint32_t BUF03M:1;
\r
2823 vuint32_t BUF02M:1;
\r
2824 vuint32_t BUF01M:1;
\r
2825 vuint32_t BUF00M:1;
\r
2827 } IMRL; /* Interruput Masks Register */
\r
2832 vuint32_t BUF63I:1;
\r
2833 vuint32_t BUF62I:1;
\r
2834 vuint32_t BUF61I:1;
\r
2835 vuint32_t BUF60I:1;
\r
2836 vuint32_t BUF59I:1;
\r
2837 vuint32_t BUF58I:1;
\r
2838 vuint32_t BUF57I:1;
\r
2839 vuint32_t BUF56I:1;
\r
2840 vuint32_t BUF55I:1;
\r
2841 vuint32_t BUF54I:1;
\r
2842 vuint32_t BUF53I:1;
\r
2843 vuint32_t BUF52I:1;
\r
2844 vuint32_t BUF51I:1;
\r
2845 vuint32_t BUF50I:1;
\r
2846 vuint32_t BUF49I:1;
\r
2847 vuint32_t BUF48I:1;
\r
2848 vuint32_t BUF47I:1;
\r
2849 vuint32_t BUF46I:1;
\r
2850 vuint32_t BUF45I:1;
\r
2851 vuint32_t BUF44I:1;
\r
2852 vuint32_t BUF43I:1;
\r
2853 vuint32_t BUF42I:1;
\r
2854 vuint32_t BUF41I:1;
\r
2855 vuint32_t BUF40I:1;
\r
2856 vuint32_t BUF39I:1;
\r
2857 vuint32_t BUF38I:1;
\r
2858 vuint32_t BUF37I:1;
\r
2859 vuint32_t BUF36I:1;
\r
2860 vuint32_t BUF35I:1;
\r
2861 vuint32_t BUF34I:1;
\r
2862 vuint32_t BUF33I:1;
\r
2863 vuint32_t BUF32I:1;
\r
2865 } IFRH; /* Interruput Flag Register */
\r
2870 vuint32_t BUF31I:1;
\r
2871 vuint32_t BUF30I:1;
\r
2872 vuint32_t BUF29I:1;
\r
2873 vuint32_t BUF28I:1;
\r
2874 vuint32_t BUF27I:1;
\r
2875 vuint32_t BUF26I:1;
\r
2876 vuint32_t BUF25I:1;
\r
2877 vuint32_t BUF24I:1;
\r
2878 vuint32_t BUF23I:1;
\r
2879 vuint32_t BUF22I:1;
\r
2880 vuint32_t BUF21I:1;
\r
2881 vuint32_t BUF20I:1;
\r
2882 vuint32_t BUF19I:1;
\r
2883 vuint32_t BUF18I:1;
\r
2884 vuint32_t BUF17I:1;
\r
2885 vuint32_t BUF16I:1;
\r
2886 vuint32_t BUF15I:1;
\r
2887 vuint32_t BUF14I:1;
\r
2888 vuint32_t BUF13I:1;
\r
2889 vuint32_t BUF12I:1;
\r
2890 vuint32_t BUF11I:1;
\r
2891 vuint32_t BUF10I:1;
\r
2892 vuint32_t BUF09I:1;
\r
2893 vuint32_t BUF08I:1;
\r
2894 vuint32_t BUF07I:1;
\r
2895 vuint32_t BUF06I:1;
\r
2896 vuint32_t BUF05I:1;
\r
2897 vuint32_t BUF04I:1;
\r
2898 vuint32_t BUF03I:1;
\r
2899 vuint32_t BUF02I:1;
\r
2900 vuint32_t BUF01I:1;
\r
2901 vuint32_t BUF00I:1;
\r
2903 } IFRL; /* Interruput Flag Register */
\r
2905 uint32_t flexcan2_reserved2[19];
\r
2917 vuint32_t LENGTH:4;
\r
2918 vuint32_t TIMESTAMP:16;
\r
2926 vuint32_t STD_ID:11;
\r
2927 vuint32_t EXT_ID:18;
\r
2932 vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
\r
2933 vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
\r
2934 vuint32_t W[2]; /* Data buffer in words (32 bits) */
\r
2935 vuint32_t R[2]; /* Data buffer in words (32 bits) */
\r
2940 uint32_t flexcan2_reserved3[256];
\r
2948 } RXIMR[64]; /* RX Individual Mask Registers */
\r
2951 /****************************************************************************/
\r
2952 /* MODULE : FEC */
\r
2953 /****************************************************************************/
\r
2954 CC_EXTENSION struct FEC_tag {
\r
2956 uint32_t fec_reserved_start[0x1];
\r
2961 vuint32_t HBERR:1;
\r
2970 vuint32_t EBERR:1;
\r
2976 } EIR; /* Interrupt Event Register */
\r
2981 vuint32_t HBERRM:1;
\r
2982 vuint32_t BABRM:1;
\r
2983 vuint32_t BABTM:1;
\r
2990 vuint32_t EBERRM:1;
\r
2996 } EIMR; /* Interrupt Mask Register */
\r
2998 uint32_t fec_reserved_eimr;
\r
3004 vuint32_t R_DES_ACTIVE:1;
\r
3007 } RDAR; /* Receive Descriptor Active Register */
\r
3013 vuint32_t X_DES_ACTIVE:1;
\r
3016 } TDAR; /* Transmit Descriptor Active Register */
\r
3018 uint32_t fec_reserved_tdar[3];
\r
3024 vuint32_t ETHER_EN:1;
\r
3025 vuint32_t RESET:1;
\r
3027 } ECR; /* Ethernet Control Register */
\r
3029 uint32_t fec_reserved_ecr[6];
\r
3039 vuint32_t DATA:16;
\r
3041 } MDATA; /* MII Data Register */
\r
3047 vuint32_t DIS_PREAMBLE:1;
\r
3048 vuint32_t MII_SPEED:6;
\r
3051 } MSCR; /* MII Speed Control Register */
\r
3053 uint32_t fec_reserved_mscr[7];
\r
3058 vuint32_t MIB_DISABLE:1;
\r
3059 vuint32_t MIB_IDLE:1;
\r
3062 } MIBC; /* MIB Control Register */
\r
3064 uint32_t fec_reserved_mibc[7];
\r
3070 vuint32_t MAX_FL:11;
\r
3073 vuint32_t BC_REJ:1;
\r
3075 vuint32_t MII_MODE:1;
\r
3079 } RCR; /* Receive Control Register */
\r
3081 uint32_t fec_reserved_rcr[15];
\r
3087 vuint32_t RFC_PAUSE:1;
\r
3088 vuint32_t TFC_PAUSE:1;
\r
3093 } TCR; /* Transmit Control Register */
\r
3095 uint32_t fec_reserved_tcr[7];
\r
3100 vuint32_t PADDR1:32;
\r
3102 } PALR; /* Physical Address Low Register */
\r
3107 vuint32_t PADDR2:16;
\r
3108 vuint32_t TYPE:16;
\r
3110 } PAUR; /* Physical Address High + Type Register */
\r
3115 vuint32_t OPCODE:16;
\r
3116 vuint32_t PAUSE_DUR:16;
\r
3118 } OPD; /* Opcode/Pause Duration Register */
\r
3120 uint32_t fec_reserved_opd[10];
\r
3125 vuint32_t IADDR1:32;
\r
3127 } IAUR; /* Descriptor Individual Upper Address Register */
\r
3132 vuint32_t IADDR2:32;
\r
3134 } IALR; /* Descriptor Individual Lower Address Register */
\r
3139 vuint32_t GADDR1:32;
\r
3141 } GAUR; /* Descriptor Group Upper Address Register */
\r
3146 vuint32_t GADDR2:32;
\r
3148 } GALR; /* Descriptor Group Lower Address Register */
\r
3150 uint32_t fec_reserved_galr[7];
\r
3156 vuint32_t X_WMRK:2;
\r
3158 } TFWR; /* FIFO Transmit FIFO Watermark Register */
\r
3160 uint32_t fec_reserved_tfwr;
\r
3166 vuint32_t R_BOUND:8;
\r
3169 } FRBR; /* FIFO Receive Bound Register */
\r
3175 vuint32_t R_FSTART:8;
\r
3178 } FRSR; /* FIFO Receive Start Register */
\r
3180 uint32_t fec_reserved_frsr[11];
\r
3185 vuint32_t R_DES_START:30;
\r
3188 } ERDSR; /* Receive Descriptor Ring Start Register */
\r
3193 vuint32_t X_DES_START:30;
\r
3196 } ETDSR; /* Transmit Descriptor Ring Start Register */
\r
3202 vuint32_t R_BUF_SIZE:7;
\r
3205 } EMRBR; /* Receive Buffer Size Register */
\r
3207 uint32_t fec_reserved_emrbr[29];
\r
3211 } RMON_T_DROP; /* Count of frames not counted correctly */
\r
3215 } RMON_T_PACKETS; /* RMON Tx packet count */
\r
3219 } RMON_T_BC_PKT; /* RMON Tx Broadcast Packets */
\r
3223 } RMON_T_MC_PKT; /* RMON Tx Multicast Packets */
\r
3227 } RMON_T_CRC_ALIGN; /* RMON Tx Packets w CRC/Align error */
\r
3231 } RMON_T_UNDERSIZE; /* RMON Tx Packets < 64 bytes, good crc */
\r
3235 } RMON_T_OVERSIZE; /* RMON Tx Packets > MAX_FL bytes, good crc */
\r
3239 } RMON_T_FRAG; /* RMON Tx Packets < 64 bytes, bad crc */
\r
3243 } RMON_T_JAB; /* RMON Tx Packets > MAX_FL bytes, bad crc */
\r
3247 } RMON_T_COL; /* RMON Tx collision count */
\r
3251 } RMON_T_P64; /* RMON Tx 64 byte packets */
\r
3255 } RMON_T_P65TO127; /* RMON Tx 65 to 127 byte packets */
\r
3259 } RMON_T_P128TO255; /* RMON Tx 128 to 255 byte packets */
\r
3263 } RMON_T_P256TO511; /* RMON Tx 256 to 511 byte packets */
\r
3267 } RMON_T_P512TO1023; /* RMON Tx 512 to 1023 byte packets */
\r
3271 } RMON_T_P1024TO2047; /* RMON Tx 1024 to 2047 byte packets */
\r
3275 } RMON_T_P_GTE2048; /* RMON Tx packets w > 2048 bytes */
\r
3279 } RMON_T_OCTETS; /* RMON Tx Octets */
\r
3283 } IEEE_T_DROP; /* Count of frames not counted correctly */
\r
3287 } IEEE_T_FRAME_OK; /* Frames Transmitted OK */
\r
3291 } IEEE_T_1COL; /* Frames Transmitted with Single Collision */
\r
3295 } IEEE_T_MCOL; /* Frames Transmitted with Multiple Collisions */
\r
3299 } IEEE_T_DEF; /* Frames Transmitted after Deferral Delay */
\r
3303 } IEEE_T_LCOL; /* Frames Transmitted with Late Collision */
\r
3307 } IEEE_T_EXCOL; /* Frames Transmitted with Excessive Collisions */
\r
3311 } IEEE_T_MACERR; /* Frames Transmitted with Tx FIFO Underrun */
\r
3315 } IEEE_T_CSERR; /* Frames Transmitted with Carrier Sense Error */
\r
3319 } IEEE_T_SQE; /* Frames Transmitted with SQE Error */
\r
3323 } IEEE_T_FDXFC; /* Flow Control Pause frames transmitted */
\r
3327 } IEEE_T_OCTETS_OK; /* Octet count for Frames Transmitted w/o Error */
\r
3329 uint32_t fec_reserved_rmon_t_octets_ok[2];
\r
3333 } RMON_R_DROP; /* Count of frames not counted correctly */
\r
3337 } RMON_R_PACKETS; /* RMON Rx packet count */
\r
3341 } RMON_R_BC_PKT; /* RMON Rx Broadcast Packets */
\r
3345 } RMON_R_MC_PKT; /* RMON Rx Multicast Packets */
\r
3349 } RMON_R_CRC_ALIGN; /* RMON Rx Packets w CRC/Align error */
\r
3353 } RMON_R_UNDERSIZE; /* RMON Rx Packets < 64 bytes, good crc */
\r
3357 } RMON_R_OVERSIZE; /* RMON Rx Packets > MAX_FL bytes, good crc */
\r
3361 } RMON_R_FRAG; /* RMON Rx Packets < 64 bytes, bad crc */
\r
3365 } RMON_R_JAB; /* RMON Rx Packets > MAX_FL bytes, bad crc */
\r
3367 uint32_t fec_reserved_rmon_r_jab;
\r
3371 } RMON_R_P64; /* RMON Rx 64 byte packets */
\r
3375 } RMON_R_P65TO127; /* RMON Rx 65 to 127 byte packets */
\r
3379 } RMON_R_P128TO255; /* RMON Rx 128 to 255 byte packets */
\r
3383 } RMON_R_P256TO511; /* RMON Rx 256 to 511 byte packets */
\r
3387 } RMON_R_P512TO1023; /* RMON Rx 512 to 1023 byte packets */
\r
3391 } RMON_R_P1024TO2047; /* RMON Rx 1024 to 2047 byte packets */
\r
3395 } RMON_R_P_GTE2048; /* RMON Rx packets w > 2048 bytes */
\r
3399 } RMON_R_OCTETS; /* RMON Rx Octets */
\r
3403 } IEEE_R_DROP; /* Count of frames not counted correctly */
\r
3407 } IEEE_R_FRAME_OK; /* Frames Received OK */
\r
3411 } IEEE_R_CRC; /* Frames Received with CRC Error */
\r
3415 } IEEE_R_ALIGN; /* Frames Received with Alignment Error */
\r
3419 } IEEE_R_MACERR; /* Receive Fifo Overflow count */
\r
3423 } IEEE_R_FDXFC; /* Flow Control Pause frames received */
\r
3427 } IEEE_R_OCTETS_OK; /* Octet count for Frames Rcvd w/o Error */
\r
3430 /****************************************************************************/
\r
3431 /* MODULE : FlexRay */
\r
3432 /****************************************************************************/
\r
3434 CC_EXTENSION typedef union uMVR {
\r
3437 vuint16_t CHIVER:8; /* CHI Version Number */
\r
3438 vuint16_t PEVER:8; /* PE Version Number */
\r
3442 CC_EXTENSION typedef union uMCR {
\r
3445 vuint16_t MEN:1; /* module enable */
\r
3447 vuint16_t SCMD:1; /* single channel mode */
\r
3448 vuint16_t CHB:1; /* channel B enable */
\r
3449 vuint16_t CHA:1; /* channel A enable */
\r
3450 vuint16_t SFFE:1; /* synchronization frame filter enable */
\r
3452 vuint16_t CLKSEL:1; /* protocol engine clock source select */
\r
3453 vuint16_t PRESCALE:3; /* protocol engine clock prescaler */
\r
3457 CC_EXTENSION typedef union uSTBSCR {
\r
3460 vuint16_t WMD:1; /* write mode */
\r
3461 vuint16_t STBSSEL:7; /* strobe signal select */
\r
3463 vuint16_t ENB:1; /* strobe signal enable */
\r
3465 vuint16_t STBPSEL:2; /* strobe port select */
\r
3468 CC_EXTENSION typedef union uSTBPCR {
\r
3472 vuint16_t STB3EN:1; /* strobe port enable */
\r
3473 vuint16_t STB2EN:1; /* strobe port enable */
\r
3474 vuint16_t STB1EN:1; /* strobe port enable */
\r
3475 vuint16_t STB0EN:1; /* strobe port enable */
\r
3479 CC_EXTENSION typedef union uMBDSR {
\r
3483 vuint16_t MBSEG2DS:7; /* message buffer segment 2 data size */
\r
3485 vuint16_t MBSEG1DS:7; /* message buffer segment 1 data size */
\r
3488 CC_EXTENSION typedef union uMBSSUTR {
\r
3493 vuint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */
\r
3495 vuint16_t LAST_MB_UTIL:7; /* last message buffer utilized */
\r
3499 CC_EXTENSION typedef union uPOCR {
\r
3503 vuint16_t WME:1; /* write mode external correction command */
\r
3505 vuint16_t EOC_AP:2; /* external offset correction application */
\r
3506 vuint16_t ERC_AP:2; /* external rate correction application */
\r
3507 vuint16_t BSY:1; /* command write busy / write mode command */
\r
3509 vuint16_t POCCMD:4; /* protocol command */
\r
3512 /* protocol commands */
\r
3513 CC_EXTENSION typedef union uGIFER {
\r
3516 vuint16_t MIF:1; /* module interrupt flag */
\r
3517 vuint16_t PRIF:1; /* protocol interrupt flag */
\r
3518 vuint16_t CHIF:1; /* CHI interrupt flag */
\r
3519 vuint16_t WKUPIF:1; /* wakeup interrupt flag */
\r
3520 vuint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
\r
3521 vuint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
\r
3522 vuint16_t RBIF:1; /* receive message buffer interrupt flag */
\r
3523 vuint16_t TBIF:1; /* transmit buffer interrupt flag */
\r
3524 vuint16_t MIE:1; /* module interrupt enable */
\r
3525 vuint16_t PRIE:1; /* protocol interrupt enable */
\r
3526 vuint16_t CHIE:1; /* CHI interrupt enable */
\r
3527 vuint16_t WKUPIE:1; /* wakeup interrupt enable */
\r
3528 vuint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
\r
3529 vuint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
\r
3530 vuint16_t RBIE:1; /* receive message buffer interrupt enable */
\r
3531 vuint16_t TBIE:1; /* transmit buffer interrupt enable */
\r
3534 CC_EXTENSION typedef union uPIFR0 {
\r
3537 vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */
\r
3538 vuint16_t INTLIF:1; /* internal protocol error interrupt flag */
\r
3539 vuint16_t ILCFIF:1; /* illegal protocol configuration flag */
\r
3540 vuint16_t CSAIF:1; /* cold start abort interrupt flag */
\r
3541 vuint16_t MRCIF:1; /* missing rate correctio interrupt flag */
\r
3542 vuint16_t MOCIF:1; /* missing offset correctio interrupt flag */
\r
3543 vuint16_t CCLIF:1; /* clock correction limit reached interrupt flag */
\r
3544 vuint16_t MXSIF:1; /* max sync frames detected interrupt flag */
\r
3545 vuint16_t MTXIF:1; /* media access test symbol received flag */
\r
3546 vuint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
\r
3547 vuint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
\r
3548 vuint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
\r
3549 vuint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
\r
3550 vuint16_t TI2IF:1; /* timer 2 expired interrupt flag */
\r
3551 vuint16_t TI1IF:1; /* timer 1 expired interrupt flag */
\r
3552 vuint16_t CYSIF:1; /* cycle start interrupt flag */
\r
3555 CC_EXTENSION typedef union uPIFR1 {
\r
3558 vuint16_t EMCIF:1; /* error mode changed interrupt flag */
\r
3559 vuint16_t IPCIF:1; /* illegal protocol command interrupt flag */
\r
3560 vuint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
\r
3561 vuint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */
\r
3562 vuint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
\r
3563 vuint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
\r
3564 vuint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
\r
3565 vuint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
\r
3567 vuint16_t EVTIF:1; /* even cycle table written interrupt flag */
\r
3568 vuint16_t ODTIF:1; /* odd cycle table written interrupt flag */
\r
3572 CC_EXTENSION typedef union uPIER0 {
\r
3575 vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */
\r
3576 vuint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */
\r
3577 vuint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
\r
3578 vuint16_t CSAIE:1; /* cold start abort interrupt enable */
\r
3579 vuint16_t MRCIE:1; /* missing rate correctio interrupt enable */
\r
3580 vuint16_t MOCIE:1; /* missing offset correctio interrupt enable */
\r
3581 vuint16_t CCLIE:1; /* clock correction limit reached interrupt enable */
\r
3582 vuint16_t MXSIE:1; /* max sync frames detected interrupt enable */
\r
3583 vuint16_t MTXIE:1; /* media access test symbol received interrupt enable */
\r
3584 vuint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
\r
3585 vuint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
\r
3586 vuint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
\r
3587 vuint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
\r
3588 vuint16_t TI2IE:1; /* timer 2 expired interrupt enable */
\r
3589 vuint16_t TI1IE:1; /* timer 1 expired interrupt enable */
\r
3590 vuint16_t CYSIE:1; /* cycle start interrupt enable */
\r
3593 CC_EXTENSION typedef union uPIER1 {
\r
3596 vuint16_t EMCIE:1; /* error mode changed interrupt enable */
\r
3597 vuint16_t IPCIE:1; /* illegal protocol command interrupt enable */
\r
3598 vuint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
\r
3599 vuint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */
\r
3600 vuint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
\r
3601 vuint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
\r
3602 vuint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
\r
3603 vuint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
\r
3605 vuint16_t EVTIE:1; /* even cycle table written interrupt enable */
\r
3606 vuint16_t ODTIE:1; /* odd cycle table written interrupt enable */
\r
3610 CC_EXTENSION typedef union uCHIERFR {
\r
3613 vuint16_t FRLBEF:1; /* flame lost channel B error flag */
\r
3614 vuint16_t FRLAEF:1; /* frame lost channel A error flag */
\r
3615 vuint16_t PCMIEF:1; /* command ignored error flag */
\r
3616 vuint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
\r
3617 vuint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
\r
3618 vuint16_t MSBEF:1; /* message buffer search error flag */
\r
3619 vuint16_t MBUEF:1; /* message buffer utilization error flag */
\r
3620 vuint16_t LCKEF:1; /* lock error flag */
\r
3621 vuint16_t DBLEF:1; /* double transmit message buffer lock error flag */
\r
3622 vuint16_t SBCFEF:1; /* system bus communication failure error flag */
\r
3623 vuint16_t FIDEF:1; /* frame ID error flag */
\r
3624 vuint16_t DPLEF:1; /* dynamic payload length error flag */
\r
3625 vuint16_t SPLEF:1; /* static payload length error flag */
\r
3626 vuint16_t NMLEF:1; /* network management length error flag */
\r
3627 vuint16_t NMFEF:1; /* network management frame error flag */
\r
3628 vuint16_t ILSAEF:1; /* illegal access error flag */
\r
3631 CC_EXTENSION typedef union uMBIVEC {
\r
3636 vuint16_t TBIVEC:7; /* transmit buffer interrupt vector */
\r
3638 vuint16_t RBIVEC:7; /* receive buffer interrupt vector */
\r
3642 CC_EXTENSION typedef union uPSR0 {
\r
3645 vuint16_t ERRMODE:2; /* error mode */
\r
3646 vuint16_t SLOTMODE:2; /* slot mode */
\r
3648 vuint16_t PROTSTATE:3; /* protocol state */
\r
3649 vuint16_t SUBSTATE:4; /* protocol sub state */
\r
3651 vuint16_t WAKEUPSTATUS:3; /* wakeup status */
\r
3655 /* protocol states */
\r
3656 /* protocol sub-states */
\r
3657 /* wakeup status */
\r
3658 CC_EXTENSION typedef union uPSR1 {
\r
3661 vuint16_t CSAA:1; /* cold start attempt abort flag */
\r
3662 vuint16_t SCP:1; /* cold start path */
\r
3664 vuint16_t REMCSAT:5; /* remanining coldstart attempts */
\r
3665 vuint16_t CPN:1; /* cold start noise path */
\r
3666 vuint16_t HHR:1; /* host halt request pending */
\r
3667 vuint16_t FRZ:1; /* freeze occured */
\r
3668 vuint16_t APTAC:5; /* allow passive to active counter */
\r
3671 CC_EXTENSION typedef union uPSR2 {
\r
3674 vuint16_t NBVB:1; /* NIT boundary violation on channel B */
\r
3675 vuint16_t NSEB:1; /* NIT syntax error on channel B */
\r
3676 vuint16_t STCB:1; /* symbol window transmit conflict on channel B */
\r
3677 vuint16_t SBVB:1; /* symbol window boundary violation on channel B */
\r
3678 vuint16_t SSEB:1; /* symbol window syntax error on channel B */
\r
3679 vuint16_t MTB:1; /* media access test symbol MTS received on channel B */
\r
3680 vuint16_t NBVA:1; /* NIT boundary violation on channel A */
\r
3681 vuint16_t NSEA:1; /* NIT syntax error on channel A */
\r
3682 vuint16_t STCA:1; /* symbol window transmit conflict on channel A */
\r
3683 vuint16_t SBVA:1; /* symbol window boundary violation on channel A */
\r
3684 vuint16_t SSEA:1; /* symbol window syntax error on channel A */
\r
3685 vuint16_t MTA:1; /* media access test symbol MTS received on channel A */
\r
3686 vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
\r
3689 CC_EXTENSION typedef union uPSR3 {
\r
3693 vuint16_t WUB:1; /* wakeup symbol received on channel B */
\r
3694 vuint16_t ABVB:1; /* aggregated boundary violation on channel B */
\r
3695 vuint16_t AACB:1; /* aggregated additional communication on channel B */
\r
3696 vuint16_t ACEB:1; /* aggregated content error on channel B */
\r
3697 vuint16_t ASEB:1; /* aggregated syntax error on channel B */
\r
3698 vuint16_t AVFB:1; /* aggregated valid frame on channel B */
\r
3700 vuint16_t WUA:1; /* wakeup symbol received on channel A */
\r
3701 vuint16_t ABVA:1; /* aggregated boundary violation on channel A */
\r
3702 vuint16_t AACA:1; /* aggregated additional communication on channel A */
\r
3703 vuint16_t ACEA:1; /* aggregated content error on channel A */
\r
3704 vuint16_t ASEA:1; /* aggregated syntax error on channel A */
\r
3705 vuint16_t AVFA:1; /* aggregated valid frame on channel A */
\r
3708 CC_EXTENSION typedef union uCIFRR {
\r
3712 vuint16_t MIFR:1; /* module interrupt flag */
\r
3713 vuint16_t PRIFR:1; /* protocol interrupt flag */
\r
3714 vuint16_t CHIFR:1; /* CHI interrupt flag */
\r
3715 vuint16_t WUPIFR:1; /* wakeup interrupt flag */
\r
3716 vuint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */
\r
3717 vuint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */
\r
3718 vuint16_t RBIFR:1; /* receive message buffer interrupt flag */
\r
3719 vuint16_t TBIFR:1; /* transmit buffer interrupt flag */
\r
3722 CC_EXTENSION typedef union uSFCNTR {
\r
3725 vuint16_t SFEVB:4; /* sync frames channel B, even cycle */
\r
3726 vuint16_t SFEVA:4; /* sync frames channel A, even cycle */
\r
3727 vuint16_t SFODB:4; /* sync frames channel B, odd cycle */
\r
3728 vuint16_t SFODA:4; /* sync frames channel A, odd cycle */
\r
3732 CC_EXTENSION typedef union uSFTCCSR {
\r
3735 vuint16_t ELKT:1; /* even cycle tables lock and unlock trigger */
\r
3736 vuint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */
\r
3737 vuint16_t CYCNUM:6; /* cycle number */
\r
3738 vuint16_t ELKS:1; /* even cycle tables lock status */
\r
3739 vuint16_t OLKS:1; /* odd cycle tables lock status */
\r
3740 vuint16_t EVAL:1; /* even cycle tables valid */
\r
3741 vuint16_t OVAL:1; /* odd cycle tables valid */
\r
3743 vuint16_t OPT:1; /*one pair trigger */
\r
3744 vuint16_t SDVEN:1; /* sync frame deviation table enable */
\r
3745 vuint16_t SIDEN:1; /* sync frame ID table enable */
\r
3748 CC_EXTENSION typedef union uSFIDRFR {
\r
3752 vuint16_t SYNFRID:10; /* sync frame rejection ID */
\r
3756 CC_EXTENSION typedef union uTICCR {
\r
3760 vuint16_t T2CFG:1; /* timer 2 configuration */
\r
3761 vuint16_t T2REP:1; /* timer 2 repetitive mode */
\r
3763 vuint16_t T2SP:1; /* timer 2 stop */
\r
3764 vuint16_t T2TR:1; /* timer 2 trigger */
\r
3765 vuint16_t T2ST:1; /* timer 2 state */
\r
3767 vuint16_t T1REP:1; /* timer 1 repetitive mode */
\r
3769 vuint16_t T1SP:1; /* timer 1 stop */
\r
3770 vuint16_t T1TR:1; /* timer 1 trigger */
\r
3771 vuint16_t T1ST:1; /* timer 1 state */
\r
3775 CC_EXTENSION typedef union uTI1CYSR {
\r
3779 vuint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */
\r
3781 vuint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */
\r
3786 CC_EXTENSION typedef union uSSSR {
\r
3789 vuint16_t WMD:1; /* write mode */
\r
3791 vuint16_t SEL:2; /* static slot number */
\r
3793 vuint16_t SLOTNUMBER:11; /* selector */
\r
3797 CC_EXTENSION typedef union uSSCCR {
\r
3800 vuint16_t WMD:1; /* write mode */
\r
3802 vuint16_t SEL:2; /* selector */
\r
3804 vuint16_t CNTCFG:2; /* counter configuration */
\r
3805 vuint16_t MCY:1; /* multi cycle selection */
\r
3806 vuint16_t VFR:1; /* valid frame selection */
\r
3807 vuint16_t SYF:1; /* sync frame selection */
\r
3808 vuint16_t NUF:1; /* null frame selection */
\r
3809 vuint16_t SUF:1; /* startup frame selection */
\r
3810 vuint16_t STATUSMASK:4; /* slot status mask */
\r
3813 CC_EXTENSION typedef union uSSR {
\r
3816 vuint16_t VFB:1; /* valid frame on channel B */
\r
3817 vuint16_t SYB:1; /* valid sync frame on channel B */
\r
3818 vuint16_t NFB:1; /* valid null frame on channel B */
\r
3819 vuint16_t SUB:1; /* valid startup frame on channel B */
\r
3820 vuint16_t SEB:1; /* syntax error on channel B */
\r
3821 vuint16_t CEB:1; /* content error on channel B */
\r
3822 vuint16_t BVB:1; /* boundary violation on channel B */
\r
3823 vuint16_t TCB:1; /* tx conflict on channel B */
\r
3824 vuint16_t VFA:1; /* valid frame on channel A */
\r
3825 vuint16_t SYA:1; /* valid sync frame on channel A */
\r
3826 vuint16_t NFA:1; /* valid null frame on channel A */
\r
3827 vuint16_t SUA:1; /* valid startup frame on channel A */
\r
3828 vuint16_t SEA:1; /* syntax error on channel A */
\r
3829 vuint16_t CEA:1; /* content error on channel A */
\r
3830 vuint16_t BVA:1; /* boundary violation on channel A */
\r
3831 vuint16_t TCA:1; /* tx conflict on channel A */
\r
3834 CC_EXTENSION typedef union uMTSCFR {
\r
3837 vuint16_t MTE:1; /* media access test symbol transmission enable */
\r
3839 vuint16_t CYCCNTMSK:6; /* cycle counter mask */
\r
3841 vuint16_t CYCCNTVAL:6; /* cycle counter value */
\r
3844 CC_EXTENSION typedef union uRSBIR {
\r
3847 vuint16_t WMD:1; /* write mode */
\r
3849 vuint16_t SEL:2; /* selector */
\r
3851 vuint16_t RSBIDX:8; /* receive shadow buffer index */
\r
3854 CC_EXTENSION typedef union uRFDSR {
\r
3857 vuint16_t FIFODEPTH:8; /* fifo depth */
\r
3859 vuint16_t ENTRYSIZE:7; /* entry size */
\r
3863 CC_EXTENSION typedef union uRFRFCFR {
\r
3866 vuint16_t WMD:1; /* write mode */
\r
3867 vuint16_t IBD:1; /* interval boundary */
\r
3868 vuint16_t SEL:2; /* filter number */
\r
3870 vuint16_t SID:11; /* slot ID */
\r
3874 CC_EXTENSION typedef union uRFRFCTR {
\r
3878 vuint16_t F3MD:1; /* filter mode */
\r
3879 vuint16_t F2MD:1; /* filter mode */
\r
3880 vuint16_t F1MD:1; /* filter mode */
\r
3881 vuint16_t F0MD:1; /* filter mode */
\r
3883 vuint16_t F3EN:1; /* filter enable */
\r
3884 vuint16_t F2EN:1; /* filter enable */
\r
3885 vuint16_t F1EN:1; /* filter enable */
\r
3886 vuint16_t F0EN:1; /* filter enable */
\r
3889 CC_EXTENSION typedef union uPCR0 {
\r
3892 vuint16_t ACTION_POINT_OFFSET:6;
\r
3893 vuint16_t STATIC_SLOT_LENGTH:10;
\r
3897 CC_EXTENSION typedef union uPCR1 {
\r
3901 vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
\r
3905 CC_EXTENSION typedef union uPCR2 {
\r
3908 vuint16_t MINISLOT_AFTER_ACTION_POINT:6;
\r
3909 vuint16_t NUMBER_OF_STATIC_SLOTS:10;
\r
3913 CC_EXTENSION typedef union uPCR3 {
\r
3916 vuint16_t WAKEUP_SYMBOL_RX_LOW:6;
\r
3917 vuint16_t MINISLOT_ACTION_POINT_OFFSET:5;
\r
3918 vuint16_t COLDSTART_ATTEMPTS:5;
\r
3922 CC_EXTENSION typedef union uPCR4 {
\r
3925 vuint16_t CAS_RX_LOW_MAX:7;
\r
3926 vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
\r
3930 CC_EXTENSION typedef union uPCR5 {
\r
3933 vuint16_t TSS_TRANSMITTER:4;
\r
3934 vuint16_t WAKEUP_SYMBOL_TX_LOW:6;
\r
3935 vuint16_t WAKEUP_SYMBOL_RX_IDLE:6;
\r
3939 CC_EXTENSION typedef union uPCR6 {
\r
3943 vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
\r
3944 vuint16_t MACRO_INITIAL_OFFSET_A:7;
\r
3948 CC_EXTENSION typedef union uPCR7 {
\r
3951 vuint16_t DECODING_CORRECTION_B:9;
\r
3952 vuint16_t MICRO_PER_MACRO_NOM_HALF:7;
\r
3956 CC_EXTENSION typedef union uPCR8 {
\r
3959 vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
\r
3960 vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
\r
3961 vuint16_t WAKEUP_SYMBOL_TX_IDLE:8;
\r
3965 CC_EXTENSION typedef union uPCR9 {
\r
3968 vuint16_t MINISLOT_EXISTS:1;
\r
3969 vuint16_t SYMBOL_WINDOW_EXISTS:1;
\r
3970 vuint16_t OFFSET_CORRECTION_OUT:14;
\r
3974 CC_EXTENSION typedef union uPCR10 {
\r
3977 vuint16_t SINGLE_SLOT_ENABLED:1;
\r
3978 vuint16_t WAKEUP_CHANNEL:1;
\r
3979 vuint16_t MACRO_PER_CYCLE:14;
\r
3983 CC_EXTENSION typedef union uPCR11 {
\r
3986 vuint16_t KEY_SLOT_USED_FOR_STARTUP:1;
\r
3987 vuint16_t KEY_SLOT_USED_FOR_SYNC:1;
\r
3988 vuint16_t OFFSET_CORRECTION_START:14;
\r
3992 CC_EXTENSION typedef union uPCR12 {
\r
3995 vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
\r
3996 vuint16_t KEY_SLOT_HEADER_CRC:11;
\r
4000 CC_EXTENSION typedef union uPCR13 {
\r
4003 vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
\r
4004 vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
\r
4008 CC_EXTENSION typedef union uPCR14 {
\r
4011 vuint16_t RATE_CORRECTION_OUT:11;
\r
4012 vuint16_t LISTEN_TIMEOUT_H:5;
\r
4016 CC_EXTENSION typedef union uPCR15 {
\r
4019 vuint16_t LISTEN_TIMEOUT_L:16;
\r
4023 CC_EXTENSION typedef union uPCR16 {
\r
4026 vuint16_t MACRO_INITIAL_OFFSET_B:7;
\r
4027 vuint16_t NOISE_LISTEN_TIMEOUT_H:9;
\r
4031 CC_EXTENSION typedef union uPCR17 {
\r
4034 vuint16_t NOISE_LISTEN_TIMEOUT_L:16;
\r
4038 CC_EXTENSION typedef union uPCR18 {
\r
4041 vuint16_t WAKEUP_PATTERN:6;
\r
4042 vuint16_t KEY_SLOT_ID:10;
\r
4046 CC_EXTENSION typedef union uPCR19 {
\r
4049 vuint16_t DECODING_CORRECTION_A:9;
\r
4050 vuint16_t PAYLOAD_LENGTH_STATIC:7;
\r
4054 CC_EXTENSION typedef union uPCR20 {
\r
4057 vuint16_t MICRO_INITIAL_OFFSET_B:8;
\r
4058 vuint16_t MICRO_INITIAL_OFFSET_A:8;
\r
4062 CC_EXTENSION typedef union uPCR21 {
\r
4065 vuint16_t EXTERN_RATE_CORRECTION:3;
\r
4066 vuint16_t LATEST_TX:13;
\r
4070 CC_EXTENSION typedef union uPCR22 {
\r
4074 vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
\r
4075 vuint16_t MICRO_PER_CYCLE_H:4;
\r
4079 CC_EXTENSION typedef union uPCR23 {
\r
4082 vuint16_t micro_per_cycle_l:16;
\r
4086 CC_EXTENSION typedef union uPCR24 {
\r
4089 vuint16_t CLUSTER_DRIFT_DAMPING:5;
\r
4090 vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
\r
4091 vuint16_t MICRO_PER_CYCLE_MIN_H:4;
\r
4095 CC_EXTENSION typedef union uPCR25 {
\r
4098 vuint16_t MICRO_PER_CYCLE_MIN_L:16;
\r
4102 CC_EXTENSION typedef union uPCR26 {
\r
4105 vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
\r
4106 vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
\r
4107 vuint16_t MICRO_PER_CYCLE_MAX_H:4;
\r
4111 CC_EXTENSION typedef union uPCR27 {
\r
4114 vuint16_t MICRO_PER_CYCLE_MAX_L:16;
\r
4118 CC_EXTENSION typedef union uPCR28 {
\r
4121 vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
\r
4122 vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
\r
4126 CC_EXTENSION typedef union uPCR29 {
\r
4129 vuint16_t EXTERN_OFFSET_CORRECTION:3;
\r
4130 vuint16_t MINISLOTS_MAX:13;
\r
4134 CC_EXTENSION typedef union uPCR30 {
\r
4138 vuint16_t SYNC_NODE_MAX:4;
\r
4142 CC_EXTENSION typedef struct uMSG_BUFF_CCS {
\r
4147 vuint16_t MCM:1; /* message buffer commit mode */
\r
4148 vuint16_t MBT:1; /* message buffer type */
\r
4149 vuint16_t MTD:1; /* message buffer direction */
\r
4150 vuint16_t CMT:1; /* commit for transmission */
\r
4151 vuint16_t EDT:1; /* enable / disable trigger */
\r
4152 vuint16_t LCKT:1; /* lock request trigger */
\r
4153 vuint16_t MBIE:1; /* message buffer interrupt enable */
\r
4155 vuint16_t DUP:1; /* data updated */
\r
4156 vuint16_t DVAL:1; /* data valid */
\r
4157 vuint16_t EDS:1; /* lock status */
\r
4158 vuint16_t LCKS:1; /* enable / disable status */
\r
4159 vuint16_t MBIF:1; /* message buffer interrupt flag */
\r
4165 vuint16_t MTM:1; /* message buffer transmission mode */
\r
4166 vuint16_t CHNLA:1; /* channel assignement */
\r
4167 vuint16_t CHNLB:1; /* channel assignement */
\r
4168 vuint16_t CCFE:1; /* cycle counter filter enable */
\r
4169 vuint16_t CCFMSK:6; /* cycle counter filter mask */
\r
4170 vuint16_t CCFVAL:6; /* cycle counter filter value */
\r
4177 vuint16_t FID:11; /* frame ID */
\r
4184 vuint16_t MBIDX:8; /* message buffer index */
\r
4188 typedef union uSYSBADHR {
\r
4191 typedef union uSYSBADLR {
\r
4194 typedef union uPDAR {
\r
4197 typedef union uCASERCR {
\r
4200 typedef union uCBSERCR {
\r
4203 typedef union uCYCTR {
\r
4206 typedef union uMTCTR {
\r
4209 typedef union uSLTCTAR {
\r
4212 typedef union uSLTCTBR {
\r
4215 typedef union uRTCORVR {
\r
4218 typedef union uOFCORVR {
\r
4221 typedef union uSFTOR {
\r
4224 typedef union uSFIDAFVR {
\r
4227 typedef union uSFIDAFMR {
\r
4230 typedef union uNMVR {
\r
4233 typedef union uNMVLR {
\r
4236 typedef union uT1MTOR {
\r
4239 typedef union uTI2CR0 {
\r
4242 typedef union uTI2CR1 {
\r
4245 typedef union uSSCR {
\r
4248 typedef union uRFSR {
\r
4251 typedef union uRFSIR {
\r
4254 typedef union uRFARIR {
\r
4257 typedef union uRFBRIR {
\r
4260 typedef union uRFMIDAFVR {
\r
4263 typedef union uRFMIAFMR {
\r
4266 typedef union uRFFIDRFVR {
\r
4269 typedef union uRFFIDRFMR {
\r
4272 typedef union uLDTXSLAR {
\r
4275 typedef union uLDTXSLBR {
\r
4279 typedef struct FR_tag {
\r
4280 volatile MVR_t MVR; /*module version register *//*0 */
\r
4281 volatile MCR_t MCR; /*module configuration register *//*2 */
\r
4282 volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */
\r
4283 volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */
\r
4284 volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */
\r
4285 volatile STBPCR_t STBPCR; /*strobe port control register *//*A */
\r
4286 volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */
\r
4287 volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */
\r
4288 vuint16_t reserved3a[1]; /*10 */
\r
4289 volatile PDAR_t PDAR; /*PE data register *//*12 */
\r
4290 volatile POCR_t POCR; /*Protocol operation control register *//*14 */
\r
4291 volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
\r
4292 volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
\r
4293 volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
\r
4294 volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
\r
4295 volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
\r
4296 volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */
\r
4297 volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */
\r
4298 volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */
\r
4299 volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */
\r
4300 volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */
\r
4301 volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */
\r
4302 volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */
\r
4303 volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */
\r
4304 volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
\r
4305 volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
\r
4306 volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */
\r
4307 volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */
\r
4308 volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */
\r
4309 volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */
\r
4310 volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
\r
4311 vuint16_t reserved3[1]; /*3E */
\r
4312 volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */
\r
4313 volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
\r
4314 volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */
\r
4315 volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */
\r
4316 volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */
\r
4317 volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */
\r
4318 volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */
\r
4319 volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
\r
4320 volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
\r
4321 volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */
\r
4322 volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */
\r
4323 volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */
\r
4324 volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */
\r
4325 volatile SSSR_t SSSR; /*slot status selection register *//*64 */
\r
4326 volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
\r
4327 volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */
\r
4328 volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */
\r
4329 volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */
\r
4330 volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */
\r
4331 volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
\r
4332 volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */
\r
4333 volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
\r
4334 volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
\r
4335 volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */
\r
4336 volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */
\r
4337 volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
\r
4338 volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */
\r
4339 volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
\r
4340 volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
\r
4341 volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */
\r
4342 volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */
\r
4343 volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */
\r
4344 volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */
\r
4345 volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */
\r
4346 volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */
\r
4347 volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */
\r
4348 volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */
\r
4349 volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */
\r
4350 volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */
\r
4351 volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */
\r
4352 volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */
\r
4353 volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */
\r
4354 volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */
\r
4355 volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
\r
4356 volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
\r
4357 volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
\r
4358 volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
\r
4359 volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
\r
4360 volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
\r
4361 volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
\r
4362 volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
\r
4363 volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
\r
4364 volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
\r
4365 volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
\r
4366 volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
\r
4367 volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
\r
4368 volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
\r
4369 volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
\r
4370 volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
\r
4371 volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
\r
4372 volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
\r
4373 volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
\r
4374 volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
\r
4375 volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
\r
4376 vuint16_t reserved2[17];
\r
4377 volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */
\r
4380 CC_EXTENSION typedef union uF_HEADER /* frame header */
\r
4384 vuint16_t HDCRC:11; /* Header CRC */
\r
4386 vuint16_t CYCCNT:6; /* Cycle Count */
\r
4388 vuint16_t PLDLEN:7; /* Payload Length */
\r
4390 vuint16_t PPI:1; /* Payload Preamble Indicator */
\r
4391 vuint16_t NUF:1; /* Null Frame Indicator */
\r
4392 vuint16_t SYF:1; /* Sync Frame Indicator */
\r
4393 vuint16_t SUF:1; /* Startup Frame Indicator */
\r
4394 vuint16_t FID:11; /* Frame ID */
\r
4396 vuint16_t WORDS[3];
\r
4398 CC_EXTENSION typedef union uS_STSTUS /* slot status */
\r
4401 vuint16_t VFB:1; /* Valid Frame on channel B */
\r
4402 vuint16_t SYB:1; /* Sync Frame Indicator channel B */
\r
4403 vuint16_t NFB:1; /* Null Frame Indicator channel B */
\r
4404 vuint16_t SUB:1; /* Startup Frame Indicator channel B */
\r
4405 vuint16_t SEB:1; /* Syntax Error on channel B */
\r
4406 vuint16_t CEB:1; /* Content Error on channel B */
\r
4407 vuint16_t BVB:1; /* Boundary Violation on channel B */
\r
4408 vuint16_t CH:1; /* Channel */
\r
4409 vuint16_t VFA:1; /* Valid Frame on channel A */
\r
4410 vuint16_t SYA:1; /* Sync Frame Indicator channel A */
\r
4411 vuint16_t NFA:1; /* Null Frame Indicator channel A */
\r
4412 vuint16_t SUA:1; /* Startup Frame Indicator channel A */
\r
4413 vuint16_t SEA:1; /* Syntax Error on channel A */
\r
4414 vuint16_t CEA:1; /* Content Error on channel A */
\r
4415 vuint16_t BVA:1; /* Boundary Violation on channel A */
\r
4419 vuint16_t VFB:1; /* Valid Frame on channel B */
\r
4420 vuint16_t SYB:1; /* Sync Frame Indicator channel B */
\r
4421 vuint16_t NFB:1; /* Null Frame Indicator channel B */
\r
4422 vuint16_t SUB:1; /* Startup Frame Indicator channel B */
\r
4423 vuint16_t SEB:1; /* Syntax Error on channel B */
\r
4424 vuint16_t CEB:1; /* Content Error on channel B */
\r
4425 vuint16_t BVB:1; /* Boundary Violation on channel B */
\r
4426 vuint16_t TCB:1; /* Tx Conflict on channel B */
\r
4427 vuint16_t VFA:1; /* Valid Frame on channel A */
\r
4428 vuint16_t SYA:1; /* Sync Frame Indicator channel A */
\r
4429 vuint16_t NFA:1; /* Null Frame Indicator channel A */
\r
4430 vuint16_t SUA:1; /* Startup Frame Indicator channel A */
\r
4431 vuint16_t SEA:1; /* Syntax Error on channel A */
\r
4432 vuint16_t CEA:1; /* Content Error on channel A */
\r
4433 vuint16_t BVA:1; /* Boundary Violation on channel A */
\r
4434 vuint16_t TCA:1; /* Tx Conflict on channel A */
\r
4439 typedef struct uMB_HEADER /* message buffer header */
\r
4441 F_HEADER_t FRAME_HEADER;
\r
4442 vuint16_t DATA_OFFSET;
\r
4443 S_STATUS_t SLOT_STATUS;
\r
4446 /* Define memories */
\r
4448 #define SRAM_START 0x40000000
\r
4449 #define SRAM_SIZE 0x14000
\r
4450 #define SRAM_END 0x40013FFF
\r
4452 #define FLASH_START 0x0
\r
4453 #define FLASH_SIZE 0x200000
\r
4454 #define FLASH_END 0x1FFFFF
\r
4456 /* Define instances of modules */
\r
4457 #define PBRIDGE_A (*( volatile struct PBRIDGE_A_tag *) 0xC3F00000)
\r
4458 #define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000)
\r
4459 #define EBI (*( volatile struct EBI_tag *) 0xC3F84000)
\r
4460 #define FLASH (*( volatile struct FLASH_tag *) 0xC3F88000)
\r
4461 #define SIU (*( volatile struct SIU_tag *) 0xC3F90000)
\r
4463 #define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000)
\r
4464 #define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000)
\r
4465 #define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)
\r
4466 #define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)
\r
4467 #define ETPU_DATA_RAM_END 0xC3FC89FC
\r
4468 #define CODE_RAM (*( uint32_t *) 0xC3FD0000)
\r
4469 #define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)
\r
4471 #define PBRIDGE_B (*( volatile struct PBRIDGE_B_tag *) 0xFFF00000)
\r
4472 #define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000)
\r
4473 #define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000)
\r
4474 #define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000)
\r
4475 #define INTC (*( volatile struct INTC_tag *) 0xFFF48000)
\r
4477 #define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000)
\r
4479 #define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000)
\r
4480 #define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000)
\r
4481 #define DSPI_D (*( volatile struct DSPI_tag *) 0xFFF9C000)
\r
4483 #define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000)
\r
4484 #define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000)
\r
4486 #define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000)
\r
4487 #define CAN_B (*( volatile struct FLEXCAN2_tag *) 0xFFFC4000)
\r
4488 #define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000)
\r
4489 #define CAN_D (*( volatile struct FLEXCAN2_tag *) 0xFFFCC000)
\r
4490 #define CAN_E (*( volatile struct FLEXCAN2_tag *) 0xFFFD0000)
\r
4492 #define FEC (*( volatile struct FEC_tag *) 0xFFF4C000)
\r
4494 #define FR (*( volatile struct FR_tag *) 0xFFFE0000)
\r
4500 #ifdef __cplusplus
\r
4503 #endif /* ifdef _MPC5567_H */
\r
4504 /*********************************************************************
\r
4507 * Freescale Semiconductor, INC. All Rights Reserved.
\r
4508 * You are hereby granted a copyright license to use, modify, and
\r
4509 * distribute the SOFTWARE so long as this entire notice is
\r
4510 * retained without alteration in any modified and/or redistributed
\r
4511 * versions, and that such modified versions are clearly identified
\r
4512 * as such. No licenses are granted by implication, estoppel or
\r
4513 * otherwise under any patents or trademarks of Freescale
\r
4514 * Semiconductor, Inc. This software is provided on an "AS IS"
\r
4515 * basis and without warranty.
\r
4517 * To the maximum extent permitted by applicable law, Freescale
\r
4518 * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
\r
4519 * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
\r
4520 * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
\r
4521 * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
\r
4522 * AND ANY ACCOMPANYING WRITTEN MATERIALS.
\r
4524 * To the maximum extent permitted by applicable law, IN NO EVENT
\r
4525 * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
\r
4526 * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
\r
4527 * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
\r
4528 * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
\r
4530 * Freescale Semiconductor assumes no responsibility for the
\r
4531 * maintenance and support of this software
\r
4533 ********************************************************************/
\r
projects / arc.git / blob