1 /**************************************************************************
\r
2 * FILE NAME: mpc5668.h COPYRIGHT (c) Freescale 2009 *
\r
3 * REVISION: 1.1 All Rights Reserved *
\r
6 * This file contain all of the register and bit field definitions for *
\r
8 **************************************************************************/
\r
9 /*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
\r
11 /**************************************************************************
\r
12 * Example register & bit field write: *
\r
14 * <MODULE>.<REGISTER>.B.<BIT> = 1; *
\r
15 * <MODULE>.<REGISTER>.R = 0x10000000; *
\r
17 **************************************************************************/
\r
22 #include "Compiler.h"
\r
23 #include "typedefs.h"
\r
31 #pragma ANSI_strict off
\r
34 #include "ip_adc_mpc56xx.h"
\r
37 /*************************************************************************/
\r
39 /*************************************************************************/
\r
51 vuint32_t XSTRTEN:1;
\r
60 vuint32_t ADCLKSEL:1;
\r
61 vuint32_t ABORTCHAIN:1;
\r
64 vuint32_t OFFREFRESH:1;
\r
65 vuint32_t OFFCANC:1;
\r
69 } MCR; /* MAIN CONFIGURATION REGISTER */
\r
80 vuint32_t CTUSTART:1;
\r
84 vuint32_t OFFREFRESH:1;
\r
85 vuint32_t OFFCANC:1;
\r
86 vuint32_t ADCSTATUS:3;
\r
88 } MSR; /* MAIN STATUS REGISTER */
\r
90 uint32_t adc_reserved1[2];
\r
96 vuint32_t OFFCANCOVR:1;
\r
97 vuint32_t EOFFSET:1;
\r
104 } ISR; /* INTERRUPT STATUS REGISTER */
\r
109 vuint32_t EOCCH31:1;
\r
110 vuint32_t EOCCH30:1;
\r
111 vuint32_t EOCCH29:1;
\r
112 vuint32_t EOCCH28:1;
\r
113 vuint32_t EOCCH27:1;
\r
114 vuint32_t EOCCH26:1;
\r
115 vuint32_t EOCCH25:1;
\r
116 vuint32_t EOCCH24:1;
\r
117 vuint32_t EOCCH23:1;
\r
118 vuint32_t EOCCH22:1;
\r
119 vuint32_t EOCCH21:1;
\r
120 vuint32_t EOCCH20:1;
\r
121 vuint32_t EOCCH19:1;
\r
122 vuint32_t EOCCH18:1;
\r
123 vuint32_t EOCCH17:1;
\r
124 vuint32_t EOCCH16:1;
\r
125 vuint32_t EOCCH15:1;
\r
126 vuint32_t EOCCH14:1;
\r
127 vuint32_t EOCCH13:1;
\r
128 vuint32_t EOCCH12:1;
\r
129 vuint32_t EOCCH11:1;
\r
130 vuint32_t EOCCH10:1;
\r
131 vuint32_t EOCCH9:1;
\r
132 vuint32_t EOCCH8:1;
\r
133 vuint32_t EOCCH7:1;
\r
134 vuint32_t EOCCH6:1;
\r
135 vuint32_t EOCCH5:1;
\r
136 vuint32_t EOCCH4:1;
\r
137 vuint32_t EOCCH3:1;
\r
138 vuint32_t EOCCH2:1;
\r
139 vuint32_t EOCCH1:1;
\r
140 vuint32_t EOCCH0:1;
\r
142 } CEOCFR0; /* CHANNEL PENDING REGISTER 0 */
\r
147 vuint32_t EOCCH63:1;
\r
148 vuint32_t EOCCH62:1;
\r
149 vuint32_t EOCCH61:1;
\r
150 vuint32_t EOCCH60:1;
\r
151 vuint32_t EOCCH59:1;
\r
152 vuint32_t EOCCH58:1;
\r
153 vuint32_t EOCCH57:1;
\r
154 vuint32_t EOCCH56:1;
\r
155 vuint32_t EOCCH55:1;
\r
156 vuint32_t EOCCH54:1;
\r
157 vuint32_t EOCCH53:1;
\r
158 vuint32_t EOCCH52:1;
\r
159 vuint32_t EOCCH51:1;
\r
160 vuint32_t EOCCH50:1;
\r
161 vuint32_t EOCCH49:1;
\r
162 vuint32_t EOCCH48:1;
\r
163 vuint32_t EOCCH47:1;
\r
164 vuint32_t EOCCH46:1;
\r
165 vuint32_t EOCCH45:1;
\r
166 vuint32_t EOCCH44:1;
\r
167 vuint32_t EOCCH43:1;
\r
168 vuint32_t EOCCH42:1;
\r
169 vuint32_t EOCCH41:1;
\r
170 vuint32_t EOCCH40:1;
\r
171 vuint32_t EOCCH39:1;
\r
172 vuint32_t EOCCH38:1;
\r
173 vuint32_t EOCCH37:1;
\r
174 vuint32_t EOCCH36:1;
\r
175 vuint32_t EOCCH35:1;
\r
176 vuint32_t EOCCH34:1;
\r
177 vuint32_t EOCCH33:1;
\r
178 vuint32_t EOCCH32:1;
\r
180 } CEOCFR1; /* CHANNEL PENDING REGISTER 1 */
\r
185 vuint32_t EOCCH95:1;
\r
186 vuint32_t EOCCH94:1;
\r
187 vuint32_t EOCCH93:1;
\r
188 vuint32_t EOCCH92:1;
\r
189 vuint32_t EOCCH91:1;
\r
190 vuint32_t EOCCH90:1;
\r
191 vuint32_t EOCCH89:1;
\r
192 vuint32_t EOCCH88:1;
\r
193 vuint32_t EOCCH87:1;
\r
194 vuint32_t EOCCH86:1;
\r
195 vuint32_t EOCCH85:1;
\r
196 vuint32_t EOCCH84:1;
\r
197 vuint32_t EOCCH83:1;
\r
198 vuint32_t EOCCH82:1;
\r
199 vuint32_t EOCCH81:1;
\r
200 vuint32_t EOCCH80:1;
\r
201 vuint32_t EOCCH79:1;
\r
202 vuint32_t EOCCH78:1;
\r
203 vuint32_t EOCCH77:1;
\r
204 vuint32_t EOCCH76:1;
\r
205 vuint32_t EOCCH75:1;
\r
206 vuint32_t EOCCH74:1;
\r
207 vuint32_t EOCCH73:1;
\r
208 vuint32_t EOCCH72:1;
\r
209 vuint32_t EOCCH71:1;
\r
210 vuint32_t EOCCH70:1;
\r
211 vuint32_t EOCCH69:1;
\r
212 vuint32_t EOCCH68:1;
\r
213 vuint32_t EOCCH67:1;
\r
214 vuint32_t EOCCH66:1;
\r
215 vuint32_t EOCCH65:1;
\r
216 vuint32_t EOCCH64:1;
\r
218 } CEOCFR2; /* CHANNEL PENDING REGISTER 2 */
\r
224 vuint32_t MSKOFFCANCOVR:1;
\r
225 vuint32_t MSKEOFFSET:1;
\r
226 vuint32_t MSKEOCTU:1;
\r
227 vuint32_t MSKJEOC:1;
\r
228 vuint32_t MSKJECH:1;
\r
229 vuint32_t MSKEOC:1;
\r
230 vuint32_t MSKECH:1;
\r
232 } IMR; /* INTERRUPT MASK REGISTER */
\r
270 } CIMR0; /* CHANNEL INTERRUPT MASK REGISTER 0 */
\r
308 } CIMR1; /* CHANNEL INTERRUPT MASK REGISTER 1 */
\r
346 } CIMR2; /* CHANNEL INTERRUPT MASK REGISTER 2 */
\r
361 } WTISR; /* WATCHDOG INTERRUPT THRESHOLD REGISTER */
\r
367 vuint32_t MSKWDG3H:1;
\r
368 vuint32_t MSKWDG2H:1;
\r
369 vuint32_t MSKWDG1H:1;
\r
370 vuint32_t MSKWDG0H:1;
\r
371 vuint32_t MSKWDG3L:1;
\r
372 vuint32_t MSKWDG2L:1;
\r
373 vuint32_t MSKWDG1L:1;
\r
374 vuint32_t MSKWDG0L:1;
\r
376 } WTIMR; /* WATCHDOG INTERRUPT THRESHOLD MASK REGISTER */
\r
378 uint32_t adc_reserved2[2];
\r
387 } DMAE; /* DMA ENABLE REGISTER */
\r
425 } DMAR0; /* DMA CHANNEL SELECT REGISTER 0 */
\r
463 } DMAR1; /* DMA CHANNEL SELECT REGISTER 1 */
\r
501 } DMAR2; /* DMA CHANNEL SELECT REGISTER 2 */
\r
508 vuint32_t THRINV:1;
\r
513 } TRC[4]; /* THRESHOLD CONTROL REGISTER */
\r
523 } THRHLR[4]; /* THRESHOLD REGISTER */
\r
533 } THRALT[4]; /* ALTERNATE THRESHOLD REGISTER */
\r
539 vuint32_t PREVAL2:2;
\r
540 vuint32_t PREVAL1:2;
\r
541 vuint32_t PREVAL0:2;
\r
542 vuint32_t PRECONV:1;
\r
544 } PSCR; /* PRESAMPLING CONTROL REGISTER */
\r
582 } PSR0; /* PRESAMPLING REGISTER 0 */
\r
620 } PSR1; /* PRESAMPLING REGISTER 1 */
\r
658 } PSR2; /* PRESAMPLING REGISTER 2 */
\r
660 uint32_t adc_reserved3;
\r
666 vuint32_t INPLATCH:1;
\r
668 vuint32_t OFFSHIFT:2;
\r
670 vuint32_t INPCMP:2;
\r
672 vuint32_t INPSAMP:8;
\r
674 } CTR0; /* CONVERSION TIMING REGISTER 0 */
\r
680 vuint32_t INPLATCH:1;
\r
682 vuint32_t INPCMP:2;
\r
684 vuint32_t INPSAMP:8;
\r
686 } CTR1; /* CONVERSION TIMING REGISTER 1 */
\r
692 vuint32_t INPLATCH:1;
\r
694 vuint32_t INPCMP:2;
\r
696 vuint32_t INPSAMP:8;
\r
698 } CTR2; /* CONVERSION TIMING REGISTER 2 */
\r
700 uint32_t adc_reserved4;
\r
738 } NCMR0; /* NORMAL CONVERSION MASK REGISTER 0 */
\r
776 } NCMR1; /* NORMAL CONVERSION MASK REGISTER 1 */
\r
814 } NCMR2; /* NORMAL CONVERSION MASK REGISTER 2 */
\r
816 uint32_t adc_reserved5;
\r
854 } JCMR0; /* INJECTED CONVERSION MASK REGISTER 0 */
\r
892 } JCMR1; /* INJECTED CONVERSION MASK REGISTER 1 */
\r
930 } JCMR2; /* INJECTED CONVERSION MASK REGISTER 2 */
\r
936 vuint32_t OFFSETLOAD:1;
\r
938 vuint32_t OFFSET_WORD:8;
\r
940 } OFFWR; /* OFFSET WORD REGISTER */
\r
948 } DSDR; /* DECODE SIGNALS DELAY REGISTER */
\r
956 } PDEDR; /* DECODE SIGNALS DELAY REGISTER */
\r
958 uint32_t adc_reserved6[9];
\r
964 vuint32_t TEST_CTL:16;
\r
966 } TCTLR; /* TEST CONTROL REGISTER */
\r
968 uint32_t adc_reserved7[3];
\r
976 vuint32_t RESULT:2;
\r
978 vuint32_t CDATA:10;
\r
980 } PRECDATAREG[32]; /* PRESISION DATA REGISTER */
\r
988 vuint32_t RESULT:2;
\r
990 vuint32_t CDATA:10;
\r
992 } INTDATAREG[32]; /* PRESISION DATA REGISTER */
\r
1000 vuint32_t RESULT:2;
\r
1002 vuint32_t CDATA:10;
\r
1004 } EXTDATAREG[32]; /* PRESISION DATA REGISTER */
\r
1006 }; /* end of ADC_tag */
\r
1009 /**************************************************************************/
\r
1010 /* MODULE : AXBS Crossbar Switch (XBAR) */
\r
1011 /**************************************************************************/
\r
1018 vuint32_t MSTR7:3;
\r
1020 vuint32_t MSTR6:3;
\r
1022 vuint32_t MSTR5:3;
\r
1024 vuint32_t MSTR3:3;
\r
1026 vuint32_t MSTR2:3;
\r
1028 vuint32_t MSTR1:3;
\r
1030 vuint32_t MSTR0:1;
\r
1032 } MPR0; /* Master Priority Register 0 */
\r
1034 uint32_t xbar_reserved1[3];
\r
1047 } SGPCR0; /* Master Priority Register 0 */
\r
1049 uint32_t xbar_reserved2[58];
\r
1055 vuint32_t MSTR7:3;
\r
1057 vuint32_t MSTR6:3;
\r
1059 vuint32_t MSTR5:3;
\r
1061 vuint32_t MSTR3:3;
\r
1063 vuint32_t MSTR2:3;
\r
1065 vuint32_t MSTR1:3;
\r
1067 vuint32_t MSTR0:1;
\r
1069 } MPR1; /* Master Priority Register 1 */
\r
1071 uint32_t xbar_reserved3[3];
\r
1084 } SGPCR1; /* Master Priority Register 1 */
\r
1086 uint32_t xbar_reserved4[58];
\r
1092 vuint32_t MSTR7:3;
\r
1094 vuint32_t MSTR6:3;
\r
1096 vuint32_t MSTR5:3;
\r
1098 vuint32_t MSTR3:3;
\r
1100 vuint32_t MSTR2:3;
\r
1102 vuint32_t MSTR1:3;
\r
1104 vuint32_t MSTR0:1;
\r
1106 } MPR2; /* Master Priority Register 2 */
\r
1108 uint32_t xbar_reserved5[3];
\r
1121 } SGPCR2; /* Master Priority Register 2 */
\r
1123 uint32_t xbar_reserved6[58];
\r
1129 vuint32_t MSTR7:3;
\r
1131 vuint32_t MSTR6:3;
\r
1133 vuint32_t MSTR5:3;
\r
1135 vuint32_t MSTR3:3;
\r
1137 vuint32_t MSTR2:3;
\r
1139 vuint32_t MSTR1:3;
\r
1141 vuint32_t MSTR0:1;
\r
1143 } MPR3; /* Master Priority Register 3 */
\r
1145 uint32_t xbar_reserved7[3];
\r
1158 } SGPCR3; /* Master Priority Register 3 */
\r
1160 uint32_t xbar_reserved8[186];
\r
1166 vuint32_t MSTR7:3;
\r
1168 vuint32_t MSTR6:3;
\r
1170 vuint32_t MSTR5:3;
\r
1172 vuint32_t MSTR3:3;
\r
1174 vuint32_t MSTR2:3;
\r
1176 vuint32_t MSTR1:3;
\r
1178 vuint32_t MSTR0:1;
\r
1180 } MPR6; /* Master Priority Register 6 */
\r
1182 uint32_t xbar_reserved9[3];
\r
1195 } SGPCR6; /* Master Priority Register 6 */
\r
1197 uint32_t xbar_reserved10[58];
\r
1203 vuint32_t MSTR7:3;
\r
1205 vuint32_t MSTR6:3;
\r
1207 vuint32_t MSTR5:3;
\r
1209 vuint32_t MSTR3:3;
\r
1211 vuint32_t MSTR2:3;
\r
1213 vuint32_t MSTR1:3;
\r
1215 vuint32_t MSTR0:1;
\r
1217 } MPR7; /* Master Priority Register 7 */
\r
1219 uint32_t xbar_reserved11[3];
\r
1232 } SGPCR7; /* Master Priority Register 7 */
\r
1234 uint32_t xbar_reserved12[506];
\r
1247 } MGPCR7; /* Master General Purpose Register 7 */
\r
1250 /*************************************************************************/
\r
1251 /* MODULE : CRP */
\r
1252 /*************************************************************************/
\r
1258 vuint32_t IRCTRIMEN:1;
\r
1260 vuint32_t PREDIV:3;
\r
1262 vuint32_t EN128KIRC:1;
\r
1263 vuint32_t EN32KOSC:1;
\r
1264 vuint32_t ENLPOSC:1;
\r
1265 vuint32_t EN40MOSC:1;
\r
1267 vuint32_t TRIM128IRC:5;
\r
1269 vuint32_t TRIM16IRC:6;
\r
1271 } CLKSRC; /* CLOCK SOURCE REGISTER */
\r
1273 uint32_t crp_reserved1[3];
\r
1278 vuint32_t CNTEN:1;
\r
1279 vuint32_t RTCIE:1;
\r
1280 vuint32_t FRZEN:1;
\r
1281 vuint32_t ROVREN:1;
\r
1282 vuint32_t RTCVAL:12;
\r
1283 vuint32_t APIEN:1;
\r
1284 vuint32_t APIIE:1;
\r
1285 vuint32_t CLKSEL:2;
\r
1286 vuint32_t DIV512EN:1;
\r
1287 vuint32_t DIV32EN:1;
\r
1288 vuint32_t APIVAL:10;
\r
1290 } RTCC; /* RTC CONTROL REGISTER */
\r
1300 vuint32_t ROVRF:1;
\r
1303 } RTSC; /* RTC STATUS REGISTER */
\r
1308 vuint32_t RTCCNT:32;
\r
1310 } RTCCNT; /* RTC Counter Register */
\r
1312 uint32_t crp_reserved2[9];
\r
1317 vuint32_t PWK31:2;
\r
1318 vuint32_t PWK30:2;
\r
1319 vuint32_t PWK29:2;
\r
1320 vuint32_t PWK28:2;
\r
1321 vuint32_t PWK27:2;
\r
1322 vuint32_t PWK26:2;
\r
1323 vuint32_t PWK25:2;
\r
1324 vuint32_t PWK24:2;
\r
1325 vuint32_t PWK23:2;
\r
1326 vuint32_t PWK22:2;
\r
1327 vuint32_t PWK21:2;
\r
1328 vuint32_t PWK20:2;
\r
1329 vuint32_t PWK19:2;
\r
1330 vuint32_t PWK18:2;
\r
1331 vuint32_t PWK17:2;
\r
1332 vuint32_t PWK16:2;
\r
1334 } PWKENH; /* PIN WAKEUP ENABLE HIGH REGISTER */
\r
1339 vuint32_t PWK15:2;
\r
1340 vuint32_t PWK14:2;
\r
1341 vuint32_t PWK13:2;
\r
1342 vuint32_t PWK12:2;
\r
1343 vuint32_t PWK11:2;
\r
1344 vuint32_t PWK10:2;
\r
1356 } PWKENL; /* PIN WAKEUP ENABLE LOW REGISTER */
\r
1361 vuint32_t PWKSRCIE31:1;
\r
1362 vuint32_t PWKSRCIE30:1;
\r
1363 vuint32_t PWKSRCIE29:1;
\r
1364 vuint32_t PWKSRCIE28:1;
\r
1365 vuint32_t PWKSRCIE27:1;
\r
1366 vuint32_t PWKSRCIE26:1;
\r
1367 vuint32_t PWKSRCIE25:1;
\r
1368 vuint32_t PWKSRCIE24:1;
\r
1369 vuint32_t PWKSRCIE23:1;
\r
1370 vuint32_t PWKSRCIE22:1;
\r
1371 vuint32_t PWKSRCIE21:1;
\r
1372 vuint32_t PWKSRCIE20:1;
\r
1373 vuint32_t PWKSRCIE19:1;
\r
1374 vuint32_t PWKSRCIE18:1;
\r
1375 vuint32_t PWKSRCIE17:1;
\r
1376 vuint32_t PWKSRCIE16:1;
\r
1377 vuint32_t PWKSRCIE15:1;
\r
1378 vuint32_t PWKSRCIE14:1;
\r
1379 vuint32_t PWKSRCIE13:1;
\r
1380 vuint32_t PWKSRCIE12:1;
\r
1381 vuint32_t PWKSRCIE11:1;
\r
1382 vuint32_t PWKSRCIE10:1;
\r
1383 vuint32_t PWKSRCIE9:1;
\r
1384 vuint32_t PWKSRCIE8:1;
\r
1385 vuint32_t PWKSRCIE7:1;
\r
1386 vuint32_t PWKSRCIE6:1;
\r
1387 vuint32_t PWKSRCIE5:1;
\r
1388 vuint32_t PWKSRCIE4:1;
\r
1389 vuint32_t PWKSRCIE3:1;
\r
1390 vuint32_t PWKSRCIE2:1;
\r
1391 vuint32_t PWKSRCIE1:1;
\r
1392 vuint32_t PWKSRCIE0:1;
\r
1394 } PWKSRCIE; /* PIN WAKEUP SOURCE INTERRUPT ENABLE REGISTER */
\r
1399 vuint32_t PWKSRCIE31:1;
\r
1400 vuint32_t PWKSRCIE30:1;
\r
1401 vuint32_t PWKSRCIE29:1;
\r
1402 vuint32_t PWKSRCIE28:1;
\r
1403 vuint32_t PWKSRCIE27:1;
\r
1404 vuint32_t PWKSRCIE26:1;
\r
1405 vuint32_t PWKSRCIE25:1;
\r
1406 vuint32_t PWKSRCIE24:1;
\r
1407 vuint32_t PWKSRCIE23:1;
\r
1408 vuint32_t PWKSRCIE22:1;
\r
1409 vuint32_t PWKSRCIE21:1;
\r
1410 vuint32_t PWKSRCIE20:1;
\r
1411 vuint32_t PWKSRCIE19:1;
\r
1412 vuint32_t PWKSRCIE18:1;
\r
1413 vuint32_t PWKSRCIE17:1;
\r
1414 vuint32_t PWKSRCIE16:1;
\r
1415 vuint32_t PWKSRCIE15:1;
\r
1416 vuint32_t PWKSRCIE14:1;
\r
1417 vuint32_t PWKSRCIE13:1;
\r
1418 vuint32_t PWKSRCIE12:1;
\r
1419 vuint32_t PWKSRCIE11:1;
\r
1420 vuint32_t PWKSRCIE10:1;
\r
1421 vuint32_t PWKSRCIE9:1;
\r
1422 vuint32_t PWKSRCIE8:1;
\r
1423 vuint32_t PWKSRCIE7:1;
\r
1424 vuint32_t PWKSRCIE6:1;
\r
1425 vuint32_t PWKSRCIE5:1;
\r
1426 vuint32_t PWKSRCIE4:1;
\r
1427 vuint32_t PWKSRCIE3:1;
\r
1428 vuint32_t PWKSRCIE2:1;
\r
1429 vuint32_t PWKSRCIE1:1;
\r
1430 vuint32_t PWKSRCIE0:1;
\r
1432 } PWKSRCF; /* PIN WAKEUP SOURCE FLAG REGISTER */
\r
1437 vuint32_t Z6VECB:20;
\r
1439 vuint32_t Z6RST:1;
\r
1442 } Z6VEC; /* Z6 RESET VECTOR REGISTER */
\r
1447 vuint32_t Z0VECB:30;
\r
1448 vuint32_t Z0RST:1;
\r
1451 } Z0VEC; /* Z0 RESET VECTOR REGISTER */
\r
1456 vuint32_t RECPTR:30;
\r
1457 vuint32_t FASTREC:1;
\r
1460 } RECPTR; /* RESET RECOVERY POINTER REGISTER */
\r
1462 uint32_t crp_reserved3;
\r
1467 vuint32_t SLEEPF:1;
\r
1469 vuint32_t RTCOVRWKF:1;
\r
1470 vuint32_t RTCWKF:1;
\r
1471 vuint32_t APIWKF:1;
\r
1472 vuint32_t SLEEP:1;
\r
1474 vuint32_t RAMSEL:3;
\r
1476 vuint32_t WKCLKSEL:1;
\r
1477 vuint32_t RTCOVRWKEN:1;
\r
1478 vuint32_t RTCWKEN:1;
\r
1479 vuint32_t APIWKEN:1;
\r
1481 } PSCR; /* POWER STATUS AND CONTROL REGISTER */
\r
1483 uint32_t crp_reserved4[3];
\r
1488 vuint32_t LVI5LOCK:1;
\r
1489 vuint32_t LVI5RE:1;
\r
1491 vuint32_t LVI5HIE:1;
\r
1492 vuint32_t LVI5NIE:1;
\r
1493 vuint32_t LVI5IE:1;
\r
1498 vuint32_t LVI5HIF:1;
\r
1499 vuint32_t LVI5NF:1;
\r
1500 vuint32_t LVI5F:1;
\r
1505 } SOCSC; /* LVI Status and Control Register */
\r
1507 }; /* end of CRP_tag */
\r
1508 /*************************************************************************/
\r
1509 /* MODULE : CTU */
\r
1510 /*************************************************************************/
\r
1517 vuint32_t TRGIEN:1;
\r
1520 vuint32_t PRESC_CONF:4;
\r
1522 } CSR; /* Control Status Register */
\r
1530 } SVR[7]; /* Start Value Register */
\r
1538 } CVR[4]; /* Current Value Register */
\r
1546 vuint32_t COUNT_GROUP:2;
\r
1548 vuint32_t DELAY_INDEX:3;
\r
1549 vuint32_t CLR_FG:1;
\r
1551 vuint32_t CHANNEL_VALUE:6;
\r
1553 } EVTCFGR[33]; /* Event Configuration Register */
\r
1555 }; /* end of CTU_tag */
\r
1556 /*************************************************************************/
\r
1557 /* MODULE : DMAMUX */
\r
1558 /*************************************************************************/
\r
1559 struct DMAMUX_tag {
\r
1565 vuint8_t SOURCE:6;
\r
1567 } CHCONFIG[32]; /* DMA Channel Configuration Register */
\r
1569 }; /* end of DMAMUX_tag */
\r
1570 /*************************************************************************/
\r
1571 /* MODULE : DSPI */
\r
1572 /*************************************************************************/
\r
1578 vuint32_t CONT_SCKE:1;
\r
1579 vuint32_t DCONF:2;
\r
1582 vuint32_t PCSSE:1;
\r
1585 vuint32_t PCSIS5:1;
\r
1586 vuint32_t PCSIS4:1;
\r
1587 vuint32_t PCSIS3:1;
\r
1588 vuint32_t PCSIS2:1;
\r
1589 vuint32_t PCSIS1:1;
\r
1590 vuint32_t PCSIS0:1;
\r
1593 vuint32_t DIS_TXF:1;
\r
1594 vuint32_t DIS_RXF:1;
\r
1595 vuint32_t CLR_TXF:1;
\r
1596 vuint32_t CLR_RXF:1;
\r
1597 vuint32_t SMPL_PT:2;
\r
1601 } MCR; /* Module Configuration Register */
\r
1603 uint32_t dspi_reserved1;
\r
1608 vuint32_t SPI_TCNT:16;
\r
1620 vuint32_t LSBFE:1;
\r
1621 vuint32_t PCSSCK:2;
\r
1625 vuint32_t CSSCK:4;
\r
1630 } CTAR[8]; /* Clock and Transfer Attributes Registers */
\r
1636 vuint32_t TXRXS:1;
\r
1647 vuint32_t TXCTR:4;
\r
1648 vuint32_t TXNXTPTR:4;
\r
1649 vuint32_t RXCTR:4;
\r
1650 vuint32_t POPNXTPTR:4;
\r
1652 } SR; /* Status Register */
\r
1657 vuint32_t TCF_RE:1;
\r
1659 vuint32_t EOQF_RE:1;
\r
1660 vuint32_t TFUF_RE:1;
\r
1662 vuint32_t TFFF_RE:1;
\r
1663 vuint32_t TFFF_DIRS:1;
\r
1665 vuint32_t RFOF_RE:1;
\r
1667 vuint32_t RFDF_RE:1;
\r
1668 vuint32_t RFDF_DIRS:1;
\r
1671 } RSER; /* DMA/Interrupt Request Select and Enable Register */
\r
1679 vuint32_t CTCNT:1;
\r
1687 vuint32_t TXDATA:16;
\r
1689 } PUSHR; /* PUSH TX FIFO Register */
\r
1695 vuint32_t RXDATA:16;
\r
1697 } POPR; /* POP RX FIFO Register */
\r
1702 vuint32_t TXCMD:16;
\r
1703 vuint32_t TXDATA:16;
\r
1705 } TXFR[4]; /* Transmit FIFO Registers */
\r
1707 vuint32_t DSPI_reserved_txf[12];
\r
1713 vuint32_t RXDATA:16;
\r
1715 } RXFR[4]; /* Transmit FIFO Registers */
\r
1717 vuint32_t DSPI_reserved_rxf[12];
\r
1727 vuint32_t DCONT:1;
\r
1728 vuint32_t DSICTAS:3;
\r
1730 vuint32_t DPCS5:1;
\r
1731 vuint32_t DPCS4:1;
\r
1732 vuint32_t DPCS3:1;
\r
1733 vuint32_t DPCS2:1;
\r
1734 vuint32_t DPCS1:1;
\r
1735 vuint32_t DPCS0:1;
\r
1737 } DSICR; /* DSI Configuration Register */
\r
1742 vuint32_t SER_DATA:32;
\r
1744 } SDR; /* DSI Serialization Data Register */
\r
1749 vuint32_t ASER_DATA:32;
\r
1751 } ASDR; /* DSI Alternate Serialization Data Register */
\r
1756 vuint32_t COMP_DATA:32;
\r
1758 } COMPR; /* DSI Transmit Comparison Register */
\r
1763 vuint32_t DESER_DATA:32;
\r
1765 } DDR; /* DSI deserialization Data Register */
\r
1771 vuint32_t TSBCNT:5;
\r
1773 vuint32_t DPCS1_7:1;
\r
1774 vuint32_t DPCS1_6:1;
\r
1775 vuint32_t DPCS1_5:1;
\r
1776 vuint32_t DPCS1_4:1;
\r
1777 vuint32_t DPCS1_3:1;
\r
1778 vuint32_t DPCS1_2:1;
\r
1779 vuint32_t DPCS1_1:1;
\r
1780 vuint32_t DPCS1_0:1;
\r
1782 } DSICR1; /* DSI Configuration Register 1 */
\r
1784 }; /* end of DSPI_tag */
\r
1785 /*************************************************************************/
\r
1786 /* MODULE : ECSM */
\r
1787 /*************************************************************************/
\r
1790 uint32_t ecsm_reserved1[9];
\r
1795 vuint32_t FXSBE0:1;
\r
1796 vuint32_t FXSBE1:1;
\r
1797 vuint32_t FXSBE2:1;
\r
1798 vuint32_t FXSBE3:1;
\r
1800 vuint32_t FXSBE6:1;
\r
1801 vuint32_t FXSBE7:1;
\r
1804 vuint32_t ACCERR:1;
\r
1807 } FBOMCR; /* FEC Burst Optimisation Master Control Register */
\r
1809 uint8_t ecsm_reserved2[27];
\r
1815 vuint8_t EPR1BR:1;
\r
1816 vuint8_t EPF1BR:1;
\r
1818 vuint8_t EPRNCR:1;
\r
1819 vuint8_t EPFNCR:1;
\r
1821 } ECR; /* ECC Configuration Register */
\r
1823 uint8_t ecsm_reserved3[3];
\r
1835 } ESR; /* ECC Status Register */
\r
1837 uint16_t ecsm_reserved4;
\r
1843 vuint16_t FRC1BI:1;
\r
1844 vuint16_t FR11BI:1;
\r
1846 vuint16_t FRCNCI:1;
\r
1847 vuint16_t FR1NCI:1;
\r
1848 vuint16_t PREI_SEL:1;
\r
1849 vuint16_t ERRBIT:7;
\r
1851 } EEGR; /* ECC Error Generation Register */
\r
1853 uint32_t ecsm_reserved5;
\r
1858 vuint32_t PFEAR:32;
\r
1860 } PFEAR; /* Platform Flash ECC Address Register */
\r
1862 uint16_t ecsm_reserved6;
\r
1870 } PFEMR; /* Platform Flash ECC Address Register */
\r
1877 vuint8_t PROTECTION:4;
\r
1879 } PFEAT; /* Flash ECC Attributes Register */
\r
1884 vuint32_t PFEDRH:32;
\r
1886 } PFEDRH; /* Flash ECC Data High Register */
\r
1891 vuint32_t PFEDRL:32;
\r
1893 } PFEDRL; /* Flash ECC Data Low Register */
\r
1898 vuint32_t PREAR:32;
\r
1900 } PREAR; /* Platform RAM ECC Address Register */
\r
1902 uint16_t ecsm_reserved8;
\r
1910 } PREMR; /* RAM ECC Attributes Register */
\r
1917 vuint8_t PROTECTION:4;
\r
1919 } PREAT; /* Platform RAM ECC Attributes Register */
\r
1924 vuint32_t PREDR:32;
\r
1926 } PREDRH; /* Platform RAM ECC Data Low Register High */
\r
1931 vuint32_t PREDR:32;
\r
1933 } PREDRL; /* Platform RAM ECC Data Low Register Low */
\r
1935 }; /* end of ECSM_tag */
\r
1937 #include "ip_edma.h"
\r
1940 /*************************************************************************/
\r
1941 /* MODULE : eDMA */
\r
1942 /*************************************************************************/
\r
1951 vuint32_t GRP1PRI:1;
\r
1953 vuint32_t GRP0PRI:1;
\r
1963 } CR; /* Control Register */
\r
1973 vuint32_t ERRCHN:6;
\r
1983 } ESR; /* Error Status Register */
\r
1985 int32_t EDMA_reserved1;
\r
1991 vuint32_t ERQ31:1;
\r
1992 vuint32_t ERQ30:1;
\r
1993 vuint32_t ERQ29:1;
\r
1994 vuint32_t ERQ28:1;
\r
1995 vuint32_t ERQ27:1;
\r
1996 vuint32_t ERQ26:1;
\r
1997 vuint32_t ERQ25:1;
\r
1998 vuint32_t ERQ24:1;
\r
1999 vuint32_t ERQ23:1;
\r
2000 vuint32_t ERQ22:1;
\r
2001 vuint32_t ERQ21:1;
\r
2002 vuint32_t ERQ20:1;
\r
2003 vuint32_t ERQ19:1;
\r
2004 vuint32_t ERQ18:1;
\r
2005 vuint32_t ERQ17:1;
\r
2006 vuint32_t ERQ16:1;
\r
2007 vuint32_t ERQ15:1;
\r
2008 vuint32_t ERQ14:1;
\r
2009 vuint32_t ERQ13:1;
\r
2010 vuint32_t ERQ12:1;
\r
2011 vuint32_t ERQ11:1;
\r
2012 vuint32_t ERQ10:1;
\r
2013 vuint32_t ERQ09:1;
\r
2014 vuint32_t ERQ08:1;
\r
2015 vuint32_t ERQ07:1;
\r
2016 vuint32_t ERQ06:1;
\r
2017 vuint32_t ERQ05:1;
\r
2018 vuint32_t ERQ04:1;
\r
2019 vuint32_t ERQ03:1;
\r
2020 vuint32_t ERQ02:1;
\r
2021 vuint32_t ERQ01:1;
\r
2022 vuint32_t ERQ00:1;
\r
2024 } ERQRL; /* DMA Enable Request Register */
\r
2026 int32_t EDMA_reserved2;
\r
2031 vuint32_t EEI31:1;
\r
2032 vuint32_t EEI30:1;
\r
2033 vuint32_t EEI29:1;
\r
2034 vuint32_t EEI28:1;
\r
2035 vuint32_t EEI27:1;
\r
2036 vuint32_t EEI26:1;
\r
2037 vuint32_t EEI25:1;
\r
2038 vuint32_t EEI24:1;
\r
2039 vuint32_t EEI23:1;
\r
2040 vuint32_t EEI22:1;
\r
2041 vuint32_t EEI21:1;
\r
2042 vuint32_t EEI20:1;
\r
2043 vuint32_t EEI19:1;
\r
2044 vuint32_t EEI18:1;
\r
2045 vuint32_t EEI17:1;
\r
2046 vuint32_t EEI16:1;
\r
2047 vuint32_t EEI15:1;
\r
2048 vuint32_t EEI14:1;
\r
2049 vuint32_t EEI13:1;
\r
2050 vuint32_t EEI12:1;
\r
2051 vuint32_t EEI11:1;
\r
2052 vuint32_t EEI10:1;
\r
2053 vuint32_t EEI09:1;
\r
2054 vuint32_t EEI08:1;
\r
2055 vuint32_t EEI07:1;
\r
2056 vuint32_t EEI06:1;
\r
2057 vuint32_t EEI05:1;
\r
2058 vuint32_t EEI04:1;
\r
2059 vuint32_t EEI03:1;
\r
2060 vuint32_t EEI02:1;
\r
2061 vuint32_t EEI01:1;
\r
2062 vuint32_t EEI00:1;
\r
2064 } EEIRL; /* DMA Enable Error Interrupt Register Low */
\r
2072 } SERQR; /* DMA Set Enable Request Register */
\r
2080 } CERQR; /* DMA Clear Enable Request Register */
\r
2088 } SEEIR; /* DMA Set Enable Error Interrupt Register */
\r
2096 } CEEIR; /* DMA Clear Enable Error Interrupt Register */
\r
2104 } CIRQR; /* DMA Clear Interrupt Request Register */
\r
2112 } CER; /* DMA Clear error Register */
\r
2120 } SSBR; /* Set Start Bit Register */
\r
2128 } CDSBR; /* Clear Done Status Bit Register */
\r
2130 int32_t EDMA_reserved3;
\r
2135 vuint32_t INT31:1;
\r
2136 vuint32_t INT30:1;
\r
2137 vuint32_t INT29:1;
\r
2138 vuint32_t INT28:1;
\r
2139 vuint32_t INT27:1;
\r
2140 vuint32_t INT26:1;
\r
2141 vuint32_t INT25:1;
\r
2142 vuint32_t INT24:1;
\r
2143 vuint32_t INT23:1;
\r
2144 vuint32_t INT22:1;
\r
2145 vuint32_t INT21:1;
\r
2146 vuint32_t INT20:1;
\r
2147 vuint32_t INT19:1;
\r
2148 vuint32_t INT18:1;
\r
2149 vuint32_t INT17:1;
\r
2150 vuint32_t INT16:1;
\r
2151 vuint32_t INT15:1;
\r
2152 vuint32_t INT14:1;
\r
2153 vuint32_t INT13:1;
\r
2154 vuint32_t INT12:1;
\r
2155 vuint32_t INT11:1;
\r
2156 vuint32_t INT10:1;
\r
2157 vuint32_t INT09:1;
\r
2158 vuint32_t INT08:1;
\r
2159 vuint32_t INT07:1;
\r
2160 vuint32_t INT06:1;
\r
2161 vuint32_t INT05:1;
\r
2162 vuint32_t INT04:1;
\r
2163 vuint32_t INT03:1;
\r
2164 vuint32_t INT02:1;
\r
2165 vuint32_t INT01:1;
\r
2166 vuint32_t INT00:1;
\r
2168 } IRQRL; /* DMA Interrupt Request Low */
\r
2170 int32_t EDMA_reserved4;
\r
2175 vuint32_t ERR31:1;
\r
2176 vuint32_t ERR30:1;
\r
2177 vuint32_t ERR29:1;
\r
2178 vuint32_t ERR28:1;
\r
2179 vuint32_t ERR27:1;
\r
2180 vuint32_t ERR26:1;
\r
2181 vuint32_t ERR25:1;
\r
2182 vuint32_t ERR24:1;
\r
2183 vuint32_t ERR23:1;
\r
2184 vuint32_t ERR22:1;
\r
2185 vuint32_t ERR21:1;
\r
2186 vuint32_t ERR20:1;
\r
2187 vuint32_t ERR19:1;
\r
2188 vuint32_t ERR18:1;
\r
2189 vuint32_t ERR17:1;
\r
2190 vuint32_t ERR16:1;
\r
2191 vuint32_t ERR15:1;
\r
2192 vuint32_t ERR14:1;
\r
2193 vuint32_t ERR13:1;
\r
2194 vuint32_t ERR12:1;
\r
2195 vuint32_t ERR11:1;
\r
2196 vuint32_t ERR10:1;
\r
2197 vuint32_t ERR09:1;
\r
2198 vuint32_t ERR08:1;
\r
2199 vuint32_t ERR07:1;
\r
2200 vuint32_t ERR06:1;
\r
2201 vuint32_t ERR05:1;
\r
2202 vuint32_t ERR04:1;
\r
2203 vuint32_t ERR03:1;
\r
2204 vuint32_t ERR02:1;
\r
2205 vuint32_t ERR01:1;
\r
2206 vuint32_t ERR00:1;
\r
2208 } ERL; /* DMA Error Low */
\r
2210 uint32_t edma_reserved5;
\r
2215 vuint32_t HRS31:1;
\r
2216 vuint32_t HRS30:1;
\r
2217 vuint32_t HRS29:1;
\r
2218 vuint32_t HRS28:1;
\r
2219 vuint32_t HRS27:1;
\r
2220 vuint32_t HRS26:1;
\r
2221 vuint32_t HRS25:1;
\r
2222 vuint32_t HRS24:1;
\r
2223 vuint32_t HRS23:1;
\r
2224 vuint32_t HRS22:1;
\r
2225 vuint32_t HRS21:1;
\r
2226 vuint32_t HRS20:1;
\r
2227 vuint32_t HRS19:1;
\r
2228 vuint32_t HRS18:1;
\r
2229 vuint32_t HRS17:1;
\r
2230 vuint32_t HRS16:1;
\r
2231 vuint32_t HRS15:1;
\r
2232 vuint32_t HRS14:1;
\r
2233 vuint32_t HRS13:1;
\r
2234 vuint32_t HRS12:1;
\r
2235 vuint32_t HRS11:1;
\r
2236 vuint32_t HRS10:1;
\r
2237 vuint32_t HRS09:1;
\r
2238 vuint32_t HRS08:1;
\r
2239 vuint32_t HRS07:1;
\r
2240 vuint32_t HRS06:1;
\r
2241 vuint32_t HRS05:1;
\r
2242 vuint32_t HRS04:1;
\r
2243 vuint32_t HRS03:1;
\r
2244 vuint32_t HRS02:1;
\r
2245 vuint32_t HRS01:1;
\r
2246 vuint32_t HRS00:1;
\r
2248 } HRSL; /* Hardware request status register Low */
\r
2250 uint32_t edma_reserved6[50];
\r
2257 vuint8_t GRPPRI:2;
\r
2260 } CPR[32]; /* Channel n Priority */
\r
2262 uint32_t edma_reserved7[952];
\r
2264 /****************************************************************************/
\r
2265 /* DMA2 Transfer Control Descriptor */
\r
2266 /****************************************************************************/
\r
2268 struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */
\r
2269 vuint32_t SADDR; /* source address */
\r
2271 vuint16_t SMOD:5; /* source address modulo */
\r
2272 vuint16_t SSIZE:3; /* source transfer size */
\r
2273 vuint16_t DMOD:5; /* destination address modulo */
\r
2274 vuint16_t DSIZE:3; /* destination transfer size */
\r
2275 vint16_t SOFF; /* signed source address offset */
\r
2277 vuint32_t NBYTES; /* inner (
\93minor
\94) byte count */
\r
2279 vint32_t SLAST; /* last destination address adjustment, or
\r
2281 scatter/gather address (if e_sg = 1) */
\r
2282 vuint32_t DADDR; /* destination address */
\r
2284 vuint16_t CITERE_LINK:1;
\r
2285 vuint16_t CITER:15;
\r
2287 vint16_t DOFF; /* signed destination address offset */
\r
2289 vint32_t DLAST_SGA;
\r
2291 vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */
\r
2292 vuint16_t BITER:15;
\r
2294 vuint16_t BWC:2; /* bandwidth control */
\r
2295 vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */
\r
2296 vuint16_t DONE:1; /* channel done */
\r
2297 vuint16_t ACTIVE:1; /* channel active */
\r
2298 vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */
\r
2299 vuint16_t E_SG:1; /* enable scatter/gather descriptor */
\r
2300 vuint16_t D_REQ:1; /* disable ipd_req when done */
\r
2301 vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
\r
2302 vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
\r
2303 vuint16_t START:1; /* explicit channel start */
\r
2304 } TCD[32]; /* transfer_control_descriptor */
\r
2308 // struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 )*/
\r
2310 // struct tcd_alt1_t {
\r
2311 // vuint32_t SADDR; /* source address */
\r
2313 // vuint16_t SMOD:5; /* source address modulo */
\r
2314 // vuint16_t SSIZE:3; /* source transfer size */
\r
2315 // vuint16_t DMOD:5; /* destination address modulo */
\r
2316 // vuint16_t DSIZE:3; /* destination transfer size */
\r
2317 // vint16_t SOFF; /* signed source address offset */
\r
2319 // vuint32_t NBYTES; /* inner (
\93minor
\94) byte count */
\r
2321 // vuint32_t SMLOE:1;
\r
2322 // vuint32_t DMLOE:1;
\r
2323 // vuint32_t MLOFFNBYTES:1;
\r
2324 // vuint32_t NBYTES1:1;
\r
2326 // vint32_t SLAST; /* last destination address adjustment, or
\r
2327 // scatter/gather address (if e_sg = 1) */
\r
2329 // vuint32_t DADDR; /* destination address */
\r
2331 // vuint16_t CITERE_LINK:1;
\r
2332 // vuint16_t CITERLINKCH:6;
\r
2333 // vuint16_t CITER:9;
\r
2335 // vint16_t DOFF; /* signed destination address offset */
\r
2337 // vint32_t DLAST_SGA;
\r
2339 // vuint16_t BITERE_LINK:1; /* beginning (
\93major
\94) iteration count */
\r
2340 // vuint16_t BITERLINKCH:6;
\r
2341 // vuint16_t BITER:9;
\r
2343 // vuint16_t BWC:2; /* bandwidth control */
\r
2344 // vuint16_t MAJORLINKCH:6;/* enable channel-to-channel link */
\r
2345 // vuint16_t DONE:1; /* channel done */
\r
2346 // vuint16_t ACTIVE:1; /* channel active */
\r
2347 // vuint16_t MAJORE_LINK:1;/* enable channel-to-channel link */
\r
2348 // vuint16_t E_SG:1; /* enable scatter/gather descriptor */
\r
2349 // vuint16_t D_REQ:1; /* disable ipd_req when done */
\r
2350 // vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
\r
2351 // vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
\r
2352 // vuint16_t START:1; /* explicit channel start */
\r
2353 // } TCD[32]; /* transfer_control_descriptor */
\r
2358 /*************************************************************************/
\r
2359 /* MODULE : EMIOS */
\r
2360 /*************************************************************************/
\r
2361 struct EMIOS_tag {
\r
2370 vuint32_t GPREN:1;
\r
2375 } MCR; /* Module Configuration Register */
\r
2413 } GFR; /* Global FLAG Register */
\r
2451 } OUDR; /* Output Update Disable Register */
\r
2489 } UCDIS; /* Disable Channel Register */
\r
2491 uint32_t emios_reserved1[4];
\r
2498 vuint32_t A:16; /* Channel A Data Register */
\r
2506 vuint32_t B:16; /* Channel B Data Register */
\r
2511 vuint32_t R; /* Channel Counter Register */
\r
2514 vuint32_t C:16; /* Channel C Data Register */
\r
2523 vuint32_t ODISSL:2;
\r
2524 vuint32_t UCPRE:2;
\r
2525 vuint32_t UCPREN:1;
\r
2532 vuint32_t FORCMA:1;
\r
2533 vuint32_t FORCMB:1;
\r
2536 vuint32_t EDSEL:1;
\r
2537 vuint32_t EDPOL:1;
\r
2540 } CCR; /* Channel Control Register */
\r
2550 vuint32_t UCOUT:1;
\r
2553 } CSR; /* Channel Status Register */
\r
2556 vuint32_t R; /* Alternate Channel A Data Register */
\r
2559 uint32_t emios_channel_reserved[2];
\r
2563 }; /* end of EMIOS_tag */
\r
2564 /*************************************************************************/
\r
2565 /* MODULE : eSCI */
\r
2566 /*************************************************************************/
\r
2573 vuint32_t LOOPS:1;
\r
2590 } CR1; /* Control Register 1 */
\r
2598 vuint16_t IEBERR:1;
\r
2599 vuint16_t RXDMA:1;
\r
2600 vuint16_t TXDMA:1;
\r
2601 vuint16_t BRK13:1;
\r
2602 vuint16_t TXDIR:1;
\r
2603 vuint16_t BESM13:1;
\r
2604 vuint16_t SBSTP:1;
\r
2605 vuint16_t RXPOL:1;
\r
2612 } CR2; /* Control Register 2 */
\r
2621 vuint16_t RD_11:4;
\r
2624 } DR; /* Data Register */
\r
2642 vuint32_t RXRDY:1;
\r
2643 vuint32_t TXRDY:1;
\r
2644 vuint32_t LWAKE:1;
\r
2646 vuint32_t PBERR:1;
\r
2648 vuint32_t CKERR:1;
\r
2654 } SR; /* Status Register */
\r
2679 } LCR; /* LIN Control Register */
\r
2683 } LTR; /* LIN Transmit Register */
\r
2685 vuint8_t eSCI_reserved1[3];
\r
2689 } LRR; /* LIN Recieve Register */
\r
2691 vuint8_t eSCI_reserved2[3];
\r
2695 } LPR; /* LIN CRC Polynom Register */
\r
2707 } CR3; /* Control Register 3 */
\r
2709 vuint8_t eSCI_reserved3[5];
\r
2710 }; /* end of ESCI_tag */
\r
2711 /*************************************************************************/
\r
2712 /* MODULE : FEC */
\r
2713 /*************************************************************************/
\r
2716 uint32_t fec_reserved_start;
\r
2721 vuint32_t HBERR:1;
\r
2730 vuint32_t EBERR:1;
\r
2736 } EIR; /* Interrupt Event Register */
\r
2741 vuint32_t HBERR:1;
\r
2750 vuint32_t EBERR:1;
\r
2756 } EIMR; /* Interrupt Mask Register */
\r
2758 uint32_t fec_reserved_eimr;
\r
2764 vuint32_t R_DES_ACTIVE:1;
\r
2767 } RDAR; /* Receive Descriptor Active Register */
\r
2773 vuint32_t X_DES_ACTIVE:1;
\r
2776 } TDAR; /* Transmit Descriptor Active Register */
\r
2778 uint32_t fec_reserved_tdar[3];
\r
2784 vuint32_t ETHER_EN:1;
\r
2785 vuint32_t RESET:1;
\r
2787 } ECR; /* Ethernet Control Register */
\r
2789 uint32_t fec_reserved_ecr[6];
\r
2799 vuint32_t DATA:16;
\r
2801 } MMFR; /* MII Data Register */
\r
2807 vuint32_t DIS_PREAMBLE:1;
\r
2808 vuint32_t MII_SPEED:6;
\r
2811 } MSCR; /* MII Speed Control Register */
\r
2813 uint32_t fec_reserved_mscr[7];
\r
2818 vuint32_t MIB_DISABLE:1;
\r
2819 vuint32_t MIB_IDLE:1;
\r
2822 } MIBC; /* MIB Control Register */
\r
2824 uint32_t fec_reserved_mibc[7];
\r
2830 vuint32_t MAX_FL:11;
\r
2833 vuint32_t BC_REJ:1;
\r
2835 vuint32_t MII_MODE:1;
\r
2839 } RCR; /* Receive Control Register */
\r
2841 uint32_t fec_reserved_rcr[15];
\r
2847 vuint32_t RFC_PAUSE:1;
\r
2848 vuint32_t TFC_PAUSE:1;
\r
2853 } TCR; /* Transmit Control Register */
\r
2855 uint32_t fec_reserved_tcr[7];
\r
2860 vuint32_t PADDR1:32;
\r
2862 } PALR; /* Physical Address Low Register */
\r
2867 vuint32_t PADDR2:16;
\r
2868 vuint32_t TYPE:16;
\r
2870 } PAUR; /* Physical Address High + Type Register */
\r
2875 vuint32_t OPCODE:16;
\r
2876 vuint32_t PAUSE_DUR:16;
\r
2878 } OPD; /* Opcode/Pause Duration Register */
\r
2880 uint32_t fec_reserved_opd[10];
\r
2885 vuint32_t IADDR1:32;
\r
2887 } IAUR; /* Descriptor Individual Upper Address Register */
\r
2892 vuint32_t IADDR2:32;
\r
2894 } IALR; /* Descriptor Individual Lower Address Register */
\r
2899 vuint32_t GADDR1:32;
\r
2901 } GAUR; /* Descriptor Group Upper Address Register */
\r
2906 vuint32_t GADDR2:32;
\r
2908 } GALR; /* Descriptor Group Lower Address Register */
\r
2910 uint32_t fec_reserved_galr[7];
\r
2916 vuint32_t X_WMRK:2;
\r
2918 } TFWR; /* FIFO Transmit FIFO Watermark Register */
\r
2920 uint32_t fec_reserved_tfwr;
\r
2926 vuint32_t R_BOUND:8;
\r
2929 } FRBR; /* FIFO Receive Bound Register */
\r
2935 vuint32_t R_FSTART:8;
\r
2938 } FRSR; /* FIFO Receive Start Register */
\r
2940 uint32_t fec_reserved_frsr[11];
\r
2945 vuint32_t R_DES_START:30;
\r
2948 } ERDSR; /* Receive Descriptor Ring Start Register */
\r
2953 vuint32_t X_DES_START:30;
\r
2956 } ETDSR; /* Transmit Descriptor Ring Start Register */
\r
2962 vuint32_t R_BUF_SIZE:7;
\r
2965 } EMRBR; /* Receive Buffer Size Register */
\r
2967 uint32_t fec_reserved_emrbr[29];
\r
2971 } RMON_T_DROP; /* Count of frames not counted correctly */
\r
2975 } RMON_T_PACKETS; /* RMON Tx packet count */
\r
2979 } RMON_T_BC_PKT; /* RMON Tx Broadcast Packets */
\r
2983 } RMON_T_MC_PKT; /* RMON Tx Multicast Packets */
\r
2987 } RMON_T_CRC_ALIGN; /* RMON Tx Packets w CRC/Align error */
\r
2991 } RMON_T_UNDERSIZE; /* RMON Tx Packets < 64 bytes, good crc */
\r
2995 } RMON_T_OVERSIZE; /* RMON Tx Packets > MAX_FL bytes, good crc */
\r
2999 } RMON_T_FRAG; /* RMON Tx Packets < 64 bytes, bad crc */
\r
3003 } RMON_T_JAB; /* RMON Tx Packets > MAX_FL bytes, bad crc */
\r
3007 } RMON_T_COL; /* RMON Tx collision count */
\r
3011 } RMON_T_P64; /* RMON Tx 64 byte packets */
\r
3015 } RMON_T_P65TO127; /* RMON Tx 65 to 127 byte packets */
\r
3019 } RMON_T_P128TO255; /* RMON Tx 128 to 255 byte packets */
\r
3023 } RMON_T_P256TO511; /* RMON Tx 256 to 511 byte packets */
\r
3027 } RMON_T_P512TO1023; /* RMON Tx 512 to 1023 byte packets */
\r
3031 } RMON_T_P1024TO2047; /* RMON Tx 1024 to 2047 byte packets */
\r
3035 } RMON_T_P_GTE2048; /* RMON Tx packets w > 2048 bytes */
\r
3039 } RMON_T_OCTETS; /* RMON Tx Octets */
\r
3043 } IEEE_T_DROP; /* Count of frames not counted correctly */
\r
3047 } IEEE_T_FRAME_OK; /* Frames Transmitted OK */
\r
3051 } IEEE_T_1COL; /* Frames Transmitted with Single Collision */
\r
3055 } IEEE_T_MCOL; /* Frames Transmitted with Multiple Collisions */
\r
3059 } IEEE_T_DEF; /* Frames Transmitted after Deferral Delay */
\r
3063 } IEEE_T_LCOL; /* Frames Transmitted with Late Collision */
\r
3067 } IEEE_T_EXCOL; /* Frames Transmitted with Excessive Collisions */
\r
3071 } IEEE_T_MACERR; /* Frames Transmitted with Tx FIFO Underrun */
\r
3075 } IEEE_T_CSERR; /* Frames Transmitted with Carrier Sense Error */
\r
3079 } IEEE_T_SQE; /* Frames Transmitted with SQE Error */
\r
3083 } IEEE_T_FDXFC; /* Flow Control Pause frames transmitted */
\r
3087 } IEEE_T_OCTETS_OK; /* Octet count for Frames Transmitted w/o Error */
\r
3089 uint32_t fec_reserved_rmon_t_octets_ok[2];
\r
3093 } RMON_R_DROP; /* Count of frames not counted correctly */
\r
3097 } RMON_R_PACKETS; /* RMON Rx packet count */
\r
3101 } RMON_R_BC_PKT; /* RMON Rx Broadcast Packets */
\r
3105 } RMON_R_MC_PKT; /* RMON Rx Multicast Packets */
\r
3109 } RMON_R_CRC_ALIGN; /* RMON Rx Packets w CRC/Align error */
\r
3113 } RMON_R_UNDERSIZE; /* RMON Rx Packets < 64 bytes, good crc */
\r
3117 } RMON_R_OVERSIZE; /* RMON Rx Packets > MAX_FL bytes, good crc */
\r
3121 } RMON_R_FRAG; /* RMON Rx Packets < 64 bytes, bad crc */
\r
3125 } RMON_R_JAB; /* RMON Rx Packets > MAX_FL bytes, bad crc */
\r
3127 uint32_t fec_reserved_rmon_r_jab;
\r
3131 } RMON_R_P64; /* RMON Rx 64 byte packets */
\r
3135 } RMON_R_P65TO127; /* RMON Rx 65 to 127 byte packets */
\r
3139 } RMON_R_P128TO255; /* RMON Rx 128 to 255 byte packets */
\r
3143 } RMON_R_P256TO511; /* RMON Rx 256 to 511 byte packets */
\r
3147 } RMON_R_P512TO1023; /* RMON Rx 512 to 1023 byte packets */
\r
3151 } RMON_R_P1024TO2047; /* RMON Rx 1024 to 2047 byte packets */
\r
3155 } RMON_R_P_GTE2048; /* RMON Rx packets w > 2048 bytes */
\r
3159 } RMON_R_OCTETS; /* RMON Rx Octets */
\r
3163 } IEEE_R_DROP; /* Count of frames not counted correctly */
\r
3167 } IEEE_R_FRAME_OK; /* Frames Received OK */
\r
3171 } IEEE_R_CRC; /* Frames Received with CRC Error */
\r
3175 } IEEE_R_ALIGN; /* Frames Received with Alignment Error */
\r
3179 } IEEE_R_MACERR; /* Receive Fifo Overflow count */
\r
3183 } IEEE_R_FDXFC; /* Flow Control Pause frames received */
\r
3187 } IEEE_R_OCTETS_OK; /* Octet count for Frames Rcvd w/o Error */
\r
3189 }; /* end of FEC_tag */
\r
3190 /*************************************************************************/
\r
3191 /* MODULE : FLASH */
\r
3192 /*************************************************************************/
\r
3193 struct FLASH_tag {
\r
3217 } MCR; /* Module Configuration Register */
\r
3224 vuint32_t SLOCK:1;
\r
3226 vuint32_t MLOCK:2;
\r
3228 vuint32_t LLOCK:10;
\r
3230 } LMLR; /* Low/Mid-address space block locking Register */
\r
3237 vuint32_t HBLOCK:6;
\r
3239 } HLR; /* High-address space block locking Register */
\r
3246 vuint32_t SSLOCK:1;
\r
3248 vuint32_t SMLOCK:2;
\r
3250 vuint32_t SLLOCK:10;
\r
3252 } SLMLR; /* Secondary low/mid-address space block locking Register */
\r
3260 vuint32_t LSEL:10;
\r
3262 } LMS; /* Low/Mid-address space block locking Register */
\r
3268 vuint32_t HBSEL:6;
\r
3270 } HBS; /* High-address space block locking Register */
\r
3277 vuint32_t ADDR:18;
\r
3280 } ADR; /* Address Register */
\r
3285 vuint32_t LBCFG:4;
\r
3289 vuint32_t M8PFE:1;
\r
3291 vuint32_t M6PFE:1;
\r
3292 vuint32_t M5PFE:1;
\r
3293 vuint32_t M4PFE:1;
\r
3295 vuint32_t M2PFE:1;
\r
3296 vuint32_t M1PFE:1;
\r
3297 vuint32_t M0PFE:1;
\r
3302 vuint32_t DPFEN:1;
\r
3304 vuint32_t IPFEN:1;
\r
3306 vuint32_t PFLIM:2;
\r
3309 } PFCRP0; /* Platform Flash Configuration Register for Port 0 */
\r
3314 vuint32_t LBCFG:4;
\r
3316 vuint32_t M8PFE:1;
\r
3318 vuint32_t M6PFE:1;
\r
3319 vuint32_t M5PFE:1;
\r
3320 vuint32_t M4PFE:1;
\r
3322 vuint32_t M2PFE:1;
\r
3323 vuint32_t M1PFE:1;
\r
3324 vuint32_t M0PFE:1;
\r
3329 vuint32_t DPFEN:1;
\r
3331 vuint32_t IPFEN:1;
\r
3333 vuint32_t PFLIM:2;
\r
3336 } PFCRP1; /* Platform Flash Configuration Register for Port 1 */
\r
3349 vuint32_t SHSACC:4;
\r
3351 vuint32_t SHDACC:4;
\r
3354 } PFAPR; /* Platform Flash access protection Register */
\r
3360 vuint32_t SACC:31;
\r
3362 } PFSACC; /* PFlash Supervisor Access Control Register */
\r
3368 vuint32_t DACC:31;
\r
3370 } PFDACC; /* PFlash Data Access Control Register */
\r
3372 uint32_t FLASH_reserved1[3];
\r
3389 } UT0; /* User Test Register 0 */
\r
3396 } UT1; /* User Test Register 1 */
\r
3403 } UT2; /* User Test Register 2 */
\r
3408 vuint32_t MISR:32;
\r
3410 } MISR[5]; /* Multiple Input Signature Register */
\r
3412 }; /* end of FLASH_tag */
\r
3414 #include "ip_flexcan.h"
\r
3416 /**************************************************************************/
\r
3417 /* MODULE : FlexRay */
\r
3418 /**************************************************************************/
\r
3420 typedef union uMVR {
\r
3423 vuint16_t CHIVER:8; /* CHI Version Number */
\r
3424 vuint16_t PEVER:8; /* PE Version Number */
\r
3428 typedef union uMCR {
\r
3431 vuint16_t MEN:1; /* module enable */
\r
3433 vuint16_t SCMD:1; /* single channel mode */
\r
3434 vuint16_t CHB:1; /* channel B enable */
\r
3435 vuint16_t CHA:1; /* channel A enable */
\r
3436 vuint16_t SFFE:1; /* synchronization frame filter enable */
\r
3438 vuint16_t CLKSEL:1; /* protocol engine clock source select */
\r
3439 vuint16_t PRESCALE:3; /* protocol engine clock prescaler */
\r
3443 typedef union uSTBSCR {
\r
3446 vuint16_t WMD:1; /* write mode */
\r
3447 vuint16_t STBSSEL:7; /* strobe signal select */
\r
3449 vuint16_t ENB:1; /* strobe signal enable */
\r
3451 vuint16_t STBPSEL:2; /* strobe port select */
\r
3454 typedef union uMBDSR {
\r
3458 vuint16_t MBSEG2DS:7; /* message buffer segment 2 data size */
\r
3460 vuint16_t MBSEG1DS:7; /* message buffer segment 1 data size */
\r
3464 typedef union uMBSSUTR {
\r
3469 vuint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */
\r
3471 vuint16_t LAST_MB_UTIL:6; /* last message buffer utilized */
\r
3475 typedef union uPOCR {
\r
3479 vuint16_t WME:1; /* write mode external correction command */
\r
3481 vuint16_t EOC_AP:2; /* external offset correction application */
\r
3482 vuint16_t ERC_AP:2; /* external rate correction application */
\r
3483 vuint16_t BSY:1; /* command write busy / write mode command */
\r
3485 vuint16_t POCCMD:4; /* protocol command */
\r
3488 /* protocol commands */
\r
3489 typedef union uGIFER {
\r
3492 vuint16_t MIF:1; /* module interrupt flag */
\r
3493 vuint16_t PRIF:1; /* protocol interrupt flag */
\r
3494 vuint16_t CHIF:1; /* CHI interrupt flag */
\r
3495 vuint16_t WKUPIF:1; /* wakeup interrupt flag */
\r
3496 vuint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
\r
3497 vuint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
\r
3498 vuint16_t RBIF:1; /* receive message buffer interrupt flag */
\r
3499 vuint16_t TBIF:1; /* transmit buffer interrupt flag */
\r
3500 vuint16_t MIE:1; /* module interrupt enable */
\r
3501 vuint16_t PRIE:1; /* protocol interrupt enable */
\r
3502 vuint16_t CHIE:1; /* CHI interrupt enable */
\r
3503 vuint16_t WKUPIE:1; /* wakeup interrupt enable */
\r
3504 vuint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
\r
3505 vuint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
\r
3506 vuint16_t RBIE:1; /* receive message buffer interrupt enable */
\r
3507 vuint16_t TBIE:1; /* transmit buffer interrupt enable */
\r
3510 typedef union uPIFR0 {
\r
3513 vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */
\r
3514 vuint16_t INTLIF:1; /* internal protocol error interrupt flag */
\r
3515 vuint16_t ILCFIF:1; /* illegal protocol configuration flag */
\r
3516 vuint16_t CSAIF:1; /* cold start abort interrupt flag */
\r
3517 vuint16_t MRCIF:1; /* missing rate correctio interrupt flag */
\r
3518 vuint16_t MOCIF:1; /* missing offset correctio interrupt flag */
\r
3519 vuint16_t CCLIF:1; /* clock correction limit reached interrupt flag */
\r
3520 vuint16_t MXSIF:1; /* max sync frames detected interrupt flag */
\r
3521 vuint16_t MTXIF:1; /* media access test symbol received flag */
\r
3522 vuint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
\r
3523 vuint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
\r
3524 vuint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
\r
3525 vuint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
\r
3526 vuint16_t TI2IF:1; /* timer 2 expired interrupt flag */
\r
3527 vuint16_t TI1IF:1; /* timer 1 expired interrupt flag */
\r
3528 vuint16_t CYSIF:1; /* cycle start interrupt flag */
\r
3531 typedef union uPIFR1 {
\r
3534 vuint16_t EMCIF:1; /* error mode changed interrupt flag */
\r
3535 vuint16_t IPCIF:1; /* illegal protocol command interrupt flag */
\r
3536 vuint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
\r
3537 vuint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */
\r
3538 vuint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
\r
3539 vuint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
\r
3540 vuint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
\r
3541 vuint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
\r
3543 vuint16_t EVTIF:1; /* even cycle table written interrupt flag */
\r
3544 vuint16_t ODTIF:1; /* odd cycle table written interrupt flag */
\r
3548 typedef union uPIER0 {
\r
3551 vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */
\r
3552 vuint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */
\r
3553 vuint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
\r
3554 vuint16_t CSAIE:1; /* cold start abort interrupt enable */
\r
3555 vuint16_t MRCIE:1; /* missing rate correctio interrupt enable */
\r
3556 vuint16_t MOCIE:1; /* missing offset correctio interrupt enable */
\r
3557 vuint16_t CCLIE:1; /* clock correction limit reached interrupt enable */
\r
3558 vuint16_t MXSIE:1; /* max sync frames detected interrupt enable */
\r
3559 vuint16_t MTXIE:1; /* media access test symbol received interrupt enable */
\r
3560 vuint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
\r
3561 vuint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
\r
3562 vuint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
\r
3563 vuint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
\r
3564 vuint16_t TI2IE:1; /* timer 2 expired interrupt enable */
\r
3565 vuint16_t TI1IE:1; /* timer 1 expired interrupt enable */
\r
3566 vuint16_t CYSIE:1; /* cycle start interrupt enable */
\r
3569 typedef union uPIER1 {
\r
3572 vuint16_t EMCIE:1; /* error mode changed interrupt enable */
\r
3573 vuint16_t IPCIE:1; /* illegal protocol command interrupt enable */
\r
3574 vuint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
\r
3575 vuint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */
\r
3576 vuint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
\r
3577 vuint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
\r
3578 vuint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
\r
3579 vuint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
\r
3581 vuint16_t EVTIE:1; /* even cycle table written interrupt enable */
\r
3582 vuint16_t ODTIE:1; /* odd cycle table written interrupt enable */
\r
3586 typedef union uCHIERFR {
\r
3589 vuint16_t FRLBEF:1; /* flame lost channel B error flag */
\r
3590 vuint16_t FRLAEF:1; /* frame lost channel A error flag */
\r
3591 vuint16_t PCMIEF:1; /* command ignored error flag */
\r
3592 vuint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
\r
3593 vuint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
\r
3594 vuint16_t MSBEF:1; /* message buffer search error flag */
\r
3595 vuint16_t MBUEF:1; /* message buffer utilization error flag */
\r
3596 vuint16_t LCKEF:1; /* lock error flag */
\r
3597 vuint16_t DBLEF:1; /* double transmit message buffer lock error flag */
\r
3598 vuint16_t SBCFEF:1; /* system bus communication failure error flag */
\r
3599 vuint16_t FIDEF:1; /* frame ID error flag */
\r
3600 vuint16_t DPLEF:1; /* dynamic payload length error flag */
\r
3601 vuint16_t SPLEF:1; /* static payload length error flag */
\r
3602 vuint16_t NMLEF:1; /* network management length error flag */
\r
3603 vuint16_t NMFEF:1; /* network management frame error flag */
\r
3604 vuint16_t ILSAEF:1; /* illegal access error flag */
\r
3607 typedef union uMBIVEC {
\r
3612 vuint16_t TBIVEC:6; /* transmit buffer interrupt vector */
\r
3614 vuint16_t RBIVEC:6; /* receive buffer interrupt vector */
\r
3618 typedef union uPSR0 {
\r
3621 vuint16_t ERRMODE:2; /* error mode */
\r
3622 vuint16_t SLOTMODE:2; /* slot mode */
\r
3624 vuint16_t PROTSTATE:3; /* protocol state */
\r
3625 vuint16_t SUBSTATE:4; /* protocol sub state */
\r
3627 vuint16_t WAKEUPSTATUS:3; /* wakeup status */
\r
3631 /* protocol states */
\r
3632 /* protocol sub-states */
\r
3633 /* wakeup status */
\r
3634 typedef union uPSR1 {
\r
3637 vuint16_t CSAA:1; /* cold start attempt abort flag */
\r
3638 vuint16_t SCP:1; /* cold start path */
\r
3640 vuint16_t REMCSAT:5; /* remanining coldstart attempts */
\r
3641 vuint16_t CPN:1; /* cold start noise path */
\r
3642 vuint16_t HHR:1; /* host halt request pending */
\r
3643 vuint16_t FRZ:1; /* freeze occured */
\r
3644 vuint16_t APTAC:5; /* allow passive to active counter */
\r
3647 typedef union uPSR2 {
\r
3650 vuint16_t NBVB:1; /* NIT boundary violation on channel B */
\r
3651 vuint16_t NSEB:1; /* NIT syntax error on channel B */
\r
3652 vuint16_t STCB:1; /* symbol window transmit conflict on channel B */
\r
3653 vuint16_t SBVB:1; /* symbol window boundary violation on channel B */
\r
3654 vuint16_t SSEB:1; /* symbol window syntax error on channel B */
\r
3655 vuint16_t MTB:1; /* media access test symbol MTS received on channel B */
\r
3656 vuint16_t NBVA:1; /* NIT boundary violation on channel A */
\r
3657 vuint16_t NSEA:1; /* NIT syntax error on channel A */
\r
3658 vuint16_t STCA:1; /* symbol window transmit conflict on channel A */
\r
3659 vuint16_t SBVA:1; /* symbol window boundary violation on channel A */
\r
3660 vuint16_t SSEA:1; /* symbol window syntax error on channel A */
\r
3661 vuint16_t MTA:1; /* media access test symbol MTS received on channel A */
\r
3662 vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
\r
3665 typedef union uPSR3 {
\r
3669 vuint16_t WUB:1; /* wakeup symbol received on channel B */
\r
3670 vuint16_t ABVB:1; /* aggregated boundary violation on channel B */
\r
3671 vuint16_t AACB:1; /* aggregated additional communication on channel B */
\r
3672 vuint16_t ACEB:1; /* aggregated content error on channel B */
\r
3673 vuint16_t ASEB:1; /* aggregated syntax error on channel B */
\r
3674 vuint16_t AVFB:1; /* aggregated valid frame on channel B */
\r
3676 vuint16_t WUA:1; /* wakeup symbol received on channel A */
\r
3677 vuint16_t ABVA:1; /* aggregated boundary violation on channel A */
\r
3678 vuint16_t AACA:1; /* aggregated additional communication on channel A */
\r
3679 vuint16_t ACEA:1; /* aggregated content error on channel A */
\r
3680 vuint16_t ASEA:1; /* aggregated syntax error on channel A */
\r
3681 vuint16_t AVFA:1; /* aggregated valid frame on channel A */
\r
3684 typedef union uCIFRR {
\r
3688 vuint16_t MIFR:1; /* module interrupt flag */
\r
3689 vuint16_t PRIFR:1; /* protocol interrupt flag */
\r
3690 vuint16_t CHIFR:1; /* CHI interrupt flag */
\r
3691 vuint16_t WUPIFR:1; /* wakeup interrupt flag */
\r
3692 vuint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */
\r
3693 vuint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */
\r
3694 vuint16_t RBIFR:1; /* receive message buffer interrupt flag */
\r
3695 vuint16_t TBIFR:1; /* transmit buffer interrupt flag */
\r
3698 typedef union uSYMATOR {
\r
3702 vuint16_t TIMEOUT:5; /* system memory time out value */
\r
3706 typedef union uSFCNTR {
\r
3709 vuint16_t SFEVB:4; /* sync frames channel B, even cycle */
\r
3710 vuint16_t SFEVA:4; /* sync frames channel A, even cycle */
\r
3711 vuint16_t SFODB:4; /* sync frames channel B, odd cycle */
\r
3712 vuint16_t SFODA:4; /* sync frames channel A, odd cycle */
\r
3716 typedef union uSFTCCSR {
\r
3719 vuint16_t ELKT:1; /* even cycle tables lock and unlock trigger */
\r
3720 vuint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */
\r
3721 vuint16_t CYCNUM:6; /* cycle number */
\r
3722 vuint16_t ELKS:1; /* even cycle tables lock status */
\r
3723 vuint16_t OLKS:1; /* odd cycle tables lock status */
\r
3724 vuint16_t EVAL:1; /* even cycle tables valid */
\r
3725 vuint16_t OVAL:1; /* odd cycle tables valid */
\r
3727 vuint16_t OPT:1; /*one pair trigger */
\r
3728 vuint16_t SDVEN:1; /* sync frame deviation table enable */
\r
3729 vuint16_t SIDEN:1; /* sync frame ID table enable */
\r
3732 typedef union uSFIDRFR {
\r
3736 vuint16_t SYNFRID:10; /* sync frame rejection ID */
\r
3740 typedef union uTICCR {
\r
3744 vuint16_t T2CFG:1; /* timer 2 configuration */
\r
3745 vuint16_t T2REP:1; /* timer 2 repetitive mode */
\r
3747 vuint16_t T2SP:1; /* timer 2 stop */
\r
3748 vuint16_t T2TR:1; /* timer 2 trigger */
\r
3749 vuint16_t T2ST:1; /* timer 2 state */
\r
3751 vuint16_t T1REP:1; /* timer 1 repetitive mode */
\r
3753 vuint16_t T1SP:1; /* timer 1 stop */
\r
3754 vuint16_t T1TR:1; /* timer 1 trigger */
\r
3755 vuint16_t T1ST:1; /* timer 1 state */
\r
3759 typedef union uTI1CYSR {
\r
3763 vuint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */
\r
3765 vuint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */
\r
3770 typedef union uSSSR {
\r
3773 vuint16_t WMD:1; /* write mode */
\r
3775 vuint16_t SEL:2; /* static slot number */
\r
3777 vuint16_t SLOTNUMBER:11; /* selector */
\r
3781 typedef union uSSCCR {
\r
3784 vuint16_t WMD:1; /* write mode */
\r
3786 vuint16_t SEL:2; /* selector */
\r
3788 vuint16_t CNTCFG:2; /* counter configuration */
\r
3789 vuint16_t MCY:1; /* multi cycle selection */
\r
3790 vuint16_t VFR:1; /* valid frame selection */
\r
3791 vuint16_t SYF:1; /* sync frame selection */
\r
3792 vuint16_t NUF:1; /* null frame selection */
\r
3793 vuint16_t SUF:1; /* startup frame selection */
\r
3794 vuint16_t STATUSMASK:4; /* slot status mask */
\r
3797 typedef union uSSR {
\r
3800 vuint16_t VFB:1; /* valid frame on channel B */
\r
3801 vuint16_t SYB:1; /* valid sync frame on channel B */
\r
3802 vuint16_t NFB:1; /* valid null frame on channel B */
\r
3803 vuint16_t SUB:1; /* valid startup frame on channel B */
\r
3804 vuint16_t SEB:1; /* syntax error on channel B */
\r
3805 vuint16_t CEB:1; /* content error on channel B */
\r
3806 vuint16_t BVB:1; /* boundary violation on channel B */
\r
3807 vuint16_t TCB:1; /* tx conflict on channel B */
\r
3808 vuint16_t VFA:1; /* valid frame on channel A */
\r
3809 vuint16_t SYA:1; /* valid sync frame on channel A */
\r
3810 vuint16_t NFA:1; /* valid null frame on channel A */
\r
3811 vuint16_t SUA:1; /* valid startup frame on channel A */
\r
3812 vuint16_t SEA:1; /* syntax error on channel A */
\r
3813 vuint16_t CEA:1; /* content error on channel A */
\r
3814 vuint16_t BVA:1; /* boundary violation on channel A */
\r
3815 vuint16_t TCA:1; /* tx conflict on channel A */
\r
3818 typedef union uMTSCFR {
\r
3821 vuint16_t MTE:1; /* media access test symbol transmission enable */
\r
3823 vuint16_t CYCCNTMSK:6; /* cycle counter mask */
\r
3825 vuint16_t CYCCNTVAL:6; /* cycle counter value */
\r
3829 typedef union uRSBIR {
\r
3832 vuint16_t WMD:1; /* write mode */
\r
3834 vuint16_t SEL:2; /* selector */
\r
3836 vuint16_t RSBIDX:7; /* receive shadow buffer index */
\r
3840 typedef union uRFDSR {
\r
3843 vuint16_t FIFODEPTH:8; /* fifo depth */
\r
3845 vuint16_t ENTRYSIZE:7; /* entry size */
\r
3849 typedef union uRFRFCFR {
\r
3852 vuint16_t WMD:1; /* write mode */
\r
3853 vuint16_t IBD:1; /* interval boundary */
\r
3854 vuint16_t SEL:2; /* filter number */
\r
3856 vuint16_t SID:11; /* slot ID */
\r
3860 typedef union uRFRFCTR {
\r
3864 vuint16_t F3MD:1; /* filter mode */
\r
3865 vuint16_t F2MD:1; /* filter mode */
\r
3866 vuint16_t F1MD:1; /* filter mode */
\r
3867 vuint16_t F0MD:1; /* filter mode */
\r
3869 vuint16_t F3EN:1; /* filter enable */
\r
3870 vuint16_t F2EN:1; /* filter enable */
\r
3871 vuint16_t F1EN:1; /* filter enable */
\r
3872 vuint16_t F0EN:1; /* filter enable */
\r
3875 typedef union uPCR0 {
\r
3878 vuint16_t ACTION_POINT_OFFSET:6;
\r
3879 vuint16_t STATIC_SLOT_LENGTH:10;
\r
3883 typedef union uPCR1 {
\r
3887 vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
\r
3891 typedef union uPCR2 {
\r
3894 vuint16_t MINISLOT_AFTER_ACTION_POINT:6;
\r
3895 vuint16_t NUMBER_OF_STATIC_SLOTS:10;
\r
3899 typedef union uPCR3 {
\r
3902 vuint16_t WAKEUP_SYMBOL_RX_LOW:6;
\r
3903 vuint16_t MINISLOT_ACTION_POINT_OFFSET:5;
\r
3904 vuint16_t COLDSTART_ATTEMPTS:5;
\r
3908 typedef union uPCR4 {
\r
3911 vuint16_t CAS_RX_LOW_MAX:7;
\r
3912 vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
\r
3916 typedef union uPCR5 {
\r
3919 vuint16_t TSS_TRANSMITTER:4;
\r
3920 vuint16_t WAKEUP_SYMBOL_TX_LOW:6;
\r
3921 vuint16_t WAKEUP_SYMBOL_RX_IDLE:6;
\r
3925 typedef union uPCR6 {
\r
3929 vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
\r
3930 vuint16_t MACRO_INITIAL_OFFSET_A:7;
\r
3934 typedef union uPCR7 {
\r
3937 vuint16_t DECODING_CORRECTION_B:9;
\r
3938 vuint16_t MICRO_PER_MACRO_NOM_HALF:7;
\r
3942 typedef union uPCR8 {
\r
3945 vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
\r
3946 vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
\r
3947 vuint16_t WAKEUP_SYMBOL_TX_IDLE:8;
\r
3951 typedef union uPCR9 {
\r
3954 vuint16_t MINISLOT_EXISTS:1;
\r
3955 vuint16_t SYMBOL_WINDOW_EXISTS:1;
\r
3956 vuint16_t OFFSET_CORRECTION_OUT:14;
\r
3960 typedef union uPCR10 {
\r
3963 vuint16_t SINGLE_SLOT_ENABLED:1;
\r
3964 vuint16_t WAKEUP_CHANNEL:1;
\r
3965 vuint16_t MACRO_PER_CYCLE:14;
\r
3969 typedef union uPCR11 {
\r
3972 vuint16_t KEY_SLOT_USED_FOR_STARTUP:1;
\r
3973 vuint16_t KEY_SLOT_USED_FOR_SYNC:1;
\r
3974 vuint16_t OFFSET_CORRECTION_START:14;
\r
3978 typedef union uPCR12 {
\r
3981 vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
\r
3982 vuint16_t KEY_SLOT_HEADER_CRC:11;
\r
3986 typedef union uPCR13 {
\r
3989 vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
\r
3990 vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
\r
3994 typedef union uPCR14 {
\r
3997 vuint16_t RATE_CORRECTION_OUT:11;
\r
3998 vuint16_t LISTEN_TIMEOUT_H:5;
\r
4002 typedef union uPCR15 {
\r
4005 vuint16_t LISTEN_TIMEOUT_L:16;
\r
4009 typedef union uPCR16 {
\r
4012 vuint16_t MACRO_INITIAL_OFFSET_B:7;
\r
4013 vuint16_t NOISE_LISTEN_TIMEOUT_H:9;
\r
4017 typedef union uPCR17 {
\r
4020 vuint16_t NOISE_LISTEN_TIMEOUT_L:16;
\r
4024 typedef union uPCR18 {
\r
4027 vuint16_t WAKEUP_PATTERN:6;
\r
4028 vuint16_t KEY_SLOT_ID:10;
\r
4032 typedef union uPCR19 {
\r
4035 vuint16_t DECODING_CORRECTION_A:9;
\r
4036 vuint16_t PAYLOAD_LENGTH_STATIC:7;
\r
4040 typedef union uPCR20 {
\r
4043 vuint16_t MICRO_INITIAL_OFFSET_B:8;
\r
4044 vuint16_t MICRO_INITIAL_OFFSET_A:8;
\r
4048 typedef union uPCR21 {
\r
4051 vuint16_t EXTERN_RATE_CORRECTION:3;
\r
4052 vuint16_t LATEST_TX:13;
\r
4056 typedef union uPCR22 {
\r
4060 vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
\r
4061 vuint16_t MICRO_PER_CYCLE_H:4;
\r
4065 typedef union uPCR23 {
\r
4068 vuint16_t micro_per_cycle_l:16;
\r
4072 typedef union uPCR24 {
\r
4075 vuint16_t CLUSTER_DRIFT_DAMPING:5;
\r
4076 vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
\r
4077 vuint16_t MICRO_PER_CYCLE_MIN_H:4;
\r
4081 typedef union uPCR25 {
\r
4084 vuint16_t MICRO_PER_CYCLE_MIN_L:16;
\r
4088 typedef union uPCR26 {
\r
4091 vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
\r
4092 vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
\r
4093 vuint16_t MICRO_PER_CYCLE_MAX_H:4;
\r
4097 typedef union uPCR27 {
\r
4100 vuint16_t MICRO_PER_CYCLE_MAX_L:16;
\r
4104 typedef union uPCR28 {
\r
4107 vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
\r
4108 vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
\r
4112 typedef union uPCR29 {
\r
4115 vuint16_t EXTERN_OFFSET_CORRECTION:3;
\r
4116 vuint16_t MINISLOTS_MAX:13;
\r
4120 typedef union uPCR30 {
\r
4124 vuint16_t SYNC_NODE_MAX:4;
\r
4128 typedef struct uMSG_BUFF_CCS {
\r
4133 vuint16_t MCM:1; /* message buffer commit mode */
\r
4134 vuint16_t MBT:1; /* message buffer type */
\r
4135 vuint16_t MTD:1; /* message buffer direction */
\r
4136 vuint16_t CMT:1; /* commit for transmission */
\r
4137 vuint16_t EDT:1; /* enable / disable trigger */
\r
4138 vuint16_t LCKT:1; /* lock request trigger */
\r
4139 vuint16_t MBIE:1; /* message buffer interrupt enable */
\r
4141 vuint16_t DUP:1; /* data updated */
\r
4142 vuint16_t DVAL:1; /* data valid */
\r
4143 vuint16_t EDS:1; /* lock status */
\r
4144 vuint16_t LCKS:1; /* enable / disable status */
\r
4145 vuint16_t MBIF:1; /* message buffer interrupt flag */
\r
4151 vuint16_t MTM:1; /* message buffer transmission mode */
\r
4152 vuint16_t CHNLA:1; /* channel assignement */
\r
4153 vuint16_t CHNLB:1; /* channel assignement */
\r
4154 vuint16_t CCFE:1; /* cycle counter filter enable */
\r
4155 vuint16_t CCFMSK:6; /* cycle counter filter mask */
\r
4156 vuint16_t CCFVAL:6; /* cycle counter filter value */
\r
4163 vuint16_t FID:11; /* frame ID */
\r
4171 vuint16_t MBIDX:7; /* message buffer index */
\r
4175 typedef union uSYSBADHR {
\r
4178 typedef union uSYSBADLR {
\r
4181 typedef union uPADR {
\r
4184 typedef union uPDAR {
\r
4187 typedef union uCASERCR {
\r
4190 typedef union uCBSERCR {
\r
4193 typedef union uCYCTR {
\r
4196 typedef union uMTCTR {
\r
4199 typedef union uSLTCTAR {
\r
4202 typedef union uSLTCTBR {
\r
4205 typedef union uRTCORVR {
\r
4208 typedef union uOFCORVR {
\r
4211 typedef union uSFTOR {
\r
4214 typedef union uSFIDAFVR {
\r
4217 typedef union uSFIDAFMR {
\r
4220 typedef union uNMVR {
\r
4223 typedef union uNMVLR {
\r
4226 typedef union uT1MTOR {
\r
4229 typedef union uTI2CR0 {
\r
4232 typedef union uTI2CR1 {
\r
4235 typedef union uSSCR {
\r
4238 typedef union uRFSR {
\r
4241 typedef union uRFSIR {
\r
4244 typedef union uRFARIR {
\r
4247 typedef union uRFBRIR {
\r
4250 typedef union uRFMIDAFVR {
\r
4253 typedef union uRFMIAFMR {
\r
4256 typedef union uRFFIDRFVR {
\r
4259 typedef union uRFFIDRFMR {
\r
4262 typedef union uLDTXSLAR {
\r
4265 typedef union uLDTXSLBR {
\r
4269 typedef struct FR_tag {
\r
4270 volatile MVR_t MVR; /*module version register *//*0 */
\r
4271 volatile MCR_t MCR; /*module configuration register *//*2 */
\r
4272 volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */
\r
4273 volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */
\r
4274 volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */
\r
4275 vuint16_t reserved0[1]; /*A */
\r
4276 volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */
\r
4277 volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */
\r
4278 vuint16_t reserved1[1]; /*10 */
\r
4279 vuint16_t reserved2[1]; /*12 */
\r
4280 volatile POCR_t POCR; /*Protocol operation control register *//*14 */
\r
4281 volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
\r
4282 volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
\r
4283 volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
\r
4284 volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
\r
4285 volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
\r
4286 volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */
\r
4287 volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */
\r
4288 volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */
\r
4289 volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */
\r
4290 volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */
\r
4291 volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */
\r
4292 volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */
\r
4293 volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */
\r
4294 volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
\r
4295 volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
\r
4296 volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */
\r
4297 volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */
\r
4298 volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */
\r
4299 volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */
\r
4300 volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
\r
4301 volatile SYMATOR_t SYMATOR; /*system memory acess time-out register *//*3E */
\r
4302 volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */
\r
4303 volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
\r
4304 volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */
\r
4305 volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */
\r
4306 volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */
\r
4307 volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */
\r
4308 volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */
\r
4309 volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
\r
4310 volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
\r
4311 volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */
\r
4312 volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */
\r
4313 volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */
\r
4314 volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */
\r
4315 volatile SSSR_t SSSR; /*slot status selection register *//*64 */
\r
4316 volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
\r
4317 volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */
\r
4318 volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */
\r
4319 volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */
\r
4320 volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */
\r
4321 volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
\r
4322 volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */
\r
4323 volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
\r
4324 volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
\r
4325 volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */
\r
4326 volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */
\r
4327 volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
\r
4328 volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */
\r
4329 volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
\r
4330 volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
\r
4331 volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */
\r
4332 volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */
\r
4333 volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */
\r
4334 volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */
\r
4335 volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */
\r
4336 volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */
\r
4337 volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */
\r
4338 volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */
\r
4339 volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */
\r
4340 volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */
\r
4341 volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */
\r
4342 volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */
\r
4343 volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */
\r
4344 volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */
\r
4345 volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
\r
4346 volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
\r
4347 volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
\r
4348 volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
\r
4349 volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
\r
4350 volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
\r
4351 volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
\r
4352 volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
\r
4353 volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
\r
4354 volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
\r
4355 volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
\r
4356 volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
\r
4357 volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
\r
4358 volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
\r
4359 volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
\r
4360 volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
\r
4361 volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
\r
4362 volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
\r
4363 volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
\r
4364 volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
\r
4365 volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
\r
4366 vuint16_t reserved3[17];
\r
4367 volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */
\r
4370 typedef union uF_HEADER /* frame header */
\r
4374 vuint16_t HDCRC:11; /* Header CRC */
\r
4376 vuint16_t CYCCNT:6; /* Cycle Count */
\r
4378 vuint16_t PLDLEN:7; /* Payload Length */
\r
4380 vuint16_t PPI:1; /* Payload Preamble Indicator */
\r
4381 vuint16_t NUF:1; /* Null Frame Indicator */
\r
4382 vuint16_t SYF:1; /* Sync Frame Indicator */
\r
4383 vuint16_t SUF:1; /* Startup Frame Indicator */
\r
4384 vuint16_t FID:11; /* Frame ID */
\r
4386 vuint16_t WORDS[3];
\r
4388 typedef union uS_STSTUS /* slot status */
\r
4391 vuint16_t VFB:1; /* Valid Frame on channel B */
\r
4392 vuint16_t SYB:1; /* Sync Frame Indicator channel B */
\r
4393 vuint16_t NFB:1; /* Null Frame Indicator channel B */
\r
4394 vuint16_t SUB:1; /* Startup Frame Indicator channel B */
\r
4395 vuint16_t SEB:1; /* Syntax Error on channel B */
\r
4396 vuint16_t CEB:1; /* Content Error on channel B */
\r
4397 vuint16_t BVB:1; /* Boundary Violation on channel B */
\r
4398 vuint16_t CH:1; /* Channel */
\r
4399 vuint16_t VFA:1; /* Valid Frame on channel A */
\r
4400 vuint16_t SYA:1; /* Sync Frame Indicator channel A */
\r
4401 vuint16_t NFA:1; /* Null Frame Indicator channel A */
\r
4402 vuint16_t SUA:1; /* Startup Frame Indicator channel A */
\r
4403 vuint16_t SEA:1; /* Syntax Error on channel A */
\r
4404 vuint16_t CEA:1; /* Content Error on channel A */
\r
4405 vuint16_t BVA:1; /* Boundary Violation on channel A */
\r
4409 vuint16_t VFB:1; /* Valid Frame on channel B */
\r
4410 vuint16_t SYB:1; /* Sync Frame Indicator channel B */
\r
4411 vuint16_t NFB:1; /* Null Frame Indicator channel B */
\r
4412 vuint16_t SUB:1; /* Startup Frame Indicator channel B */
\r
4413 vuint16_t SEB:1; /* Syntax Error on channel B */
\r
4414 vuint16_t CEB:1; /* Content Error on channel B */
\r
4415 vuint16_t BVB:1; /* Boundary Violation on channel B */
\r
4416 vuint16_t TCB:1; /* Tx Conflict on channel B */
\r
4417 vuint16_t VFA:1; /* Valid Frame on channel A */
\r
4418 vuint16_t SYA:1; /* Sync Frame Indicator channel A */
\r
4419 vuint16_t NFA:1; /* Null Frame Indicator channel A */
\r
4420 vuint16_t SUA:1; /* Startup Frame Indicator channel A */
\r
4421 vuint16_t SEA:1; /* Syntax Error on channel A */
\r
4422 vuint16_t CEA:1; /* Content Error on channel A */
\r
4423 vuint16_t BVA:1; /* Boundary Violation on channel A */
\r
4424 vuint16_t TCA:1; /* Tx Conflict on channel A */
\r
4429 typedef struct uMB_HEADER /* message buffer header */
\r
4431 F_HEADER_t FRAME_HEADER;
\r
4432 vuint16_t DATA_OFFSET;
\r
4433 S_STATUS_t SLOT_STATUS;
\r
4435 /**************************************************************************/
\r
4436 /* MODULE : FMPLL */
\r
4437 /**************************************************************************/
\r
4438 struct FMPLL_tag {
\r
4440 uint32_t FMPLL_reserved0;
\r
4442 union { /* Synthesiser Status Register */
\r
4449 vuint32_t PLLSEL:1;
\r
4450 vuint32_t PLLREF:1;
\r
4451 vuint32_t LOCKS:1;
\r
4454 vuint32_t CALDONE:1;
\r
4455 vuint32_t CALPASS:1;
\r
4463 vuint32_t CLKCFG:3;
\r
4465 vuint32_t EPREDIV:4;
\r
4475 vuint32_t LOCEN:1;
\r
4476 vuint32_t LOLRE:1;
\r
4477 vuint32_t LOCRE:1;
\r
4478 vuint32_t LOLIRQ:1;
\r
4479 vuint32_t LOCIRQ:1;
\r
4481 vuint32_t ERATE:2;
\r
4483 vuint32_t EDEPTH:3;
\r
4490 /*************************************************************************/
\r
4491 /* MODULE : i2c */
\r
4492 /*************************************************************************/
\r
4500 } IBAD; /* Module Bus Address Register */
\r
4508 } IBFD; /* Module Bus Frequency Register */
\r
4522 } IBCR; /* Module Bus Control Register */
\r
4536 } IBSR; /* Module Status Register */
\r
4543 } IBDR; /* Module Data Register */
\r
4551 } IBIC; /* Module Interrupt Configuration Register */
\r
4553 }; /* end of i2c_tag */
\r
4554 /*************************************************************************/
\r
4555 /* MODULE : INTC */
\r
4556 /*************************************************************************/
\r
4562 vuint32_t VTES_PRC1:1;
\r
4564 vuint32_t HVEN_PRC1:1;
\r
4566 vuint32_t VTES_PRC0:1;
\r
4568 vuint32_t HVEN_PRC0:1;
\r
4570 } MCR; /* Module Configuration Register */
\r
4572 int32_t INTC_reserved1;
\r
4580 } CPR_PRC0; /* Processor 0 (Z6) Current Priority Register */
\r
4588 } CPR_PRC1; /* Processor 1 (Z0) Current Priority Register */
\r
4593 vuint32_t VTBA_PRC0:21;
\r
4594 vuint32_t INTVEC_PRC0:9;
\r
4597 } IACKR_PRC0; /* Processor 0 (Z6) Interrupt Acknowledge Register */
\r
4602 vuint32_t VTBA_PRC1:21;
\r
4603 vuint32_t INTVEC_PRC1:9;
\r
4606 } IACKR_PRC1; /* Processor 1 (Z0) Interrupt Acknowledge Register */
\r
4613 } EOIR_PRC0; /* Processor 0 End of Interrupt Register */
\r
4620 } EOIR_PRC1; /* Processor 1 End of Interrupt Register */
\r
4629 } SSCIR[8]; /* Software Set/Clear Interruput Register */
\r
4631 uint32_t intc_reserved2[6];
\r
4636 vuint8_t PRC_SEL:2;
\r
4640 } PSR[316]; /* Software Set/Clear Interrupt Register */
\r
4642 }; /* end of INTC_tag */
\r
4643 /*************************************************************************/
\r
4644 /* MODULE : MLB */
\r
4645 /*************************************************************************/
\r
4662 } DCCR; /* Device Control Configuration Register */
\r
4677 } SSCR; /* MLB Blank Register */
\r
4684 } SDCR; /* MLB Status Register */
\r
4698 } SMCR; /* RX Control Channel Address Register */
\r
4700 uint32_t MLB_reserved1[3];
\r
4710 } VCCR; /* Version Control Configuration Register */
\r
4715 vuint32_t SRBA:16;
\r
4716 vuint32_t STBA:16;
\r
4718 } SBCR; /* Sync Base Address Config Register */
\r
4723 vuint32_t ARBA:16;
\r
4724 vuint32_t ATBA:16;
\r
4726 } ABCR; /* Async Base Address Channel Config Register */
\r
4731 vuint32_t CRBA:16;
\r
4732 vuint32_t CTBA:16;
\r
4734 } CBCR; /* Control Base Address Config Register */
\r
4739 vuint32_t IRBA:16;
\r
4740 vuint32_t ITBA:16;
\r
4742 } IBCR; /* Isochronous Base Address Config Register */
\r
4750 } CICR; /* Channel Interrupt Config Register */
\r
4752 uint32_t MLB_reserved2[3];
\r
4762 vuint32_t FSE_FCE:1;
\r
4772 vuint32_t FSCD_IPL:1;
\r
4774 vuint32_t FSPC_IPL:5;
\r
4777 } CECR; /* Channel Entry Config Register */
\r
4786 vuint32_t GIRB_GB:1;
\r
4802 } CSCR; /* Channel Status Config Register */
\r
4810 } CCBCR; /* Channel Current Buffer Config Register */
\r
4818 } CNBCR; /* Channel Next Buffer Config Register */
\r
4822 uint32_t MLB_reserved3[80];
\r
4830 } LCBCR[16]; /* Local Channel Buffer Config Register */
\r
4832 }; /* end of MLB_tag */
\r
4833 /*************************************************************************/
\r
4834 /* MODULE : MPU */
\r
4835 /*************************************************************************/
\r
4840 vuint32_t MPERR:8;
\r
4848 } CESR; /* Module Control/Error Status Register */
\r
4850 uint32_t mpu_reserved1[3];
\r
4855 vuint32_t EADDR:32;
\r
4857 } EAR0; /* Error Address Register */
\r
4862 vuint32_t EACD:16;
\r
4865 vuint32_t EATTR:3;
\r
4868 } EDR0; /* Error Detail Register */
\r
4873 vuint32_t EADDR:32;
\r
4880 vuint32_t EACD:16;
\r
4883 vuint32_t EATTR:3;
\r
4891 vuint32_t EADDR:32;
\r
4898 vuint32_t EACD:16;
\r
4901 vuint32_t EATTR:3;
\r
4909 vuint32_t EADDR:32;
\r
4916 vuint32_t EACD:16;
\r
4919 vuint32_t EATTR:3;
\r
4924 uint32_t mpu_reserved2[244];
\r
4930 vuint32_t SRTADDR:27;
\r
4933 } WORD0; /* Region Descriptor n Word 0 */
\r
4938 vuint32_t ENDADDR:27;
\r
4941 } WORD1; /* Region Descriptor n Word 1 */
\r
4964 } WORD2; /* Region Descriptor n Word 2 */
\r
4970 vuint32_t PIDMASK:8;
\r
4974 } WORD3; /* Region Descriptor n Word 3 */
\r
4978 uint32_t mpu_reserved3[192];
\r
5001 } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */
\r
5003 /**************************************************************************/
\r
5004 /* MODULE : pit */
\r
5005 /**************************************************************************/
\r
5017 uint32_t pit_reserved1[63];
\r
5267 /**************************************************************************/
\r
5268 /* MODULE : sem4 */
\r
5269 /**************************************************************************/
\r
5270 struct SEMA4_tag {
\r
5277 } GATE[16]; /* Gate n Register */
\r
5279 uint32_t sema4_reserved1[12]; /* {0x40-0x10}/4 = 0x0C */
\r
5294 vuint16_t INE10:1;
\r
5295 vuint16_t INE11:1;
\r
5296 vuint16_t INE12:1;
\r
5297 vuint16_t INE13:1;
\r
5298 vuint16_t INE14:1;
\r
5299 vuint16_t INE15:1;
\r
5303 uint16_t sema4_reserved2[3]; /* {0x48-0x42}/2 = 0x03 */
\r
5318 vuint16_t INE10:1;
\r
5319 vuint16_t INE11:1;
\r
5320 vuint16_t INE12:1;
\r
5321 vuint16_t INE13:1;
\r
5322 vuint16_t INE14:1;
\r
5323 vuint16_t INE15:1;
\r
5327 uint16_t sema4_reserved3[27]; /* {0x80-0x4A}/2 = 0x1B */
\r
5351 uint16_t sema4_reserved4[3]; /* {0x88-0x82}/2 = 0x03 */
\r
5375 uint16_t sema4_reserved5[59]; /* {0x100-0x8A}/2 = 0x3B */
\r
5381 vuint16_t RSTGSM:2;
\r
5383 vuint16_t RSTGMS:3;
\r
5384 vuint16_t RSTGTN:8;
\r
5388 uint16_t sema4_reserved6;
\r
5394 vuint16_t RSTNSM:2;
\r
5396 vuint16_t RSTNMS:3;
\r
5397 vuint16_t RSTNTN:8;
\r
5401 /*************************************************************************/
\r
5402 /* MODULE : SIU */
\r
5403 /*************************************************************************/
\r
5406 int32_t SIU_reserved0;
\r
5411 vuint32_t PARTNUM:16;
\r
5415 vuint32_t MASKNUM_MAJOR:4;
\r
5416 vuint32_t MASKNUM_MINOR:4;
\r
5418 } MIDR; /* MCU ID Register */
\r
5420 int32_t SIU_reserved1;
\r
5434 vuint32_t BOOTCFG:1;
\r
5437 } RSR; /* Reset Status Register */
\r
5450 } SRCR; /* System Reset Control Register */
\r
5458 vuint32_t EIF15:1;
\r
5459 vuint32_t EIF14:1;
\r
5460 vuint32_t EIF13:1;
\r
5461 vuint32_t EIF12:1;
\r
5462 vuint32_t EIF11:1;
\r
5463 vuint32_t EIF10:1;
\r
5475 } EISR; /* External Interrupt Status Register */
\r
5481 vuint32_t EIRE15:1;
\r
5482 vuint32_t EIRE14:1;
\r
5483 vuint32_t EIRE13:1;
\r
5484 vuint32_t EIRE12:1;
\r
5485 vuint32_t EIRE11:1;
\r
5486 vuint32_t EIRE10:1;
\r
5487 vuint32_t EIRE9:1;
\r
5488 vuint32_t EIRE8:1;
\r
5489 vuint32_t EIRE7:1;
\r
5490 vuint32_t EIRE6:1;
\r
5491 vuint32_t EIRE5:1;
\r
5492 vuint32_t EIRE4:1;
\r
5493 vuint32_t EIRE3:1;
\r
5494 vuint32_t EIRE2:1;
\r
5495 vuint32_t EIRE1:1;
\r
5496 vuint32_t EIRE0:1;
\r
5498 } DIRER; /* DMA/Interrupt Request Enable Register */
\r
5504 vuint32_t DIRS1:1;
\r
5505 vuint32_t DIRS0:1;
\r
5507 } DIRSR; /* DMA/Interrupt Select Register */
\r
5513 vuint32_t OVF15:1;
\r
5514 vuint32_t OVF14:1;
\r
5515 vuint32_t OVF13:1;
\r
5516 vuint32_t OVF12:1;
\r
5517 vuint32_t OVF11:1;
\r
5518 vuint32_t OVF10:1;
\r
5530 } OSR; /* Overrun Status Register */
\r
5536 vuint32_t ORE15:1;
\r
5537 vuint32_t ORE14:1;
\r
5538 vuint32_t ORE13:1;
\r
5539 vuint32_t ORE12:1;
\r
5540 vuint32_t ORE11:1;
\r
5541 vuint32_t ORE10:1;
\r
5553 } ORER; /* Overrun Request Enable Register */
\r
5558 vuint32_t NREE0:1;
\r
5559 vuint32_t NREE1:1;
\r
5561 vuint32_t IREE15:1;
\r
5562 vuint32_t IREE14:1;
\r
5563 vuint32_t IREE13:1;
\r
5564 vuint32_t IREE12:1;
\r
5565 vuint32_t IREE11:1;
\r
5566 vuint32_t IREE10:1;
\r
5567 vuint32_t IREE9:1;
\r
5568 vuint32_t IREE8:1;
\r
5569 vuint32_t IREE7:1;
\r
5570 vuint32_t IREE6:1;
\r
5571 vuint32_t IREE5:1;
\r
5572 vuint32_t IREE4:1;
\r
5573 vuint32_t IREE3:1;
\r
5574 vuint32_t IREE2:1;
\r
5575 vuint32_t IREE1:1;
\r
5576 vuint32_t IREE0:1;
\r
5578 } IREER; /* External IRQ Rising-Edge Event Enable Register */
\r
5583 vuint32_t NFEE0:1;
\r
5584 vuint32_t NFEE1:1;
\r
5586 vuint32_t IFEE15:1;
\r
5587 vuint32_t IFEE14:1;
\r
5588 vuint32_t IFEE13:1;
\r
5589 vuint32_t IFEE12:1;
\r
5590 vuint32_t IFEE11:1;
\r
5591 vuint32_t IFEE10:1;
\r
5592 vuint32_t IFEE9:1;
\r
5593 vuint32_t IFEE8:1;
\r
5594 vuint32_t IFEE7:1;
\r
5595 vuint32_t IFEE6:1;
\r
5596 vuint32_t IFEE5:1;
\r
5597 vuint32_t IFEE4:1;
\r
5598 vuint32_t IFEE3:1;
\r
5599 vuint32_t IFEE2:1;
\r
5600 vuint32_t IFEE1:1;
\r
5601 vuint32_t IFEE0:1;
\r
5603 } IFEER; /* External IRQ Falling-Edge Event Enable Register */
\r
5611 } IDFR; /* External IRQ Digital Filter Register */
\r
5616 vuint32_t FNMI0:1;
\r
5617 vuint32_t FNMI1:1;
\r
5636 } IFIR; /* External IRQ Filtered Input Register */
\r
5638 int32_t SIU_reserved2[2];
\r
5654 } PCR[155]; /* Pad Configuration Registers */
\r
5656 int32_t SIU_reserved3[290];
\r
5664 } GPDO[155]; /* GPIO Pin Data Output Registers */
\r
5666 int8_t SIU_reserved4[357];
\r
5674 } GPDI[155]; /* GPIO Pin Data Input Registers */
\r
5676 int32_t SIU_reserved5[26];
\r
5681 vuint32_t ESEL15:2;
\r
5682 vuint32_t ESEL14:2;
\r
5683 vuint32_t ESEL13:2;
\r
5684 vuint32_t ESEL12:2;
\r
5685 vuint32_t ESEL11:2;
\r
5686 vuint32_t ESEL10:2;
\r
5687 vuint32_t ESEL9:2;
\r
5688 vuint32_t ESEL8:2;
\r
5689 vuint32_t ESEL7:2;
\r
5690 vuint32_t ESEL6:2;
\r
5691 vuint32_t ESEL5:2;
\r
5692 vuint32_t ESEL4:2;
\r
5693 vuint32_t ESEL3:2;
\r
5694 vuint32_t ESEL2:2;
\r
5695 vuint32_t ESEL1:2;
\r
5696 vuint32_t ESEL0:2;
\r
5698 } ISEL1; /* IMUX Register */
\r
5703 vuint32_t ESEL15:2;
\r
5704 vuint32_t ESEL14:2;
\r
5705 vuint32_t ESEL13:2;
\r
5706 vuint32_t ESEL12:2;
\r
5707 vuint32_t ESEL11:2;
\r
5708 vuint32_t ESEL10:2;
\r
5709 vuint32_t ESEL9:2;
\r
5710 vuint32_t ESEL8:2;
\r
5711 vuint32_t ESEL7:2;
\r
5712 vuint32_t ESEL6:2;
\r
5713 vuint32_t ESEL5:2;
\r
5714 vuint32_t ESEL4:2;
\r
5715 vuint32_t ESEL3:2;
\r
5716 vuint32_t ESEL2:2;
\r
5717 vuint32_t ESEL1:2;
\r
5718 vuint32_t ESEL0:2;
\r
5720 } ISEL2; /* IMUX Register */
\r
5722 int32_t SIU_reserved6;
\r
5728 vuint32_t TSEL1:7;
\r
5730 vuint32_t TSEL0:7;
\r
5732 } ISEL4; /* IMUX Register */
\r
5734 int32_t SIU_reserved7[27];
\r
5740 vuint32_t MATCH:1;
\r
5741 vuint32_t DISNEX:1;
\r
5743 vuint32_t TESTLOCK:1;
\r
5746 } CCR; /* Chip Configuration Register Register */
\r
5756 } ECCR; /* External Clock Configuration Register Register */
\r
5760 } GPR0; /* General Purpose Register 0 */
\r
5764 } GPR1; /* General Purpose Register 1 */
\r
5768 } GPR2; /* General Purpose Register 2 */
\r
5772 } GPR3; /* General Purpose Register 3 */
\r
5774 int32_t SIU_reserved8[2];
\r
5779 vuint32_t SYSCLKSEL:2;
\r
5780 vuint32_t SYSCLKDIV:3;
\r
5782 vuint32_t LPCLKDIV3:2;
\r
5783 vuint32_t LPCLKDIV2:2;
\r
5784 vuint32_t LPCLKDIV1:2;
\r
5785 vuint32_t LPCLKDIV0:2;
\r
5787 } SYSCLK; /* System CLock Register */
\r
5797 vuint32_t HLT10:1;
\r
5798 vuint32_t HLT11:1;
\r
5799 vuint32_t HLT12:1;
\r
5800 vuint32_t HLT13:1;
\r
5801 vuint32_t HLT14:1;
\r
5802 vuint32_t HLT15:1;
\r
5803 vuint32_t HLT16:1;
\r
5804 vuint32_t HLT17:1;
\r
5805 vuint32_t HLT18:1;
\r
5806 vuint32_t HLT19:1;
\r
5807 vuint32_t HLT20:1;
\r
5808 vuint32_t HLT21:1;
\r
5809 vuint32_t HLT22:1;
\r
5810 vuint32_t HLT23:1;
\r
5812 vuint32_t HLT26:1;
\r
5813 vuint32_t HLT27:1;
\r
5814 vuint32_t HLT28:1;
\r
5815 vuint32_t HLT29:1;
\r
5817 vuint32_t HLT31:1;
\r
5819 } HLT0; /* Halt Register 0 */
\r
5828 vuint32_t HLT20:1;
\r
5829 vuint32_t HLT21:1;
\r
5830 vuint32_t HLT22:1;
\r
5831 vuint32_t HLT23:1;
\r
5833 vuint32_t HLT26:1;
\r
5834 vuint32_t HLT27:1;
\r
5835 vuint32_t HLT28:1;
\r
5836 vuint32_t HLT29:1;
\r
5839 } HLT1; /* Halt Register 1 */
\r
5845 vuint32_t HLTACK6:1;
\r
5846 vuint32_t HLTACK7:1;
\r
5848 vuint32_t HLTACK9:1;
\r
5849 vuint32_t HLTACK10:1;
\r
5850 vuint32_t HLTACK11:1;
\r
5851 vuint32_t HLTACK12:1;
\r
5852 vuint32_t HLTACK13:1;
\r
5853 vuint32_t HLTACK14:1;
\r
5854 vuint32_t HLTACK15:1;
\r
5855 vuint32_t HLTACK16:1;
\r
5856 vuint32_t HLTACK17:1;
\r
5857 vuint32_t HLTACK18:1;
\r
5858 vuint32_t HLTACK19:1;
\r
5859 vuint32_t HLTACK20:1;
\r
5860 vuint32_t HLTACK21:1;
\r
5861 vuint32_t HLTACK22:1;
\r
5862 vuint32_t HLTACK23:1;
\r
5864 vuint32_t HLTACK26:1;
\r
5865 vuint32_t HLTACK27:1;
\r
5866 vuint32_t HLTACK28:1;
\r
5867 vuint32_t HLTACK29:1;
\r
5869 vuint32_t HLTACK31:1;
\r
5871 } HLTACK0; /* Halt Acknowledge Register 0 */
\r
5876 vuint32_t HLTACK0:1;
\r
5877 vuint32_t HLTACK1:1;
\r
5879 vuint32_t HLTACK3:1;
\r
5880 vuint32_t HLTACK4:1;
\r
5882 vuint32_t HLTACK20:1;
\r
5883 vuint32_t HLTACK21:1;
\r
5884 vuint32_t HLTACK22:1;
\r
5885 vuint32_t HLTACK23:1;
\r
5887 vuint32_t HLTACK26:1;
\r
5888 vuint32_t HLTACK27:1;
\r
5889 vuint32_t HLTACK28:1;
\r
5890 vuint32_t HLTACK29:1;
\r
5893 } HLTACK1; /* Halt Acknowledge Register 0 */
\r
5898 vuint32_t EMIOSSEL31:4;
\r
5899 vuint32_t EMIOSSEL30:4;
\r
5900 vuint32_t EMIOSSEL29:4;
\r
5901 vuint32_t EMIOSSEL28:4;
\r
5902 vuint32_t EMIOSSEL27:4;
\r
5903 vuint32_t EMIOSSEL26:4;
\r
5904 vuint32_t EMIOSSEL25:4;
\r
5905 vuint32_t EMIOSSEL24:4;
\r
5907 } EMIOS_SEL0; /* eMIOS Select Register 0 */
\r
5912 vuint32_t EMIOSSEL23:4;
\r
5913 vuint32_t EMIOSSEL22:4;
\r
5914 vuint32_t EMIOSSEL21:4;
\r
5915 vuint32_t EMIOSSEL20:4;
\r
5916 vuint32_t EMIOSSEL19:4;
\r
5917 vuint32_t EMIOSSEL18:4;
\r
5918 vuint32_t EMIOSSEL17:4;
\r
5919 vuint32_t EMIOSSEL16:4;
\r
5921 } EMIOS_SEL1; /* eMIOS Select Register 1 */
\r
5926 vuint32_t EMIOSSEL15:4;
\r
5927 vuint32_t EMIOSSEL14:4;
\r
5928 vuint32_t EMIOSSEL13:4;
\r
5929 vuint32_t EMIOSSEL12:4;
\r
5930 vuint32_t EMIOSSEL11:4;
\r
5931 vuint32_t EMIOSSEL10:4;
\r
5932 vuint32_t EMIOSSEL9:4;
\r
5933 vuint32_t EMIOSSEL8:4;
\r
5935 } EMIOS_SEL2; /* eMIOS Select Register 2 */
\r
5940 vuint32_t EMIOSSEL7:4;
\r
5941 vuint32_t EMIOSSEL6:4;
\r
5942 vuint32_t EMIOSSEL5:4;
\r
5943 vuint32_t EMIOSSEL4:4;
\r
5944 vuint32_t EMIOSSEL3:4;
\r
5945 vuint32_t EMIOSSEL2:4;
\r
5946 vuint32_t EMIOSSEL1:4;
\r
5947 vuint32_t EMIOSSEL0:4;
\r
5949 } EMIOS_SEL3; /* eMIOS Select Register 3 */
\r
5954 vuint32_t ESEL15:2;
\r
5955 vuint32_t ESEL14:2;
\r
5956 vuint32_t ESEL13:2;
\r
5957 vuint32_t ESEL12:2;
\r
5958 vuint32_t ESEL11:2;
\r
5959 vuint32_t ESEL10:2;
\r
5960 vuint32_t ESEL9:2;
\r
5961 vuint32_t ESEL8:2;
\r
5962 vuint32_t ESEL7:2;
\r
5963 vuint32_t ESEL6:2;
\r
5964 vuint32_t ESEL5:2;
\r
5965 vuint32_t ESEL4:2;
\r
5966 vuint32_t ESEL3:2;
\r
5967 vuint32_t ESEL2:2;
\r
5968 vuint32_t ESEL1:2;
\r
5969 vuint32_t ESEL0:2;
\r
5971 } ISEL2A; /* External Interrupt Select Register 2A */
\r
5973 int32_t SIU_reserved9[142];
\r
5981 } PGPDO0; /* Parallel GPIO Pin Data Output Register */
\r
5989 } PGPDO1; /* Parallel GPIO Pin Data Output Register */
\r
5997 } PGPDO2; /* Parallel GPIO Pin Data Output Register */
\r
6005 } PGPDO3; /* Parallel GPIO Pin Data Output Register */
\r
6014 } PGPDO4; /* Parallel GPIO Pin Data Output Register */
\r
6016 int32_t SIU_reserved10[11];
\r
6024 } PGPDI0; /* Parallel GPIO Pin Data Input Register */
\r
6032 } PGPDI1; /* Parallel GPIO Pin Data Input Register */
\r
6040 } PGPDI2; /* Parallel GPIO Pin Data Input Register */
\r
6048 } PGPDI3; /* Parallel GPIO Pin Data Input Register */
\r
6057 } PGPDI4; /* Parallel GPIO Pin Data Input Register */
\r
6059 int32_t SIU_reserved11[12];
\r
6064 vuint32_t PB_MASK:16;
\r
6067 } MPGPDO1; /* Masked Parallel GPIO Pin Data Input Register */
\r
6072 vuint32_t PC_MASK:16;
\r
6075 } MPGPDO2; /* Masked Parallel GPIO Pin Data Input Register */
\r
6080 vuint32_t PD_MASK:16;
\r
6083 } MPGPDO3; /* Masked Parallel GPIO Pin Data Input Register */
\r
6088 vuint32_t PE_MASK:16;
\r
6091 } MPGPDO4; /* Masked Parallel GPIO Pin Data Input Register */
\r
6096 vuint32_t PF_MASK:16;
\r
6099 } MPGPDO5; /* Masked Parallel GPIO Pin Data Input Register */
\r
6104 vuint32_t PG_MASK:16;
\r
6107 } MPGPDO6; /* Masked Parallel GPIO Pin Data Input Register */
\r
6112 vuint32_t PH_MASK:16;
\r
6115 } MPGPDO7; /* Masked Parallel GPIO Pin Data Input Register */
\r
6120 vuint32_t PJ_MASK:16;
\r
6123 } MPGPDO8; /* Masked Parallel GPIO Pin Data Input Register */
\r
6128 vuint32_t PK_MASK:11;
\r
6133 } MPGPDO9; /* Masked Parallel GPIO Pin Data Input Register */
\r
6135 int32_t SIU_reserved12[22];
\r
6140 vuint32_t MASK31:1;
\r
6141 vuint32_t MASK30:1;
\r
6142 vuint32_t MASK29:1;
\r
6143 vuint32_t MASK28:1;
\r
6144 vuint32_t MASK27:1;
\r
6145 vuint32_t MASK26:1;
\r
6146 vuint32_t MASK25:1;
\r
6147 vuint32_t MASK24:1;
\r
6148 vuint32_t MASK23:1;
\r
6149 vuint32_t MASK22:1;
\r
6150 vuint32_t MASK21:1;
\r
6151 vuint32_t MASK20:1;
\r
6152 vuint32_t MASK19:1;
\r
6153 vuint32_t MASK18:1;
\r
6154 vuint32_t MASK17:1;
\r
6155 vuint32_t MASK16:1;
\r
6156 vuint32_t DATA31:1;
\r
6157 vuint32_t DATA30:1;
\r
6158 vuint32_t DATA29:1;
\r
6159 vuint32_t DATA28:1;
\r
6160 vuint32_t DATA27:1;
\r
6161 vuint32_t DATA26:1;
\r
6162 vuint32_t DATA25:1;
\r
6163 vuint32_t DATA24:1;
\r
6164 vuint32_t DATA23:1;
\r
6165 vuint32_t DATA22:1;
\r
6166 vuint32_t DATA21:1;
\r
6167 vuint32_t DATA20:1;
\r
6168 vuint32_t DATA19:1;
\r
6169 vuint32_t DATA18:1;
\r
6170 vuint32_t DATA17:1;
\r
6171 vuint32_t DATA16:1;
\r
6173 } DSPIAH; /* Masked Serial GPO for DSPI_A High Register */
\r
6178 vuint32_t MASK15:1;
\r
6179 vuint32_t MASK14:1;
\r
6180 vuint32_t MASK13:1;
\r
6181 vuint32_t MASK12:1;
\r
6182 vuint32_t MASK11:1;
\r
6183 vuint32_t MASK10:1;
\r
6184 vuint32_t MASK9:1;
\r
6185 vuint32_t MASK8:1;
\r
6186 vuint32_t MASK7:1;
\r
6187 vuint32_t MASK6:1;
\r
6188 vuint32_t MASK5:1;
\r
6189 vuint32_t MASK4:1;
\r
6190 vuint32_t MASK3:1;
\r
6191 vuint32_t MASK2:1;
\r
6192 vuint32_t MASK1:1;
\r
6193 vuint32_t MASK0:1;
\r
6194 vuint32_t DATA15:1;
\r
6195 vuint32_t DATA14:1;
\r
6196 vuint32_t DATA13:1;
\r
6197 vuint32_t DATA12:1;
\r
6198 vuint32_t DATA11:1;
\r
6199 vuint32_t DATA10:1;
\r
6200 vuint32_t DATA9:1;
\r
6201 vuint32_t DATA8:1;
\r
6202 vuint32_t DATA7:1;
\r
6203 vuint32_t DATA6:1;
\r
6204 vuint32_t DATA5:1;
\r
6205 vuint32_t DATA4:1;
\r
6206 vuint32_t DATA3:1;
\r
6207 vuint32_t DATA2:1;
\r
6208 vuint32_t DATA1:1;
\r
6209 vuint32_t DATA0:1;
\r
6211 } DSPIAL; /* Masked Serial GPO for DSPI_A Low Register */
\r
6216 vuint32_t MASK31:1;
\r
6217 vuint32_t MASK30:1;
\r
6218 vuint32_t MASK29:1;
\r
6219 vuint32_t MASK28:1;
\r
6220 vuint32_t MASK27:1;
\r
6221 vuint32_t MASK26:1;
\r
6222 vuint32_t MASK25:1;
\r
6223 vuint32_t MASK24:1;
\r
6224 vuint32_t MASK23:1;
\r
6225 vuint32_t MASK22:1;
\r
6226 vuint32_t MASK21:1;
\r
6227 vuint32_t MASK20:1;
\r
6228 vuint32_t MASK19:1;
\r
6229 vuint32_t MASK18:1;
\r
6230 vuint32_t MASK17:1;
\r
6231 vuint32_t MASK16:1;
\r
6232 vuint32_t DATA31:1;
\r
6233 vuint32_t DATA30:1;
\r
6234 vuint32_t DATA29:1;
\r
6235 vuint32_t DATA28:1;
\r
6236 vuint32_t DATA27:1;
\r
6237 vuint32_t DATA26:1;
\r
6238 vuint32_t DATA25:1;
\r
6239 vuint32_t DATA24:1;
\r
6240 vuint32_t DATA23:1;
\r
6241 vuint32_t DATA22:1;
\r
6242 vuint32_t DATA21:1;
\r
6243 vuint32_t DATA20:1;
\r
6244 vuint32_t DATA19:1;
\r
6245 vuint32_t DATA18:1;
\r
6246 vuint32_t DATA17:1;
\r
6247 vuint32_t DATA16:1;
\r
6249 } DSPIBH; /* Masked Serial GPO for DSPI_B High Register */
\r
6254 vuint32_t MASK15:1;
\r
6255 vuint32_t MASK14:1;
\r
6256 vuint32_t MASK13:1;
\r
6257 vuint32_t MASK12:1;
\r
6258 vuint32_t MASK11:1;
\r
6259 vuint32_t MASK10:1;
\r
6260 vuint32_t MASK9:1;
\r
6261 vuint32_t MASK8:1;
\r
6262 vuint32_t MASK7:1;
\r
6263 vuint32_t MASK6:1;
\r
6264 vuint32_t MASK5:1;
\r
6265 vuint32_t MASK4:1;
\r
6266 vuint32_t MASK3:1;
\r
6267 vuint32_t MASK2:1;
\r
6268 vuint32_t MASK1:1;
\r
6269 vuint32_t MASK0:1;
\r
6270 vuint32_t DATA15:1;
\r
6271 vuint32_t DATA14:1;
\r
6272 vuint32_t DATA13:1;
\r
6273 vuint32_t DATA12:1;
\r
6274 vuint32_t DATA11:1;
\r
6275 vuint32_t DATA10:1;
\r
6276 vuint32_t DATA9:1;
\r
6277 vuint32_t DATA8:1;
\r
6278 vuint32_t DATA7:1;
\r
6279 vuint32_t DATA6:1;
\r
6280 vuint32_t DATA5:1;
\r
6281 vuint32_t DATA4:1;
\r
6282 vuint32_t DATA3:1;
\r
6283 vuint32_t DATA2:1;
\r
6284 vuint32_t DATA1:1;
\r
6285 vuint32_t DATA0:1;
\r
6287 } DSPIBL; /* Masked Serial GPO for DSPI_B Low Register */
\r
6292 vuint32_t MASK31:1;
\r
6293 vuint32_t MASK30:1;
\r
6294 vuint32_t MASK29:1;
\r
6295 vuint32_t MASK28:1;
\r
6296 vuint32_t MASK27:1;
\r
6297 vuint32_t MASK26:1;
\r
6298 vuint32_t MASK25:1;
\r
6299 vuint32_t MASK24:1;
\r
6300 vuint32_t MASK23:1;
\r
6301 vuint32_t MASK22:1;
\r
6302 vuint32_t MASK21:1;
\r
6303 vuint32_t MASK20:1;
\r
6304 vuint32_t MASK19:1;
\r
6305 vuint32_t MASK18:1;
\r
6306 vuint32_t MASK17:1;
\r
6307 vuint32_t MASK16:1;
\r
6308 vuint32_t DATA31:1;
\r
6309 vuint32_t DATA30:1;
\r
6310 vuint32_t DATA29:1;
\r
6311 vuint32_t DATA28:1;
\r
6312 vuint32_t DATA27:1;
\r
6313 vuint32_t DATA26:1;
\r
6314 vuint32_t DATA25:1;
\r
6315 vuint32_t DATA24:1;
\r
6316 vuint32_t DATA23:1;
\r
6317 vuint32_t DATA22:1;
\r
6318 vuint32_t DATA21:1;
\r
6319 vuint32_t DATA20:1;
\r
6320 vuint32_t DATA19:1;
\r
6321 vuint32_t DATA18:1;
\r
6322 vuint32_t DATA17:1;
\r
6323 vuint32_t DATA16:1;
\r
6325 } DSPICH; /* Masked Serial GPO for DSPI_C High Register */
\r
6330 vuint32_t MASK15:1;
\r
6331 vuint32_t MASK14:1;
\r
6332 vuint32_t MASK13:1;
\r
6333 vuint32_t MASK12:1;
\r
6334 vuint32_t MASK11:1;
\r
6335 vuint32_t MASK10:1;
\r
6336 vuint32_t MASK9:1;
\r
6337 vuint32_t MASK8:1;
\r
6338 vuint32_t MASK7:1;
\r
6339 vuint32_t MASK6:1;
\r
6340 vuint32_t MASK5:1;
\r
6341 vuint32_t MASK4:1;
\r
6342 vuint32_t MASK3:1;
\r
6343 vuint32_t MASK2:1;
\r
6344 vuint32_t MASK1:1;
\r
6345 vuint32_t MASK0:1;
\r
6346 vuint32_t DATA15:1;
\r
6347 vuint32_t DATA14:1;
\r
6348 vuint32_t DATA13:1;
\r
6349 vuint32_t DATA12:1;
\r
6350 vuint32_t DATA11:1;
\r
6351 vuint32_t DATA10:1;
\r
6352 vuint32_t DATA9:1;
\r
6353 vuint32_t DATA8:1;
\r
6354 vuint32_t DATA7:1;
\r
6355 vuint32_t DATA6:1;
\r
6356 vuint32_t DATA5:1;
\r
6357 vuint32_t DATA4:1;
\r
6358 vuint32_t DATA3:1;
\r
6359 vuint32_t DATA2:1;
\r
6360 vuint32_t DATA1:1;
\r
6361 vuint32_t DATA0:1;
\r
6363 } DSPICL; /* Masked Serial GPO for DSPI_C Low Register */
\r
6368 vuint32_t MASK31:1;
\r
6369 vuint32_t MASK30:1;
\r
6370 vuint32_t MASK29:1;
\r
6371 vuint32_t MASK28:1;
\r
6372 vuint32_t MASK27:1;
\r
6373 vuint32_t MASK26:1;
\r
6374 vuint32_t MASK25:1;
\r
6375 vuint32_t MASK24:1;
\r
6376 vuint32_t MASK23:1;
\r
6377 vuint32_t MASK22:1;
\r
6378 vuint32_t MASK21:1;
\r
6379 vuint32_t MASK20:1;
\r
6380 vuint32_t MASK19:1;
\r
6381 vuint32_t MASK18:1;
\r
6382 vuint32_t MASK17:1;
\r
6383 vuint32_t MASK16:1;
\r
6384 vuint32_t DATA31:1;
\r
6385 vuint32_t DATA30:1;
\r
6386 vuint32_t DATA29:1;
\r
6387 vuint32_t DATA28:1;
\r
6388 vuint32_t DATA27:1;
\r
6389 vuint32_t DATA26:1;
\r
6390 vuint32_t DATA25:1;
\r
6391 vuint32_t DATA24:1;
\r
6392 vuint32_t DATA23:1;
\r
6393 vuint32_t DATA22:1;
\r
6394 vuint32_t DATA21:1;
\r
6395 vuint32_t DATA20:1;
\r
6396 vuint32_t DATA19:1;
\r
6397 vuint32_t DATA18:1;
\r
6398 vuint32_t DATA17:1;
\r
6399 vuint32_t DATA16:1;
\r
6401 } DSPIDH; /* Masked Serial GPO for DSPI_D High Register */
\r
6406 vuint32_t MASK15:1;
\r
6407 vuint32_t MASK14:1;
\r
6408 vuint32_t MASK13:1;
\r
6409 vuint32_t MASK12:1;
\r
6410 vuint32_t MASK11:1;
\r
6411 vuint32_t MASK10:1;
\r
6412 vuint32_t MASK9:1;
\r
6413 vuint32_t MASK8:1;
\r
6414 vuint32_t MASK7:1;
\r
6415 vuint32_t MASK6:1;
\r
6416 vuint32_t MASK5:1;
\r
6417 vuint32_t MASK4:1;
\r
6418 vuint32_t MASK3:1;
\r
6419 vuint32_t MASK2:1;
\r
6420 vuint32_t MASK1:1;
\r
6421 vuint32_t MASK0:1;
\r
6422 vuint32_t DATA15:1;
\r
6423 vuint32_t DATA14:1;
\r
6424 vuint32_t DATA13:1;
\r
6425 vuint32_t DATA12:1;
\r
6426 vuint32_t DATA11:1;
\r
6427 vuint32_t DATA10:1;
\r
6428 vuint32_t DATA9:1;
\r
6429 vuint32_t DATA8:1;
\r
6430 vuint32_t DATA7:1;
\r
6431 vuint32_t DATA6:1;
\r
6432 vuint32_t DATA5:1;
\r
6433 vuint32_t DATA4:1;
\r
6434 vuint32_t DATA3:1;
\r
6435 vuint32_t DATA2:1;
\r
6436 vuint32_t DATA1:1;
\r
6437 vuint32_t DATA0:1;
\r
6439 } DSPIDL; /* Masked Serial GPO for DSPI_D Low Register */
\r
6441 int32_t SIU_reserved13[9];
\r
6446 vuint32_t EMIOS31:1;
\r
6447 vuint32_t EMIOS30:1;
\r
6448 vuint32_t EMIOS29:1;
\r
6449 vuint32_t EMIOS28:1;
\r
6450 vuint32_t EMIOS27:1;
\r
6451 vuint32_t EMIOS26:1;
\r
6452 vuint32_t EMIOS25:1;
\r
6453 vuint32_t EMIOS24:1;
\r
6454 vuint32_t EMIOS23:1;
\r
6455 vuint32_t EMIOS22:1;
\r
6456 vuint32_t EMIOS21:1;
\r
6457 vuint32_t EMIOS20:1;
\r
6458 vuint32_t EMIOS19:1;
\r
6459 vuint32_t EMIOS18:1;
\r
6460 vuint32_t EMIOS17:1;
\r
6461 vuint32_t EMIOS16:1;
\r
6462 vuint32_t EMIOS15:1;
\r
6463 vuint32_t EMIOS14:1;
\r
6464 vuint32_t EMIOS13:1;
\r
6465 vuint32_t EMIOS12:1;
\r
6466 vuint32_t EMIOS11:1;
\r
6467 vuint32_t EMIOS10:1;
\r
6468 vuint32_t EMIOS9:1;
\r
6469 vuint32_t EMIOS8:1;
\r
6470 vuint32_t EMIOS7:1;
\r
6471 vuint32_t EMIOS6:1;
\r
6472 vuint32_t EMIOS5:1;
\r
6473 vuint32_t EMIOS4:1;
\r
6474 vuint32_t EMIOS3:1;
\r
6475 vuint32_t EMIOS2:1;
\r
6476 vuint32_t EMIOS1:1;
\r
6477 vuint32_t EMIOS0:1;
\r
6479 } EMIOSA; /* EMIOS A Select Register */
\r
6484 vuint32_t DSPIAH31:1;
\r
6485 vuint32_t DSPIAH30:1;
\r
6486 vuint32_t DSPIAH29:1;
\r
6487 vuint32_t DSPIAH28:1;
\r
6488 vuint32_t DSPIAH27:1;
\r
6489 vuint32_t DSPIAH26:1;
\r
6490 vuint32_t DSPIAH25:1;
\r
6491 vuint32_t DSPIAH24:1;
\r
6492 vuint32_t DSPIAH23:1;
\r
6493 vuint32_t DSPIAH22:1;
\r
6494 vuint32_t DSPIAH21:1;
\r
6495 vuint32_t DSPIAH20:1;
\r
6496 vuint32_t DSPIAH19:1;
\r
6497 vuint32_t DSPIAH18:1;
\r
6498 vuint32_t DSPIAH17:1;
\r
6499 vuint32_t DSPIAH16:1;
\r
6500 vuint32_t DSPIAL15:1;
\r
6501 vuint32_t DSPIAL14:1;
\r
6502 vuint32_t DSPIAL13:1;
\r
6503 vuint32_t DSPIAL12:1;
\r
6504 vuint32_t DSPIAL11:1;
\r
6505 vuint32_t DSPIAL10:1;
\r
6506 vuint32_t DSPIAL9:1;
\r
6507 vuint32_t DSPIAL8:1;
\r
6508 vuint32_t DSPIAL7:1;
\r
6509 vuint32_t DSPIAL6:1;
\r
6510 vuint32_t DSPIAL5:1;
\r
6511 vuint32_t DSPIAL4:1;
\r
6512 vuint32_t DSPIAL3:1;
\r
6513 vuint32_t DSPIAL2:1;
\r
6514 vuint32_t DSPIAL1:1;
\r
6515 vuint32_t DSPIAL0:1;
\r
6517 } DSPIAHLA; /* DSPIAH/L Select Register for DSPI A */
\r
6519 int32_t SIU_reserved14[2];
\r
6524 vuint32_t EMIOS31:1;
\r
6525 vuint32_t EMIOS30:1;
\r
6526 vuint32_t EMIOS29:1;
\r
6527 vuint32_t EMIOS28:1;
\r
6528 vuint32_t EMIOS27:1;
\r
6529 vuint32_t EMIOS26:1;
\r
6530 vuint32_t EMIOS25:1;
\r
6531 vuint32_t EMIOS24:1;
\r
6532 vuint32_t EMIOS23:1;
\r
6533 vuint32_t EMIOS22:1;
\r
6534 vuint32_t EMIOS21:1;
\r
6535 vuint32_t EMIOS20:1;
\r
6536 vuint32_t EMIOS19:1;
\r
6537 vuint32_t EMIOS18:1;
\r
6538 vuint32_t EMIOS17:1;
\r
6539 vuint32_t EMIOS16:1;
\r
6540 vuint32_t EMIOS15:1;
\r
6541 vuint32_t EMIOS14:1;
\r
6542 vuint32_t EMIOS13:1;
\r
6543 vuint32_t EMIOS12:1;
\r
6544 vuint32_t EMIOS11:1;
\r
6545 vuint32_t EMIOS10:1;
\r
6546 vuint32_t EMIOS9:1;
\r
6547 vuint32_t EMIOS8:1;
\r
6548 vuint32_t EMIOS7:1;
\r
6549 vuint32_t EMIOS6:1;
\r
6550 vuint32_t EMIOS5:1;
\r
6551 vuint32_t EMIOS4:1;
\r
6552 vuint32_t EMIOS3:1;
\r
6553 vuint32_t EMIOS2:1;
\r
6554 vuint32_t EMIOS1:1;
\r
6555 vuint32_t EMIOS0:1;
\r
6557 } EMIOSB; /* EMIOS B Select Register */
\r
6562 vuint32_t DSPIBH31:1;
\r
6563 vuint32_t DSPIBH30:1;
\r
6564 vuint32_t DSPIBH29:1;
\r
6565 vuint32_t DSPIBH28:1;
\r
6566 vuint32_t DSPIBH27:1;
\r
6567 vuint32_t DSPIBH26:1;
\r
6568 vuint32_t DSPIBH25:1;
\r
6569 vuint32_t DSPIBH24:1;
\r
6570 vuint32_t DSPIBH23:1;
\r
6571 vuint32_t DSPIBH22:1;
\r
6572 vuint32_t DSPIBH21:1;
\r
6573 vuint32_t DSPIBH20:1;
\r
6574 vuint32_t DSPIBH19:1;
\r
6575 vuint32_t DSPIBH18:1;
\r
6576 vuint32_t DSPIBH17:1;
\r
6577 vuint32_t DSPIBH16:1;
\r
6578 vuint32_t DSPIBL15:1;
\r
6579 vuint32_t DSPIBL14:1;
\r
6580 vuint32_t DSPIBL13:1;
\r
6581 vuint32_t DSPIBL12:1;
\r
6582 vuint32_t DSPIBL11:1;
\r
6583 vuint32_t DSPIBL10:1;
\r
6584 vuint32_t DSPIBL9:1;
\r
6585 vuint32_t DSPIBL8:1;
\r
6586 vuint32_t DSPIBL7:1;
\r
6587 vuint32_t DSPIBL6:1;
\r
6588 vuint32_t DSPIBL5:1;
\r
6589 vuint32_t DSPIBL4:1;
\r
6590 vuint32_t DSPIBL3:1;
\r
6591 vuint32_t DSPIBL2:1;
\r
6592 vuint32_t DSPIBL1:1;
\r
6593 vuint32_t DSPIBL0:1;
\r
6595 } DSPIBHLB; /* DSPIBH/L Select Register for DSPI B */
\r
6597 int32_t SIU_reserved115[2];
\r
6602 vuint32_t EMIOS31:1;
\r
6603 vuint32_t EMIOS30:1;
\r
6604 vuint32_t EMIOS29:1;
\r
6605 vuint32_t EMIOS28:1;
\r
6606 vuint32_t EMIOS27:1;
\r
6607 vuint32_t EMIOS26:1;
\r
6608 vuint32_t EMIOS25:1;
\r
6609 vuint32_t EMIOS24:1;
\r
6610 vuint32_t EMIOS23:1;
\r
6611 vuint32_t EMIOS22:1;
\r
6612 vuint32_t EMIOS21:1;
\r
6613 vuint32_t EMIOS20:1;
\r
6614 vuint32_t EMIOS19:1;
\r
6615 vuint32_t EMIOS18:1;
\r
6616 vuint32_t EMIOS17:1;
\r
6617 vuint32_t EMIOS16:1;
\r
6618 vuint32_t EMIOS15:1;
\r
6619 vuint32_t EMIOS14:1;
\r
6620 vuint32_t EMIOS13:1;
\r
6621 vuint32_t EMIOS12:1;
\r
6622 vuint32_t EMIOS11:1;
\r
6623 vuint32_t EMIOS10:1;
\r
6624 vuint32_t EMIOS9:1;
\r
6625 vuint32_t EMIOS8:1;
\r
6626 vuint32_t EMIOS7:1;
\r
6627 vuint32_t EMIOS6:1;
\r
6628 vuint32_t EMIOS5:1;
\r
6629 vuint32_t EMIOS4:1;
\r
6630 vuint32_t EMIOS3:1;
\r
6631 vuint32_t EMIOS2:1;
\r
6632 vuint32_t EMIOS1:1;
\r
6633 vuint32_t EMIOS0:1;
\r
6635 } EMIOSC; /* EMIOS C Select Register */
\r
6640 vuint32_t DSPICH31:1;
\r
6641 vuint32_t DSPICH30:1;
\r
6642 vuint32_t DSPICH29:1;
\r
6643 vuint32_t DSPICH28:1;
\r
6644 vuint32_t DSPICH27:1;
\r
6645 vuint32_t DSPICH26:1;
\r
6646 vuint32_t DSPICH25:1;
\r
6647 vuint32_t DSPICH24:1;
\r
6648 vuint32_t DSPICH23:1;
\r
6649 vuint32_t DSPICH22:1;
\r
6650 vuint32_t DSPICH21:1;
\r
6651 vuint32_t DSPICH20:1;
\r
6652 vuint32_t DSPICH19:1;
\r
6653 vuint32_t DSPICH18:1;
\r
6654 vuint32_t DSPICH17:1;
\r
6655 vuint32_t DSPICH16:1;
\r
6656 vuint32_t DSPICL15:1;
\r
6657 vuint32_t DSPICL14:1;
\r
6658 vuint32_t DSPICL13:1;
\r
6659 vuint32_t DSPICL12:1;
\r
6660 vuint32_t DSPICL11:1;
\r
6661 vuint32_t DSPICL10:1;
\r
6662 vuint32_t DSPICL9:1;
\r
6663 vuint32_t DSPICL8:1;
\r
6664 vuint32_t DSPICL7:1;
\r
6665 vuint32_t DSPICL6:1;
\r
6666 vuint32_t DSPICL5:1;
\r
6667 vuint32_t DSPICL4:1;
\r
6668 vuint32_t DSPICL3:1;
\r
6669 vuint32_t DSPICL2:1;
\r
6670 vuint32_t DSPICL1:1;
\r
6671 vuint32_t DSPICL0:1;
\r
6673 } DSPICHLC; /* DSPIAH/L Select Register for DSPI C */
\r
6675 int32_t SIU_reserved16[2];
\r
6680 vuint32_t EMIOS31:1;
\r
6681 vuint32_t EMIOS30:1;
\r
6682 vuint32_t EMIOS29:1;
\r
6683 vuint32_t EMIOS28:1;
\r
6684 vuint32_t EMIOS27:1;
\r
6685 vuint32_t EMIOS26:1;
\r
6686 vuint32_t EMIOS25:1;
\r
6687 vuint32_t EMIOS24:1;
\r
6688 vuint32_t EMIOS23:1;
\r
6689 vuint32_t EMIOS22:1;
\r
6690 vuint32_t EMIOS21:1;
\r
6691 vuint32_t EMIOS20:1;
\r
6692 vuint32_t EMIOS19:1;
\r
6693 vuint32_t EMIOS18:1;
\r
6694 vuint32_t EMIOS17:1;
\r
6695 vuint32_t EMIOS16:1;
\r
6696 vuint32_t EMIOS15:1;
\r
6697 vuint32_t EMIOS14:1;
\r
6698 vuint32_t EMIOS13:1;
\r
6699 vuint32_t EMIOS12:1;
\r
6700 vuint32_t EMIOS11:1;
\r
6701 vuint32_t EMIOS10:1;
\r
6702 vuint32_t EMIOS9:1;
\r
6703 vuint32_t EMIOS8:1;
\r
6704 vuint32_t EMIOS7:1;
\r
6705 vuint32_t EMIOS6:1;
\r
6706 vuint32_t EMIOS5:1;
\r
6707 vuint32_t EMIOS4:1;
\r
6708 vuint32_t EMIOS3:1;
\r
6709 vuint32_t EMIOS2:1;
\r
6710 vuint32_t EMIOS1:1;
\r
6711 vuint32_t EMIOS0:1;
\r
6713 } EMIOSD; /* EMIOS D Select Register */
\r
6718 vuint32_t DSPIDH31:1;
\r
6719 vuint32_t DSPIDH30:1;
\r
6720 vuint32_t DSPIDH29:1;
\r
6721 vuint32_t DSPIDH28:1;
\r
6722 vuint32_t DSPIDH27:1;
\r
6723 vuint32_t DSPIDH26:1;
\r
6724 vuint32_t DSPIDH25:1;
\r
6725 vuint32_t DSPIDH24:1;
\r
6726 vuint32_t DSPIDH23:1;
\r
6727 vuint32_t DSPIDH22:1;
\r
6728 vuint32_t DSPIDH21:1;
\r
6729 vuint32_t DSPIDH20:1;
\r
6730 vuint32_t DSPIDH19:1;
\r
6731 vuint32_t DSPIDH18:1;
\r
6732 vuint32_t DSPIDH17:1;
\r
6733 vuint32_t DSPIDH16:1;
\r
6734 vuint32_t DSPIDL15:1;
\r
6735 vuint32_t DSPIDL14:1;
\r
6736 vuint32_t DSPIDL13:1;
\r
6737 vuint32_t DSPIDL12:1;
\r
6738 vuint32_t DSPIDL11:1;
\r
6739 vuint32_t DSPIDL10:1;
\r
6740 vuint32_t DSPIDL9:1;
\r
6741 vuint32_t DSPIDL8:1;
\r
6742 vuint32_t DSPIDL7:1;
\r
6743 vuint32_t DSPIDL6:1;
\r
6744 vuint32_t DSPIDL5:1;
\r
6745 vuint32_t DSPIDL4:1;
\r
6746 vuint32_t DSPIDL3:1;
\r
6747 vuint32_t DSPIDL2:1;
\r
6748 vuint32_t DSPIDL1:1;
\r
6749 vuint32_t DSPIDL0:1;
\r
6751 } DSPIDHLD; /* DSPIAH/L Select Register for DSPI D */
\r
6753 }; /* end of SIU_tag */
\r
6754 /**************************************************************************/
\r
6755 /* MODULE : STM */
\r
6756 /**************************************************************************/
\r
6768 } CR; /* STM Control Register */
\r
6772 } CNT; /* STM Count Register */
\r
6774 int32_t STM_reserved[2];
\r
6782 } CCR0; /* STM Channel Control Register 0 */
\r
6790 } CIR0; /* STM Channel Interrupt Register 0 */
\r
6794 } CMP0; /* STM Channel Compare Register 0 */
\r
6796 int32_t STM_reserved1;
\r
6804 } CCR1; /* STM Channel Control Register 1 */
\r
6812 } CIR1; /* STM Channel Interrupt Register 1 */
\r
6816 } CMP1; /* STM Channel Compare Register 1 */
\r
6818 int32_t STM_reserved2;
\r
6826 } CCR2; /* STM Channel Control Register 2 */
\r
6834 } CIR2; /* STM Channel Interrupt Register 2 */
\r
6838 } CMP2; /* STM Channel Compare Register 2 */
\r
6840 int32_t STM_reserved3;
\r
6848 } CCR3; /* STM Channel Control Register 3 */
\r
6856 } CIR3; /* STM Channel Interrupt Register 3 */
\r
6860 } CMP3; /* STM Channel Compare Register 3 */
\r
6862 }; /* end of STM_tag */
\r
6863 /**************************************************************************/
\r
6864 /* MODULE : SWT */
\r
6865 /**************************************************************************/
\r
6889 } CR; /* SWT Control Register */
\r
6897 } IR; /* SWT Interrupt Register */
\r
6904 } TO; /* SWT Time-Out Register */
\r
6911 } WN; /* SWT Window Register */
\r
6919 } SR; /* SWT Service Register */
\r
6926 } CO; /* SWT Counter Output Register */
\r
6934 } SK; /* SWT Service Key Register */
\r
6936 }; /* end of SWT_tag */
\r
6938 /* Define memories */
\r
6940 #define SRAM0_START 0x40000000
\r
6941 #define SRAM0_SIZE 0x80000
\r
6942 #define SRAM0_END 0x4007FFFFUL
\r
6944 #define SRAM1_START 0x40080000UL
\r
6945 #define SRAM1_SIZE 0x14000
\r
6946 #define SRAM1_END 0x40093FFFUL
\r
6948 #define FLASH_START 0x0UL
\r
6949 #define FLASH_SIZE 0x200000UL
\r
6950 #define FLASH_END 0x1FFFFFUL
\r
6952 /* Define instances of modules AIPS_A */
\r
6953 #define MLB (*(volatile struct MLB_tag *) 0xC3F84000UL)
\r
6954 #define I2C_C (*(volatile struct I2C_tag *) 0xC3F88000UL)
\r
6955 #define I2C_D (*(volatile struct I2C_tag *) 0xC3F8C000UL)
\r
6956 #define DSPI_C (*(volatile struct DSPI_tag *) 0xC3F90000UL)
\r
6957 #define DSPI_D (*(volatile struct DSPI_tag *) 0xC3F94000UL)
\r
6958 #define ESCI_J (*(volatile struct ESCI_tag *) 0xC3FA0000UL)
\r
6959 #define ESCI_K (*(volatile struct ESCI_tag *) 0xC3FA4000UL)
\r
6960 #define ESCI_L (*(volatile struct ESCI_tag *) 0xC3FA8000UL)
\r
6961 #define ESCI_M (*(volatile struct ESCI_tag *) 0xC3FAC000UL)
\r
6962 #define FR (*(volatile struct FR_tag *) 0xC3FDC000UL)
\r
6964 /* Define instances of modules AIPS_B */
\r
6965 #define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000UL)
\r
6966 #define SEMA4 (*(volatile struct SEMA4_tag *) 0xFFF10000UL)
\r
6967 #define MPU (*(volatile struct MPU_tag *) 0xFFF14000UL)
\r
6968 #define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)
\r
6969 #define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)
\r
6970 #define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)
\r
6971 #define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL)
\r
6972 #define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
\r
6973 #define FEC (*(volatile struct FEC_tag *) 0xFFF4C000UL)
\r
6974 #define ADC (*(volatile struct ADC_tag *) 0xFFF80000UL)
\r
6975 #define I2C_A (*(volatile struct I2C_tag *) 0xFFF88000UL)
\r
6976 #define I2C_B (*(volatile struct I2C_tag *) 0xFFF8C000UL)
\r
6977 #define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000UL)
\r
6978 #define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000UL)
\r
6979 #define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFA0000UL)
\r
6980 #define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFA4000UL)
\r
6981 #define ESCI_C (*(volatile struct ESCI_tag *) 0xFFFA8000UL)
\r
6982 #define ESCI_D (*(volatile struct ESCI_tag *) 0xFFFAC000UL)
\r
6983 #define ESCI_E (*(volatile struct ESCI_tag *) 0xFFFB0000UL)
\r
6984 #define ESCI_F (*(volatile struct ESCI_tag *) 0xFFFB4000UL)
\r
6985 #define ESCI_G (*(volatile struct ESCI_tag *) 0xFFFB8000UL)
\r
6986 #define ESCI_H (*(volatile struct ESCI_tag *) 0xFFFBC000UL)
\r
6987 #define CAN_A (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
\r
6988 #define CAN_B (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)
\r
6989 #define CAN_C (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)
\r
6990 #define CAN_D (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)
\r
6991 #define CAN_E (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)
\r
6992 #define CAN_F (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)
\r
6993 #define CTU (*(volatile struct CTU_tag *) 0xFFFD8000UL)
\r
6994 #define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)
\r
6995 #define PIT (*(volatile struct PIT_tag *) 0xFFFE0000UL)
\r
6996 #define EMIOS (*(volatile struct EMIOS_tag *) 0xFFFE4000UL)
\r
6997 #define SIU (*(volatile struct SIU_tag *) 0xFFFE8000UL)
\r
6998 #define CRP (*(volatile struct CRP_tag *) 0xFFFEC000UL)
\r
6999 #define FMPLL (*(volatile struct FMPLL_tag *) 0xFFFF0000UL)
\r
7000 #define FLASH (*(volatile struct FLASH_tag *) 0xFFFF8000UL)
\r
7006 #ifdef __cplusplus
\r
7009 #endif /* ifdef _MPC5668_H */
\r
projects / arc.git / blob