2 /**************************************************************************/
\r
3 /* FILE NAME: mpc5554.h COPYRIGHT (c) Freescale 2007 */
\r
4 /* VERSION: 1.7 All Rights Reserved */
\r
7 /* This file contain all of the register and bit field definitions for */
\r
9 /*========================================================================*/
\r
10 /* UPDATE HISTORY */
\r
11 /* REV AUTHOR DATE DESCRIPTION OF CHANGE */
\r
12 /* --- ----------- --------- --------------------- */
\r
13 /* 0.01 J. Loeliger 03/Mar/03 Initial version of file for MPC5554. */
\r
14 /* Based on SoC version 0.7. */
\r
15 /* 0.02 J. Loeliger 05/Mar/03 All registers and bit fields now */
\r
17 /* 0.03 J. Loeliger 05/May/03 Updated to current spec., fixed several*/
\r
18 /* bugs and naming/formating issues. */
\r
19 /* 0.04 J. Loeliger 16/May/03 More fixes and naming/formating issues.*/
\r
20 /* 0.05 J. Loeliger 19/Aug/03 Updated for latest documentation. */
\r
21 /* 0.06 J. Loeliger 03/Sep/03 Changed to include motint.h */
\r
22 /* Updated many register names. */
\r
23 /* 0.07 J. Loeliger 04/Nov/03 Changed to include typedefs.h and more */
\r
24 /* register name updates. */
\r
25 /* 0.08 J. Loeliger 25/Feb/04 Added MetroWerks #pragmas. */
\r
26 /* Updated for user manual 1.0 */
\r
27 /* 0.09 J. Loeliger 27/Feb/04 Updated eDMA tcd section and some more */
\r
28 /* bit field names to match user's man. */
\r
29 /* 0.10 J. Loeliger 01/Apr/04 Fixed register spacing in ADC and eTPU */
\r
30 /* 0.11 J. Loeliger 16/Jun/04 Many fixes and updated to user's */
\r
31 /* manual, also some testing done. */
\r
32 /* 0.12 J. Loeliger 25/Jun/04 Fixed problems in edma and eTPU. */
\r
33 /* 0.13 J. Loeliger 16/Jul/04 Fixed mistake in FlexCAN TIMER size and*/
\r
34 /* changed eTPU memory defs to start with*/
\r
36 /* 0.14 J. Loeliger 17/Nov/04 Added ETPU_CODE_RAM definition. */
\r
37 /* All code moved to CVS repository. */
\r
38 /* Updated copyright to Freescale. */
\r
39 /* Added new SCMOFFDATAR register to eTPU*/
\r
40 /* Fixed REDCR_A&B bit fields in eTPU. */
\r
41 /* Added new DBR bit in CTAR for DSPI. */
\r
42 /* 0.15 J. Loeliger 29/Nov/04 Added support for new eTPU util funcs. */
\r
43 /* Added bit fields for FlexCAN buffer ID*/
\r
44 /* 0.16 J. Loeliger 01/Dec/04 Corrected comments in release 0.16. */
\r
45 /* 0.17 J. Loeliger 02/Dec/04 Moved eTPU variable definitions to a */
\r
46 /* seperate new file. */
\r
47 /* Removed SIU variable the GPIO */
\r
48 /* routines do not need it. */
\r
49 /* 1.0 G.Emerson 22/Feb/05 No real changes to this file. */
\r
50 /* Joint generation with mpc5553.h */
\r
51 /* 1.1 G. Emerson 6/Jun/05 Changes to SIU to allow for upward */
\r
52 /* expansion of PCR/GPDI/GPDO */
\r
53 /* Added #defines for memory sizes etc */
\r
54 /* 1.2 G. Emerson 21/Sep/05 PBRIDGES fixes */
\r
55 /* 1.3 G. Emerson 03/Jan/06 Pbridge MPCR/PACR/OPACR now generic */
\r
56 /* XBAR MPR now generic */
\r
57 /* ECSM has FSBMCR on all integrations */
\r
58 /* 1.4 G. Emerson 24/Jan/06 Make Pbridges, XBAR, Flash BIU */
\r
59 /* integration specific */
\r
60 /* 1.5 S. Mathieson 28/Jul/06 Split out unused bit to support build */
\r
61 /* process. No real change. */
\r
62 /* 1.6 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */
\r
63 /* to DPB to align with documentation. */
\r
64 /* 1.7 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */
\r
65 /* alternate configuration. INTC, */
\r
66 /* correction to the number of PSR */
\r
68 /**************************************************************************/
\r
69 /*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
\r
74 #include "Compiler.h"
\r
75 #include "typedefs.h"
\r
83 #pragma ANSI_strict off
\r
86 /****************************************************************************/
\r
87 /* MODULE : PBRIDGE_A Peripheral Bridge */
\r
88 /****************************************************************************/
\r
89 struct PBRIDGE_A_tag {
\r
118 } MPCR; /* Master Privilege Control Register */
\r
120 uint32_t pbridge_a_reserved2[7];
\r
133 uint32_t pbridge_a_reserved3[7];
\r
163 vuint32_t BW0:1; /* EMIOS */
\r
198 /****************************************************************************/
\r
199 /* MODULE : PBRIDGE_B Peripheral Bridge */
\r
200 /****************************************************************************/
\r
201 struct PBRIDGE_B_tag {
\r
230 } MPCR; /* Master Privilege Control Register */
\r
232 uint32_t pbridge_b_reserved2[7];
\r
249 uint32_t pbridge_b_reserved3;
\r
274 uint32_t pbridge_b_reserved4[5];
\r
285 vuint32_t BW4:1; /* DSPI_A */
\r
290 vuint32_t BW5:1; /* DSPI_B */
\r
315 vuint32_t BW5:1; /* ESCI_B */
\r
332 vuint32_t BW1:1; /* CAN_B */
\r
365 /****************************************************************************/
\r
366 /* MODULE : FMPLL */
\r
367 /****************************************************************************/
\r
373 vuint32_t PREDIV:3;
\r
380 vuint32_t DISCLK:1;
\r
381 vuint32_t LOLIRQ:1;
\r
382 vuint32_t LOCIRQ:1;
\r
396 vuint32_t PLLSEL:1;
\r
397 vuint32_t PLLREF:1;
\r
401 vuint32_t CALDONE:1;
\r
402 vuint32_t CALPASS:1;
\r
407 /****************************************************************************/
\r
408 /* MODULE : External Bus Interface (EBI) */
\r
409 /****************************************************************************/
\r
411 union { /* Base Register Bank */
\r
427 union { /* Option Register Bank */
\r
440 union { /* Module Configuration Register */
\r
444 vuint32_t SIZEEN:1;
\r
458 uint32_t EBI_reserved1;
\r
460 union { /* Transfer Error Status Register */
\r
469 union { /* Bus Monitor Control Register */
\r
479 struct CS_tag CS[4];
\r
482 /****************************************************************************/
\r
483 /* MODULE : FLASH */
\r
484 /****************************************************************************/
\r
486 union { /* Module Configuration Register */
\r
515 union { /* LML Register */
\r
522 vuint32_t LLOCK:16;
\r
526 union { /* HL Register */
\r
531 vuint32_t HBLOCK:28;
\r
535 union { /* SLML Register */
\r
540 vuint32_t SSLOCK:1;
\r
541 vuint32_t SMLOCK:4;
\r
542 vuint32_t SLLOCK:16;
\r
546 union { /* LMS Register */
\r
559 vuint32_t HBSEL:28;
\r
611 /****************************************************************************/
\r
613 /****************************************************************************/
\r
615 int32_t SIU_reserved0;
\r
617 union { /* MCU ID Register */
\r
620 vuint32_t PARTNUM:16;
\r
621 vuint32_t MASKNUM:16;
\r
624 int32_t SIU_reserved00;
\r
626 union { /* Reset Status Register */
\r
638 vuint32_t WKPCFG:1;
\r
640 vuint32_t BOOTCFG:2;
\r
645 union { /* System Reset Control Register */
\r
656 union { /* External Interrupt Status Register */
\r
679 union { /* DMA/Interrupt Request Enable Register */
\r
683 vuint32_t EIRE15:1;
\r
684 vuint32_t EIRE14:1;
\r
685 vuint32_t EIRE13:1;
\r
686 vuint32_t EIRE12:1;
\r
687 vuint32_t EIRE11:1;
\r
688 vuint32_t EIRE10:1;
\r
702 union { /* DMA/Interrupt Select Register */
\r
713 union { /* Overrun Status Register */
\r
736 union { /* Overrun Request Enable Register */
\r
759 union { /* External IRQ Rising-Edge Event Enable Register */
\r
763 vuint32_t IREE15:1;
\r
764 vuint32_t IREE14:1;
\r
765 vuint32_t IREE13:1;
\r
766 vuint32_t IREE12:1;
\r
767 vuint32_t IREE11:1;
\r
768 vuint32_t IREE10:1;
\r
782 union { /* External IRQ Falling-Edge Event Enable Register */
\r
786 vuint32_t IFEE15:1;
\r
787 vuint32_t IFEE14:1;
\r
788 vuint32_t IFEE13:1;
\r
789 vuint32_t IFEE12:1;
\r
790 vuint32_t IFEE11:1;
\r
791 vuint32_t IFEE10:1;
\r
805 union { /* External IRQ Digital Filter Register */
\r
813 int32_t SIU_reserved1[3];
\r
815 union { /* Pad Configuration Registers */
\r
831 int16_t SIU_reserved_0[224];
\r
833 union { /* GPIO Pin Data Output Registers */
\r
841 int32_t SIU_reserved_3[64];
\r
843 union { /* GPIO Pin Data Input Registers */
\r
851 union { /* IMUX Register */
\r
864 union { /* IMUX Register */
\r
867 vuint32_t ESEL15:2;
\r
868 vuint32_t ESEL14:2;
\r
869 vuint32_t ESEL13:2;
\r
870 vuint32_t ESEL12:2;
\r
871 vuint32_t ESEL11:2;
\r
872 vuint32_t ESEL10:2;
\r
886 union { /* IMUX Register */
\r
889 vuint32_t SINSELA:2;
\r
890 vuint32_t SSSELA:2;
\r
891 vuint32_t SCKSELA:2;
\r
892 vuint32_t TRIGSELA:2;
\r
893 vuint32_t SINSELB:2;
\r
894 vuint32_t SSSELB:2;
\r
895 vuint32_t SCKSELB:2;
\r
896 vuint32_t TRIGSELB:2;
\r
897 vuint32_t SINSELC:2;
\r
898 vuint32_t SSSELC:2;
\r
899 vuint32_t SCKSELC:2;
\r
900 vuint32_t TRIGSELC:2;
\r
901 vuint32_t SINSELD:2;
\r
902 vuint32_t SSSELD:2;
\r
903 vuint32_t SCKSELD:2;
\r
904 vuint32_t TRIGSELD:2;
\r
908 int32_t SIU_reserved2[29];
\r
910 union { /* Chip Configuration Register Register */
\r
915 vuint32_t DISNEX:1;
\r
920 union { /* External Clock Configuration Register Register */
\r
924 vuint32_t ENGDIV:6;
\r
949 /****************************************************************************/
\r
950 /* MODULE : EMIOS */
\r
951 /****************************************************************************/
\r
967 } MCR; /* Module Configuration Register */
\r
998 } GFR; /* Global FLAG Register */
\r
1029 } OUDR; /* Output Update Disable Register */
\r
1031 uint32_t emios_reserved[5];
\r
1035 vuint32_t R; /* Channel A Data Register */
\r
1039 vuint32_t R; /* Channel B Data Register */
\r
1043 vuint32_t R; /* Channel Counter Register */
\r
1051 vuint32_t ODISSL:2;
\r
1052 vuint32_t UCPRE:2;
\r
1053 vuint32_t UCPREN:1;
\r
1060 vuint32_t FORCMA:1;
\r
1061 vuint32_t FORCMB:1;
\r
1064 vuint32_t EDSEL:1;
\r
1065 vuint32_t EDPOL:1;
\r
1068 } CCR; /* Channel Control Register */
\r
1078 vuint32_t UCOUT:1;
\r
1081 } CSR; /* Channel Status Register */
\r
1082 uint32_t emios_channel_reserved[3];
\r
1087 /****************************************************************************/
\r
1088 /* MODULE :ETPU */
\r
1089 /****************************************************************************/
\r
1091 /***************************Configuration Registers**************************/
\r
1094 union { /* MODULE CONFIGURATION REGISTER */
\r
1097 vuint32_t GEC:1; /* Global Exception Clear */
\r
1099 vuint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */
\r
1101 vuint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */
\r
1103 vuint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */
\r
1105 vuint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */
\r
1108 vuint32_t SCMSIZE:5; /* Shared Code Memory size */
\r
1110 vuint32_t SCMMISF:1; /* SCM MISC Flag */
\r
1111 vuint32_t SCMMISEN:1; /* SCM MISC Enable */
\r
1113 vuint32_t VIS:1; /* SCM Visability */
\r
1115 vuint32_t GTBE:1; /* Global Time Base Enable */
\r
1119 union { /* COHERENT DUAL-PARAMETER CONTROL */
\r
1122 vuint32_t STS:1; /* Start Status bit */
\r
1123 vuint32_t CTBASE:5; /* Channel Transfer Base */
\r
1124 vuint32_t PBASE:10; /* Parameter Buffer Base Address */
\r
1125 vuint32_t PWIDTH:1; /* Parameter Width */
\r
1126 vuint32_t PARAM0:7; /* Channel Parameter 0 */
\r
1128 vuint32_t PARAM1:7; /* Channel Parameter 1 */
\r
1132 uint32_t etpu_reserved1;
\r
1134 union { /* MISC Compare Register */
\r
1138 union { /* SCM off-range Date Register */
\r
1142 union { /* ETPU_A Configuration Register */
\r
1145 vuint32_t FEND:1; /* Force END */
\r
1146 vuint32_t MDIS:1; /* Low power Stop */
\r
1148 vuint32_t STF:1; /* Stop Flag */
\r
1150 vuint32_t HLTF:1; /* Halt Mode Flag */
\r
1152 vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */
\r
1155 vuint32_t ETB:5; /* Entry Table Base */
\r
1159 union { /* ETPU_B Configuration Register */
\r
1162 vuint32_t FEND:1; /* Force END */
\r
1163 vuint32_t MDIS:1; /* Low power Stop */
\r
1165 vuint32_t STF:1; /* Stop Flag */
\r
1167 vuint32_t HLTF:1; /* Halt Mode Flag */
\r
1169 vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */
\r
1172 vuint32_t ETB:5; /* Entry Table Base */
\r
1176 uint32_t etpu_reserved4;
\r
1178 union { /* ETPU_A Timebase Configuration Register */
\r
1181 uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
\r
1182 uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
\r
1184 uint32_t AM:1; /* Angle Mode */
\r
1186 uint32_t TCR2P:6; /* TCR2 Prescaler Control */
\r
1187 uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
\r
1189 uint32_t TCR1P:8; /* TCR1 Prescaler Control */
\r
1193 union { /* ETPU_A TCR1 Visibility Register */
\r
1197 union { /* ETPU_A TCR2 Visibility Register */
\r
1201 union { /* ETPU_A STAC Configuration Register */
\r
1204 vuint32_t REN1:1; /* Resource Enable TCR1 */
\r
1205 vuint32_t RSC1:1; /* Resource Control TCR1 */
\r
1207 vuint32_t SERVER_ID1:4;
\r
1209 vuint32_t SRV1:4; /* Resource Server Slot */
\r
1210 vuint32_t REN2:1; /* Resource Enable TCR2 */
\r
1211 vuint32_t RSC2:1; /* Resource Control TCR2 */
\r
1213 vuint32_t SERVER_ID2:4;
\r
1215 vuint32_t SRV2:4; /* Resource Server Slot */
\r
1219 uint32_t etpu_reserved5[4];
\r
1221 union { /* ETPU_B Timebase Configuration Register */
\r
1224 uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
\r
1225 uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
\r
1227 uint32_t AM:1; /* Angle Mode */
\r
1229 uint32_t TCR2P:6; /* TCR2 Prescaler Control */
\r
1230 uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
\r
1232 uint32_t TCR1P:8; /* TCR1 Prescaler Control */
\r
1236 union { /* ETPU_B TCR1 Visibility Register */
\r
1240 union { /* ETPU_B TCR2 Visibility Register */
\r
1244 union { /* ETPU_B STAC Configuration Register */
\r
1247 vuint32_t REN1:1; /* Resource Enable TCR1 */
\r
1248 vuint32_t RSC1:1; /* Resource Control TCR1 */
\r
1250 vuint32_t SERVER_ID1:4;
\r
1252 vuint32_t SRV1:4; /* Resource Server Slot */
\r
1253 vuint32_t REN2:1; /* Resource Enable TCR2 */
\r
1254 vuint32_t RSC2:1; /* Resource Control TCR2 */
\r
1256 vuint32_t SERVER_ID2:4;
\r
1258 vuint32_t SRV2:4; /* Resource Server Slot */
\r
1262 uint32_t etpu_reserved7[108];
\r
1264 /*****************************Status and Control Registers**************************/
\r
1266 union { /* ETPU_A Channel Interrut Status */
\r
1269 vuint32_t CIS31:1; /* Channel 31 Interrut Status */
\r
1270 vuint32_t CIS30:1; /* Channel 30 Interrut Status */
\r
1271 vuint32_t CIS29:1; /* Channel 29 Interrut Status */
\r
1272 vuint32_t CIS28:1; /* Channel 28 Interrut Status */
\r
1273 vuint32_t CIS27:1; /* Channel 27 Interrut Status */
\r
1274 vuint32_t CIS26:1; /* Channel 26 Interrut Status */
\r
1275 vuint32_t CIS25:1; /* Channel 25 Interrut Status */
\r
1276 vuint32_t CIS24:1; /* Channel 24 Interrut Status */
\r
1277 vuint32_t CIS23:1; /* Channel 23 Interrut Status */
\r
1278 vuint32_t CIS22:1; /* Channel 22 Interrut Status */
\r
1279 vuint32_t CIS21:1; /* Channel 21 Interrut Status */
\r
1280 vuint32_t CIS20:1; /* Channel 20 Interrut Status */
\r
1281 vuint32_t CIS19:1; /* Channel 19 Interrut Status */
\r
1282 vuint32_t CIS18:1; /* Channel 18 Interrut Status */
\r
1283 vuint32_t CIS17:1; /* Channel 17 Interrut Status */
\r
1284 vuint32_t CIS16:1; /* Channel 16 Interrut Status */
\r
1285 vuint32_t CIS15:1; /* Channel 15 Interrut Status */
\r
1286 vuint32_t CIS14:1; /* Channel 14 Interrut Status */
\r
1287 vuint32_t CIS13:1; /* Channel 13 Interrut Status */
\r
1288 vuint32_t CIS12:1; /* Channel 12 Interrut Status */
\r
1289 vuint32_t CIS11:1; /* Channel 11 Interrut Status */
\r
1290 vuint32_t CIS10:1; /* Channel 10 Interrut Status */
\r
1291 vuint32_t CIS9:1; /* Channel 9 Interrut Status */
\r
1292 vuint32_t CIS8:1; /* Channel 8 Interrut Status */
\r
1293 vuint32_t CIS7:1; /* Channel 7 Interrut Status */
\r
1294 vuint32_t CIS6:1; /* Channel 6 Interrut Status */
\r
1295 vuint32_t CIS5:1; /* Channel 5 Interrut Status */
\r
1296 vuint32_t CIS4:1; /* Channel 4 Interrut Status */
\r
1297 vuint32_t CIS3:1; /* Channel 3 Interrut Status */
\r
1298 vuint32_t CIS2:1; /* Channel 2 Interrut Status */
\r
1299 vuint32_t CIS1:1; /* Channel 1 Interrut Status */
\r
1300 vuint32_t CIS0:1; /* Channel 0 Interrut Status */
\r
1304 union { /* ETPU_B Channel Interruput Status */
\r
1307 vuint32_t CIS31:1; /* Channel 31 Interrut Status */
\r
1308 vuint32_t CIS30:1; /* Channel 30 Interrut Status */
\r
1309 vuint32_t CIS29:1; /* Channel 29 Interrut Status */
\r
1310 vuint32_t CIS28:1; /* Channel 28 Interrut Status */
\r
1311 vuint32_t CIS27:1; /* Channel 27 Interrut Status */
\r
1312 vuint32_t CIS26:1; /* Channel 26 Interrut Status */
\r
1313 vuint32_t CIS25:1; /* Channel 25 Interrut Status */
\r
1314 vuint32_t CIS24:1; /* Channel 24 Interrut Status */
\r
1315 vuint32_t CIS23:1; /* Channel 23 Interrut Status */
\r
1316 vuint32_t CIS22:1; /* Channel 22 Interrut Status */
\r
1317 vuint32_t CIS21:1; /* Channel 21 Interrut Status */
\r
1318 vuint32_t CIS20:1; /* Channel 20 Interrut Status */
\r
1319 vuint32_t CIS19:1; /* Channel 19 Interrut Status */
\r
1320 vuint32_t CIS18:1; /* Channel 18 Interrut Status */
\r
1321 vuint32_t CIS17:1; /* Channel 17 Interrut Status */
\r
1322 vuint32_t CIS16:1; /* Channel 16 Interrut Status */
\r
1323 vuint32_t CIS15:1; /* Channel 15 Interrut Status */
\r
1324 vuint32_t CIS14:1; /* Channel 14 Interrut Status */
\r
1325 vuint32_t CIS13:1; /* Channel 13 Interrut Status */
\r
1326 vuint32_t CIS12:1; /* Channel 12 Interrut Status */
\r
1327 vuint32_t CIS11:1; /* Channel 11 Interrut Status */
\r
1328 vuint32_t CIS10:1; /* Channel 10 Interrut Status */
\r
1329 vuint32_t CIS9:1; /* Channel 9 Interrut Status */
\r
1330 vuint32_t CIS8:1; /* Channel 8 Interrut Status */
\r
1331 vuint32_t CIS7:1; /* Channel 7 Interrut Status */
\r
1332 vuint32_t CIS6:1; /* Channel 6 Interrut Status */
\r
1333 vuint32_t CIS5:1; /* Channel 5 Interrut Status */
\r
1334 vuint32_t CIS4:1; /* Channel 4 Interrut Status */
\r
1335 vuint32_t CIS3:1; /* Channel 3 Interrut Status */
\r
1336 vuint32_t CIS2:1; /* Channel 2 Interrut Status */
\r
1337 vuint32_t CIS1:1; /* Channel 1 Interrupt Status */
\r
1338 vuint32_t CIS0:1; /* Channel 0 Interrupt Status */
\r
1342 uint32_t etpu_reserved9[2];
\r
1344 union { /* ETPU_A Data Transfer Request Status */
\r
1347 vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
\r
1348 vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
\r
1349 vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
\r
1350 vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
\r
1351 vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
\r
1352 vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
\r
1353 vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
\r
1354 vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
\r
1355 vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
\r
1356 vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
\r
1357 vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
\r
1358 vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
\r
1359 vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
\r
1360 vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
\r
1361 vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
\r
1362 vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
\r
1363 vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
\r
1364 vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
\r
1365 vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
\r
1366 vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
\r
1367 vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
\r
1368 vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
\r
1369 vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
\r
1370 vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
\r
1371 vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
\r
1372 vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
\r
1373 vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
\r
1374 vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
\r
1375 vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
\r
1376 vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
\r
1377 vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
\r
1378 vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
\r
1382 union { /* ETPU_B Data Transfer Request Status */
\r
1385 vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
\r
1386 vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
\r
1387 vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
\r
1388 vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
\r
1389 vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
\r
1390 vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
\r
1391 vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
\r
1392 vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
\r
1393 vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
\r
1394 vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
\r
1395 vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
\r
1396 vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
\r
1397 vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
\r
1398 vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
\r
1399 vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
\r
1400 vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
\r
1401 vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
\r
1402 vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
\r
1403 vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
\r
1404 vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
\r
1405 vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
\r
1406 vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
\r
1407 vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
\r
1408 vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
\r
1409 vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
\r
1410 vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
\r
1411 vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
\r
1412 vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
\r
1413 vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
\r
1414 vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
\r
1415 vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
\r
1416 vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
\r
1420 uint32_t etpu_reserved11[2];
\r
1422 union { /* ETPU_A Interruput Overflow Status */
\r
1425 vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
\r
1426 vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
\r
1427 vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
\r
1428 vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
\r
1429 vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
\r
1430 vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
\r
1431 vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
\r
1432 vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
\r
1433 vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
\r
1434 vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
\r
1435 vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
\r
1436 vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
\r
1437 vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
\r
1438 vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
\r
1439 vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
\r
1440 vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
\r
1441 vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
\r
1442 vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
\r
1443 vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
\r
1444 vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
\r
1445 vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
\r
1446 vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
\r
1447 vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
\r
1448 vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
\r
1449 vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
\r
1450 vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
\r
1451 vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
\r
1452 vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
\r
1453 vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
\r
1454 vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
\r
1455 vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
\r
1456 vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
\r
1460 union { /* ETPU_B Interruput Overflow Status */
\r
1463 vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
\r
1464 vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
\r
1465 vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
\r
1466 vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
\r
1467 vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
\r
1468 vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
\r
1469 vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
\r
1470 vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
\r
1471 vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
\r
1472 vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
\r
1473 vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
\r
1474 vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
\r
1475 vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
\r
1476 vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
\r
1477 vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
\r
1478 vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
\r
1479 vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
\r
1480 vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
\r
1481 vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
\r
1482 vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
\r
1483 vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
\r
1484 vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
\r
1485 vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
\r
1486 vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
\r
1487 vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
\r
1488 vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
\r
1489 vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
\r
1490 vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
\r
1491 vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
\r
1492 vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
\r
1493 vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
\r
1494 vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
\r
1498 uint32_t etpu_reserved13[2];
\r
1500 union { /* ETPU_A Data Transfer Overflow Status */
\r
1503 vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
\r
1504 vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
\r
1505 vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
\r
1506 vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
\r
1507 vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
\r
1508 vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
\r
1509 vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
\r
1510 vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
\r
1511 vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
\r
1512 vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
\r
1513 vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
\r
1514 vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
\r
1515 vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
\r
1516 vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
\r
1517 vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
\r
1518 vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
\r
1519 vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
\r
1520 vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
\r
1521 vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
\r
1522 vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
\r
1523 vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
\r
1524 vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
\r
1525 vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
\r
1526 vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
\r
1527 vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
\r
1528 vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
\r
1529 vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
\r
1530 vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
\r
1531 vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
\r
1532 vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
\r
1533 vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
\r
1534 vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
\r
1538 union { /* ETPU_B Data Transfer Overflow Status */
\r
1541 vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
\r
1542 vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
\r
1543 vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
\r
1544 vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
\r
1545 vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
\r
1546 vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
\r
1547 vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
\r
1548 vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
\r
1549 vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
\r
1550 vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
\r
1551 vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
\r
1552 vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
\r
1553 vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
\r
1554 vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
\r
1555 vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
\r
1556 vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
\r
1557 vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
\r
1558 vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
\r
1559 vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
\r
1560 vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
\r
1561 vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
\r
1562 vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
\r
1563 vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
\r
1564 vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
\r
1565 vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
\r
1566 vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
\r
1567 vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
\r
1568 vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
\r
1569 vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
\r
1570 vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
\r
1571 vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
\r
1572 vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
\r
1576 uint32_t etpu_reserved15[2];
\r
1578 union { /* ETPU_A Channel Interruput Enable */
\r
1581 vuint32_t CIE31:1; /* Channel 31 Interruput Enable */
\r
1582 vuint32_t CIE30:1; /* Channel 30 Interruput Enable */
\r
1583 vuint32_t CIE29:1; /* Channel 29 Interruput Enable */
\r
1584 vuint32_t CIE28:1; /* Channel 28 Interruput Enable */
\r
1585 vuint32_t CIE27:1; /* Channel 27 Interruput Enable */
\r
1586 vuint32_t CIE26:1; /* Channel 26 Interruput Enable */
\r
1587 vuint32_t CIE25:1; /* Channel 25 Interruput Enable */
\r
1588 vuint32_t CIE24:1; /* Channel 24 Interruput Enable */
\r
1589 vuint32_t CIE23:1; /* Channel 23 Interruput Enable */
\r
1590 vuint32_t CIE22:1; /* Channel 22 Interruput Enable */
\r
1591 vuint32_t CIE21:1; /* Channel 21 Interruput Enable */
\r
1592 vuint32_t CIE20:1; /* Channel 20 Interruput Enable */
\r
1593 vuint32_t CIE19:1; /* Channel 19 Interruput Enable */
\r
1594 vuint32_t CIE18:1; /* Channel 18 Interruput Enable */
\r
1595 vuint32_t CIE17:1; /* Channel 17 Interruput Enable */
\r
1596 vuint32_t CIE16:1; /* Channel 16 Interruput Enable */
\r
1597 vuint32_t CIE15:1; /* Channel 15 Interruput Enable */
\r
1598 vuint32_t CIE14:1; /* Channel 14 Interruput Enable */
\r
1599 vuint32_t CIE13:1; /* Channel 13 Interruput Enable */
\r
1600 vuint32_t CIE12:1; /* Channel 12 Interruput Enable */
\r
1601 vuint32_t CIE11:1; /* Channel 11 Interruput Enable */
\r
1602 vuint32_t CIE10:1; /* Channel 10 Interruput Enable */
\r
1603 vuint32_t CIE9:1; /* Channel 9 Interruput Enable */
\r
1604 vuint32_t CIE8:1; /* Channel 8 Interruput Enable */
\r
1605 vuint32_t CIE7:1; /* Channel 7 Interruput Enable */
\r
1606 vuint32_t CIE6:1; /* Channel 6 Interruput Enable */
\r
1607 vuint32_t CIE5:1; /* Channel 5 Interruput Enable */
\r
1608 vuint32_t CIE4:1; /* Channel 4 Interruput Enable */
\r
1609 vuint32_t CIE3:1; /* Channel 3 Interruput Enable */
\r
1610 vuint32_t CIE2:1; /* Channel 2 Interruput Enable */
\r
1611 vuint32_t CIE1:1; /* Channel 1 Interruput Enable */
\r
1612 vuint32_t CIE0:1; /* Channel 0 Interruput Enable */
\r
1616 union { /* ETPU_B Channel Interruput Enable */
\r
1619 vuint32_t CIE31:1; /* Channel 31 Interruput Enable */
\r
1620 vuint32_t CIE30:1; /* Channel 30 Interruput Enable */
\r
1621 vuint32_t CIE29:1; /* Channel 29 Interruput Enable */
\r
1622 vuint32_t CIE28:1; /* Channel 28 Interruput Enable */
\r
1623 vuint32_t CIE27:1; /* Channel 27 Interruput Enable */
\r
1624 vuint32_t CIE26:1; /* Channel 26 Interruput Enable */
\r
1625 vuint32_t CIE25:1; /* Channel 25 Interruput Enable */
\r
1626 vuint32_t CIE24:1; /* Channel 24 Interruput Enable */
\r
1627 vuint32_t CIE23:1; /* Channel 23 Interruput Enable */
\r
1628 vuint32_t CIE22:1; /* Channel 22 Interruput Enable */
\r
1629 vuint32_t CIE21:1; /* Channel 21 Interruput Enable */
\r
1630 vuint32_t CIE20:1; /* Channel 20 Interruput Enable */
\r
1631 vuint32_t CIE19:1; /* Channel 19 Interruput Enable */
\r
1632 vuint32_t CIE18:1; /* Channel 18 Interruput Enable */
\r
1633 vuint32_t CIE17:1; /* Channel 17 Interruput Enable */
\r
1634 vuint32_t CIE16:1; /* Channel 16 Interruput Enable */
\r
1635 vuint32_t CIE15:1; /* Channel 15 Interruput Enable */
\r
1636 vuint32_t CIE14:1; /* Channel 14 Interruput Enable */
\r
1637 vuint32_t CIE13:1; /* Channel 13 Interruput Enable */
\r
1638 vuint32_t CIE12:1; /* Channel 12 Interruput Enable */
\r
1639 vuint32_t CIE11:1; /* Channel 11 Interruput Enable */
\r
1640 vuint32_t CIE10:1; /* Channel 10 Interruput Enable */
\r
1641 vuint32_t CIE9:1; /* Channel 9 Interruput Enable */
\r
1642 vuint32_t CIE8:1; /* Channel 8 Interruput Enable */
\r
1643 vuint32_t CIE7:1; /* Channel 7 Interruput Enable */
\r
1644 vuint32_t CIE6:1; /* Channel 6 Interruput Enable */
\r
1645 vuint32_t CIE5:1; /* Channel 5 Interruput Enable */
\r
1646 vuint32_t CIE4:1; /* Channel 4 Interruput Enable */
\r
1647 vuint32_t CIE3:1; /* Channel 3 Interruput Enable */
\r
1648 vuint32_t CIE2:1; /* Channel 2 Interruput Enable */
\r
1649 vuint32_t CIE1:1; /* Channel 1 Interruput Enable */
\r
1650 vuint32_t CIE0:1; /* Channel 0 Interruput Enable */
\r
1654 uint32_t etpu_reserved17[2];
\r
1656 union { /* ETPU_A Channel Data Transfer Request Enable */
\r
1659 vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
\r
1660 vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
\r
1661 vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
\r
1662 vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
\r
1663 vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
\r
1664 vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
\r
1665 vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
\r
1666 vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
\r
1667 vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
\r
1668 vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
\r
1669 vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
\r
1670 vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
\r
1671 vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
\r
1672 vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
\r
1673 vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
\r
1674 vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
\r
1675 vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
\r
1676 vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
\r
1677 vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
\r
1678 vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
\r
1679 vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
\r
1680 vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
\r
1681 vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
\r
1682 vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
\r
1683 vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
\r
1684 vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
\r
1685 vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
\r
1686 vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
\r
1687 vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
\r
1688 vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
\r
1689 vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
\r
1690 vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
\r
1694 union { /* ETPU_B Channel Data Transfer Request Enable */
\r
1697 vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
\r
1698 vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
\r
1699 vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
\r
1700 vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
\r
1701 vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
\r
1702 vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
\r
1703 vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
\r
1704 vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
\r
1705 vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
\r
1706 vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
\r
1707 vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
\r
1708 vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
\r
1709 vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
\r
1710 vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
\r
1711 vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
\r
1712 vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
\r
1713 vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
\r
1714 vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
\r
1715 vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
\r
1716 vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
\r
1717 vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
\r
1718 vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
\r
1719 vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
\r
1720 vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
\r
1721 vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
\r
1722 vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
\r
1723 vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
\r
1724 vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
\r
1725 vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
\r
1726 vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
\r
1727 vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
\r
1728 vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
\r
1732 uint32_t etpu_reserved20[10];
\r
1733 union { /* ETPU_A Channel Pending Service Status */
\r
1736 vuint32_t SR31:1; /* Channel 31 Pending Service Status */
\r
1737 vuint32_t SR30:1; /* Channel 30 Pending Service Status */
\r
1738 vuint32_t SR29:1; /* Channel 29 Pending Service Status */
\r
1739 vuint32_t SR28:1; /* Channel 28 Pending Service Status */
\r
1740 vuint32_t SR27:1; /* Channel 27 Pending Service Status */
\r
1741 vuint32_t SR26:1; /* Channel 26 Pending Service Status */
\r
1742 vuint32_t SR25:1; /* Channel 25 Pending Service Status */
\r
1743 vuint32_t SR24:1; /* Channel 24 Pending Service Status */
\r
1744 vuint32_t SR23:1; /* Channel 23 Pending Service Status */
\r
1745 vuint32_t SR22:1; /* Channel 22 Pending Service Status */
\r
1746 vuint32_t SR21:1; /* Channel 21 Pending Service Status */
\r
1747 vuint32_t SR20:1; /* Channel 20 Pending Service Status */
\r
1748 vuint32_t SR19:1; /* Channel 19 Pending Service Status */
\r
1749 vuint32_t SR18:1; /* Channel 18 Pending Service Status */
\r
1750 vuint32_t SR17:1; /* Channel 17 Pending Service Status */
\r
1751 vuint32_t SR16:1; /* Channel 16 Pending Service Status */
\r
1752 vuint32_t SR15:1; /* Channel 15 Pending Service Status */
\r
1753 vuint32_t SR14:1; /* Channel 14 Pending Service Status */
\r
1754 vuint32_t SR13:1; /* Channel 13 Pending Service Status */
\r
1755 vuint32_t SR12:1; /* Channel 12 Pending Service Status */
\r
1756 vuint32_t SR11:1; /* Channel 11 Pending Service Status */
\r
1757 vuint32_t SR10:1; /* Channel 10 Pending Service Status */
\r
1758 vuint32_t SR9:1; /* Channel 9 Pending Service Status */
\r
1759 vuint32_t SR8:1; /* Channel 8 Pending Service Status */
\r
1760 vuint32_t SR7:1; /* Channel 7 Pending Service Status */
\r
1761 vuint32_t SR6:1; /* Channel 6 Pending Service Status */
\r
1762 vuint32_t SR5:1; /* Channel 5 Pending Service Status */
\r
1763 vuint32_t SR4:1; /* Channel 4 Pending Service Status */
\r
1764 vuint32_t SR3:1; /* Channel 3 Pending Service Status */
\r
1765 vuint32_t SR2:1; /* Channel 2 Pending Service Status */
\r
1766 vuint32_t SR1:1; /* Channel 1 Pending Service Status */
\r
1767 vuint32_t SR0:1; /* Channel 0 Pending Service Status */
\r
1771 union { /* ETPU_B Channel Pending Service Status */
\r
1774 vuint32_t SR31:1; /* Channel 31 Pending Service Status */
\r
1775 vuint32_t SR30:1; /* Channel 30 Pending Service Status */
\r
1776 vuint32_t SR29:1; /* Channel 29 Pending Service Status */
\r
1777 vuint32_t SR28:1; /* Channel 28 Pending Service Status */
\r
1778 vuint32_t SR27:1; /* Channel 27 Pending Service Status */
\r
1779 vuint32_t SR26:1; /* Channel 26 Pending Service Status */
\r
1780 vuint32_t SR25:1; /* Channel 25 Pending Service Status */
\r
1781 vuint32_t SR24:1; /* Channel 24 Pending Service Status */
\r
1782 vuint32_t SR23:1; /* Channel 23 Pending Service Status */
\r
1783 vuint32_t SR22:1; /* Channel 22 Pending Service Status */
\r
1784 vuint32_t SR21:1; /* Channel 21 Pending Service Status */
\r
1785 vuint32_t SR20:1; /* Channel 20 Pending Service Status */
\r
1786 vuint32_t SR19:1; /* Channel 19 Pending Service Status */
\r
1787 vuint32_t SR18:1; /* Channel 18 Pending Service Status */
\r
1788 vuint32_t SR17:1; /* Channel 17 Pending Service Status */
\r
1789 vuint32_t SR16:1; /* Channel 16 Pending Service Status */
\r
1790 vuint32_t SR15:1; /* Channel 15 Pending Service Status */
\r
1791 vuint32_t SR14:1; /* Channel 14 Pending Service Status */
\r
1792 vuint32_t SR13:1; /* Channel 13 Pending Service Status */
\r
1793 vuint32_t SR12:1; /* Channel 12 Pending Service Status */
\r
1794 vuint32_t SR11:1; /* Channel 11 Pending Service Status */
\r
1795 vuint32_t SR10:1; /* Channel 10 Pending Service Status */
\r
1796 vuint32_t SR9:1; /* Channel 9 Pending Service Status */
\r
1797 vuint32_t SR8:1; /* Channel 8 Pending Service Status */
\r
1798 vuint32_t SR7:1; /* Channel 7 Pending Service Status */
\r
1799 vuint32_t SR6:1; /* Channel 6 Pending Service Status */
\r
1800 vuint32_t SR5:1; /* Channel 5 Pending Service Status */
\r
1801 vuint32_t SR4:1; /* Channel 4 Pending Service Status */
\r
1802 vuint32_t SR3:1; /* Channel 3 Pending Service Status */
\r
1803 vuint32_t SR2:1; /* Channel 2 Pending Service Status */
\r
1804 vuint32_t SR1:1; /* Channel 1 Pending Service Status */
\r
1805 vuint32_t SR0:1; /* Channel 0 Pending Service Status */
\r
1809 uint32_t etpu_reserved20a[2];
\r
1811 union { /* ETPU_A Channel Service Status */
\r
1814 vuint32_t SS31:1; /* Channel 31 Service Status */
\r
1815 vuint32_t SS30:1; /* Channel 30 Service Status */
\r
1816 vuint32_t SS29:1; /* Channel 29 Service Status */
\r
1817 vuint32_t SS28:1; /* Channel 28 Service Status */
\r
1818 vuint32_t SS27:1; /* Channel 27 Service Status */
\r
1819 vuint32_t SS26:1; /* Channel 26 Service Status */
\r
1820 vuint32_t SS25:1; /* Channel 25 Service Status */
\r
1821 vuint32_t SS24:1; /* Channel 24 Service Status */
\r
1822 vuint32_t SS23:1; /* Channel 23 Service Status */
\r
1823 vuint32_t SS22:1; /* Channel 22 Service Status */
\r
1824 vuint32_t SS21:1; /* Channel 21 Service Status */
\r
1825 vuint32_t SS20:1; /* Channel 20 Service Status */
\r
1826 vuint32_t SS19:1; /* Channel 19 Service Status */
\r
1827 vuint32_t SS18:1; /* Channel 18 Service Status */
\r
1828 vuint32_t SS17:1; /* Channel 17 Service Status */
\r
1829 vuint32_t SS16:1; /* Channel 16 Service Status */
\r
1830 vuint32_t SS15:1; /* Channel 15 Service Status */
\r
1831 vuint32_t SS14:1; /* Channel 14 Service Status */
\r
1832 vuint32_t SS13:1; /* Channel 13 Service Status */
\r
1833 vuint32_t SS12:1; /* Channel 12 Service Status */
\r
1834 vuint32_t SS11:1; /* Channel 11 Service Status */
\r
1835 vuint32_t SS10:1; /* Channel 10 Service Status */
\r
1836 vuint32_t SS9:1; /* Channel 9 Service Status */
\r
1837 vuint32_t SS8:1; /* Channel 8 Service Status */
\r
1838 vuint32_t SS7:1; /* Channel 7 Service Status */
\r
1839 vuint32_t SS6:1; /* Channel 6 Service Status */
\r
1840 vuint32_t SS5:1; /* Channel 5 Service Status */
\r
1841 vuint32_t SS4:1; /* Channel 4 Service Status */
\r
1842 vuint32_t SS3:1; /* Channel 3 Service Status */
\r
1843 vuint32_t SS2:1; /* Channel 2 Service Status */
\r
1844 vuint32_t SS1:1; /* Channel 1 Service Status */
\r
1845 vuint32_t SS0:1; /* Channel 0 Service Status */
\r
1849 union { /* ETPU_B Channel Service Status */
\r
1852 vuint32_t SS31:1; /* Channel 31 Service Status */
\r
1853 vuint32_t SS30:1; /* Channel 30 Service Status */
\r
1854 vuint32_t SS29:1; /* Channel 29 Service Status */
\r
1855 vuint32_t SS28:1; /* Channel 28 Service Status */
\r
1856 vuint32_t SS27:1; /* Channel 27 Service Status */
\r
1857 vuint32_t SS26:1; /* Channel 26 Service Status */
\r
1858 vuint32_t SS25:1; /* Channel 25 Service Status */
\r
1859 vuint32_t SS24:1; /* Channel 24 Service Status */
\r
1860 vuint32_t SS23:1; /* Channel 23 Service Status */
\r
1861 vuint32_t SS22:1; /* Channel 22 Service Status */
\r
1862 vuint32_t SS21:1; /* Channel 21 Service Status */
\r
1863 vuint32_t SS20:1; /* Channel 20 Service Status */
\r
1864 vuint32_t SS19:1; /* Channel 19 Service Status */
\r
1865 vuint32_t SS18:1; /* Channel 18 Service Status */
\r
1866 vuint32_t SS17:1; /* Channel 17 Service Status */
\r
1867 vuint32_t SS16:1; /* Channel 16 Service Status */
\r
1868 vuint32_t SS15:1; /* Channel 15 Service Status */
\r
1869 vuint32_t SS14:1; /* Channel 14 Service Status */
\r
1870 vuint32_t SS13:1; /* Channel 13 Service Status */
\r
1871 vuint32_t SS12:1; /* Channel 12 Service Status */
\r
1872 vuint32_t SS11:1; /* Channel 11 Service Status */
\r
1873 vuint32_t SS10:1; /* Channel 10 Service Status */
\r
1874 vuint32_t SS9:1; /* Channel 9 Service Status */
\r
1875 vuint32_t SS8:1; /* Channel 8 Service Status */
\r
1876 vuint32_t SS7:1; /* Channel 7 Service Status */
\r
1877 vuint32_t SS6:1; /* Channel 6 Service Status */
\r
1878 vuint32_t SS5:1; /* Channel 5 Service Status */
\r
1879 vuint32_t SS4:1; /* Channel 4 Service Status */
\r
1880 vuint32_t SS3:1; /* Channel 3 Service Status */
\r
1881 vuint32_t SS2:1; /* Channel 2 Service Status */
\r
1882 vuint32_t SS1:1; /* Channel 1 Service Status */
\r
1883 vuint32_t SS0:1; /* Channel 0 Service Status */
\r
1887 uint32_t etpu_reserved23[90];
\r
1889 /*****************************Channels********************************/
\r
1893 vuint32_t R; /* Channel Configuration Register */
\r
1895 vuint32_t CIE:1; /* Channel Interruput Enable */
\r
1896 vuint32_t DTRE:1; /* Data Transfer Request Enable */
\r
1897 vuint32_t CPR:2; /* Channel Priority */
\r
1899 vuint32_t ETCS:1; /* Entry Table Condition Select */
\r
1901 vuint32_t CFS:5; /* Channel Function Select */
\r
1902 vuint32_t ODIS:1; /* Output disable */
\r
1903 vuint32_t OPOL:1; /* output polarity */
\r
1905 vuint32_t CPBA:11; /* Channel Parameter Base Address */
\r
1909 vuint32_t R; /* Channel Status Control Register */
\r
1911 vuint32_t CIS:1; /* Channel Interruput Status */
\r
1912 vuint32_t CIOS:1; /* Channel Interruput Overflow Status */
\r
1914 vuint32_t DTRS:1; /* Data Transfer Status */
\r
1915 vuint32_t DTROS:1; /* Data Transfer Overflow Status */
\r
1917 vuint32_t IPS:1; /* Input Pin State */
\r
1918 vuint32_t OPS:1; /* Output Pin State */
\r
1919 vuint32_t OBE:1; /* Output Buffer Enable */
\r
1921 vuint32_t FM1:1; /* Function mode */
\r
1922 vuint32_t FM0:1; /* Function mode */
\r
1926 vuint32_t R; /* Channel Host Service Request Register */
\r
1928 vuint32_t:29; /* Host Service Request */
\r
1932 uint32_t etpu_reserved23;
\r
1936 /****************************************************************************/
\r
1937 /* MODULE : XBAR CrossBar */
\r
1938 /****************************************************************************/
\r
1954 vuint32_t MSTR2:3;
\r
1956 vuint32_t MSTR1:3;
\r
1958 vuint32_t MSTR0:3;
\r
1960 } MPR0; /* Master Priority Register for Slave Port 0 */
\r
1962 uint32_t xbar_reserved1[3];
\r
1975 } SGPCR0; /* General Purpose Control Register for Slave Port 0 */
\r
1977 uint32_t xbar_reserved2[59];
\r
1993 vuint32_t MSTR2:3;
\r
1995 vuint32_t MSTR1:3;
\r
1997 vuint32_t MSTR0:3;
\r
1999 } MPR1; /* Master Priority Register for Slave Port 1 */
\r
2001 uint32_t xbar_reserved3[3];
\r
2014 } SGPCR1; /* General Purpose Control Register for Slave Port 1 */
\r
2016 uint32_t xbar_reserved4[123];
\r
2032 vuint32_t MSTR2:3;
\r
2034 vuint32_t MSTR1:3;
\r
2036 vuint32_t MSTR0:3;
\r
2038 } MPR3; /* Master Priority Register for Slave Port 3 */
\r
2040 uint32_t xbar_reserved5[3];
\r
2053 } SGPCR3; /* General Purpose Control Register for Slave Port 3 */
\r
2054 uint32_t xbar_reserved6[187];
\r
2070 vuint32_t MSTR2:3;
\r
2072 vuint32_t MSTR1:3;
\r
2074 vuint32_t MSTR0:3;
\r
2076 } MPR6; /* Master Priority Register for Slave Port 6 */
\r
2078 uint32_t xbar_reserved7[3];
\r
2091 } SGPCR6; /* General Purpose Control Register for Slave Port 6 */
\r
2093 uint32_t xbar_reserved8[59];
\r
2109 vuint32_t MSTR2:3;
\r
2111 vuint32_t MSTR1:3;
\r
2113 vuint32_t MSTR0:3;
\r
2115 } MPR7; /* Master Priority Register for Slave Port 7 */
\r
2117 uint32_t xbar_reserved9[3];
\r
2130 } SGPCR7; /* General Purpose Control Register for Slave Port 7 */
\r
2133 /****************************************************************************/
\r
2134 /* MODULE : ECSM */
\r
2135 /****************************************************************************/
\r
2138 uint32_t ecsm_reserved1[5];
\r
2140 uint16_t ecsm_reserved2;
\r
2144 } SWTCR; //Software Watchdog Timer Control
\r
2146 uint8_t ecsm_reserved3[3];
\r
2150 } SWTSR; //SWT Service Register
\r
2152 uint8_t ecsm_reserved4[3];
\r
2156 } SWTIR; //SWT Interrupt Register
\r
2158 uint32_t ecsm_reserved5a[1];
\r
2159 uint32_t ecsm_reserved5b[1];
\r
2161 uint32_t ecsm_reserved5c[6];
\r
2163 uint8_t ecsm_reserved6[3];
\r
2172 } ECR; //ECC Configuration Register
\r
2174 uint8_t mcm_reserved8[3];
\r
2183 } ESR; //ECC Status Register
\r
2185 uint16_t ecsm_reserved9;
\r
2191 vuint16_t FRCNCI:1;
\r
2192 vuint16_t FR1NCI:1;
\r
2194 vuint16_t ERRBIT:7;
\r
2196 } EEGR; //ECC Error Generation Register
\r
2198 uint32_t ecsm_reserved10;
\r
2203 vuint32_t FEAR:32;
\r
2205 } FEAR; //Flash ECC Address Register
\r
2207 uint16_t ecsm_reserved11;
\r
2215 } FEMR; //Flash ECC Master Register
\r
2227 } FEAT; //Flash ECC Attributes Register
\r
2232 vuint32_t FEDH:32;
\r
2234 } FEDRH; //Flash ECC Data High Register
\r
2239 vuint32_t FEDL:32;
\r
2241 } FEDRL; //Flash ECC Data Low Register
\r
2246 vuint32_t REAR:32;
\r
2248 } REAR; //RAM ECC Address
\r
2250 uint8_t ecsm_reserved12[2];
\r
2258 } REMR; //RAM ECC Master
\r
2270 } REAT; // RAM ECC Attributes Register
\r
2275 vuint32_t REDH:32;
\r
2277 } REDRH; //RAM ECC Data High Register
\r
2282 vuint32_t REDL:32;
\r
2284 } REDRL; //RAMECC Data Low Register
\r
2287 /****************************************************************************/
\r
2288 /* MODULE : eDMA */
\r
2289 /****************************************************************************/
\r
2295 vuint32_t GRP3PRI:2;
\r
2296 vuint32_t GRP2PRI:2;
\r
2297 vuint32_t GRP1PRI:2;
\r
2298 vuint32_t GRP0PRI:2;
\r
2305 } CR; /* Control Register */
\r
2313 vuint32_t ERRCHN:6;
\r
2323 } ESR; /* Error Status Register */
\r
2328 vuint32_t ERQ63:1;
\r
2329 vuint32_t ERQ62:1;
\r
2330 vuint32_t ERQ61:1;
\r
2331 vuint32_t ERQ60:1;
\r
2332 vuint32_t ERQ59:1;
\r
2333 vuint32_t ERQ58:1;
\r
2334 vuint32_t ERQ57:1;
\r
2335 vuint32_t ERQ56:1;
\r
2336 vuint32_t ERQ55:1;
\r
2337 vuint32_t ERQ54:1;
\r
2338 vuint32_t ERQ53:1;
\r
2339 vuint32_t ERQ52:1;
\r
2340 vuint32_t ERQ51:1;
\r
2341 vuint32_t ERQ50:1;
\r
2342 vuint32_t ERQ49:1;
\r
2343 vuint32_t ERQ48:1;
\r
2344 vuint32_t ERQ47:1;
\r
2345 vuint32_t ERQ46:1;
\r
2346 vuint32_t ERQ45:1;
\r
2347 vuint32_t ERQ44:1;
\r
2348 vuint32_t ERQ43:1;
\r
2349 vuint32_t ERQ42:1;
\r
2350 vuint32_t ERQ41:1;
\r
2351 vuint32_t ERQ40:1;
\r
2352 vuint32_t ERQ39:1;
\r
2353 vuint32_t ERQ38:1;
\r
2354 vuint32_t ERQ37:1;
\r
2355 vuint32_t ERQ36:1;
\r
2356 vuint32_t ERQ35:1;
\r
2357 vuint32_t ERQ34:1;
\r
2358 vuint32_t ERQ33:1;
\r
2359 vuint32_t ERQ32:1;
\r
2361 } ERQRH; /* DMA Enable Request Register High */
\r
2366 vuint32_t ERQ31:1;
\r
2367 vuint32_t ERQ30:1;
\r
2368 vuint32_t ERQ29:1;
\r
2369 vuint32_t ERQ28:1;
\r
2370 vuint32_t ERQ27:1;
\r
2371 vuint32_t ERQ26:1;
\r
2372 vuint32_t ERQ25:1;
\r
2373 vuint32_t ERQ24:1;
\r
2374 vuint32_t ERQ23:1;
\r
2375 vuint32_t ERQ22:1;
\r
2376 vuint32_t ERQ21:1;
\r
2377 vuint32_t ERQ20:1;
\r
2378 vuint32_t ERQ19:1;
\r
2379 vuint32_t ERQ18:1;
\r
2380 vuint32_t ERQ17:1;
\r
2381 vuint32_t ERQ16:1;
\r
2382 vuint32_t ERQ15:1;
\r
2383 vuint32_t ERQ14:1;
\r
2384 vuint32_t ERQ13:1;
\r
2385 vuint32_t ERQ12:1;
\r
2386 vuint32_t ERQ11:1;
\r
2387 vuint32_t ERQ10:1;
\r
2388 vuint32_t ERQ09:1;
\r
2389 vuint32_t ERQ08:1;
\r
2390 vuint32_t ERQ07:1;
\r
2391 vuint32_t ERQ06:1;
\r
2392 vuint32_t ERQ05:1;
\r
2393 vuint32_t ERQ04:1;
\r
2394 vuint32_t ERQ03:1;
\r
2395 vuint32_t ERQ02:1;
\r
2396 vuint32_t ERQ01:1;
\r
2397 vuint32_t ERQ00:1;
\r
2399 } ERQRL; /* DMA Enable Request Register Low */
\r
2404 vuint32_t EEI63:1;
\r
2405 vuint32_t EEI62:1;
\r
2406 vuint32_t EEI61:1;
\r
2407 vuint32_t EEI60:1;
\r
2408 vuint32_t EEI59:1;
\r
2409 vuint32_t EEI58:1;
\r
2410 vuint32_t EEI57:1;
\r
2411 vuint32_t EEI56:1;
\r
2412 vuint32_t EEI55:1;
\r
2413 vuint32_t EEI54:1;
\r
2414 vuint32_t EEI53:1;
\r
2415 vuint32_t EEI52:1;
\r
2416 vuint32_t EEI51:1;
\r
2417 vuint32_t EEI50:1;
\r
2418 vuint32_t EEI49:1;
\r
2419 vuint32_t EEI48:1;
\r
2420 vuint32_t EEI47:1;
\r
2421 vuint32_t EEI46:1;
\r
2422 vuint32_t EEI45:1;
\r
2423 vuint32_t EEI44:1;
\r
2424 vuint32_t EEI43:1;
\r
2425 vuint32_t EEI42:1;
\r
2426 vuint32_t EEI41:1;
\r
2427 vuint32_t EEI40:1;
\r
2428 vuint32_t EEI39:1;
\r
2429 vuint32_t EEI38:1;
\r
2430 vuint32_t EEI37:1;
\r
2431 vuint32_t EEI36:1;
\r
2432 vuint32_t EEI35:1;
\r
2433 vuint32_t EEI34:1;
\r
2434 vuint32_t EEI33:1;
\r
2435 vuint32_t EEI32:1;
\r
2437 } EEIRH; /* DMA Enable Error Interrupt Register High */
\r
2442 vuint32_t EEI31:1;
\r
2443 vuint32_t EEI30:1;
\r
2444 vuint32_t EEI29:1;
\r
2445 vuint32_t EEI28:1;
\r
2446 vuint32_t EEI27:1;
\r
2447 vuint32_t EEI26:1;
\r
2448 vuint32_t EEI25:1;
\r
2449 vuint32_t EEI24:1;
\r
2450 vuint32_t EEI23:1;
\r
2451 vuint32_t EEI22:1;
\r
2452 vuint32_t EEI21:1;
\r
2453 vuint32_t EEI20:1;
\r
2454 vuint32_t EEI19:1;
\r
2455 vuint32_t EEI18:1;
\r
2456 vuint32_t EEI17:1;
\r
2457 vuint32_t EEI16:1;
\r
2458 vuint32_t EEI15:1;
\r
2459 vuint32_t EEI14:1;
\r
2460 vuint32_t EEI13:1;
\r
2461 vuint32_t EEI12:1;
\r
2462 vuint32_t EEI11:1;
\r
2463 vuint32_t EEI10:1;
\r
2464 vuint32_t EEI09:1;
\r
2465 vuint32_t EEI08:1;
\r
2466 vuint32_t EEI07:1;
\r
2467 vuint32_t EEI06:1;
\r
2468 vuint32_t EEI05:1;
\r
2469 vuint32_t EEI04:1;
\r
2470 vuint32_t EEI03:1;
\r
2471 vuint32_t EEI02:1;
\r
2472 vuint32_t EEI01:1;
\r
2473 vuint32_t EEI00:1;
\r
2475 } EEIRL; /* DMA Enable Error Interrupt Register Low */
\r
2479 } SERQR; /* DMA Set Enable Request Register */
\r
2483 } CERQR; /* DMA Clear Enable Request Register */
\r
2487 } SEEIR; /* DMA Set Enable Error Interrupt Register */
\r
2491 } CEEIR; /* DMA Clear Enable Error Interrupt Register */
\r
2495 } CIRQR; /* DMA Clear Interrupt Request Register */
\r
2499 } CER; /* DMA Clear error Register */
\r
2503 } SSBR; /* Set Start Bit Register */
\r
2507 } CDSBR; /* Clear Done Status Bit Register */
\r
2512 vuint32_t INT63:1;
\r
2513 vuint32_t INT62:1;
\r
2514 vuint32_t INT61:1;
\r
2515 vuint32_t INT60:1;
\r
2516 vuint32_t INT59:1;
\r
2517 vuint32_t INT58:1;
\r
2518 vuint32_t INT57:1;
\r
2519 vuint32_t INT56:1;
\r
2520 vuint32_t INT55:1;
\r
2521 vuint32_t INT54:1;
\r
2522 vuint32_t INT53:1;
\r
2523 vuint32_t INT52:1;
\r
2524 vuint32_t INT51:1;
\r
2525 vuint32_t INT50:1;
\r
2526 vuint32_t INT49:1;
\r
2527 vuint32_t INT48:1;
\r
2528 vuint32_t INT47:1;
\r
2529 vuint32_t INT46:1;
\r
2530 vuint32_t INT45:1;
\r
2531 vuint32_t INT44:1;
\r
2532 vuint32_t INT43:1;
\r
2533 vuint32_t INT42:1;
\r
2534 vuint32_t INT41:1;
\r
2535 vuint32_t INT40:1;
\r
2536 vuint32_t INT39:1;
\r
2537 vuint32_t INT38:1;
\r
2538 vuint32_t INT37:1;
\r
2539 vuint32_t INT36:1;
\r
2540 vuint32_t INT35:1;
\r
2541 vuint32_t INT34:1;
\r
2542 vuint32_t INT33:1;
\r
2543 vuint32_t INT32:1;
\r
2545 } IRQRH; /* DMA Interrupt Request High */
\r
2550 vuint32_t INT31:1;
\r
2551 vuint32_t INT30:1;
\r
2552 vuint32_t INT29:1;
\r
2553 vuint32_t INT28:1;
\r
2554 vuint32_t INT27:1;
\r
2555 vuint32_t INT26:1;
\r
2556 vuint32_t INT25:1;
\r
2557 vuint32_t INT24:1;
\r
2558 vuint32_t INT23:1;
\r
2559 vuint32_t INT22:1;
\r
2560 vuint32_t INT21:1;
\r
2561 vuint32_t INT20:1;
\r
2562 vuint32_t INT19:1;
\r
2563 vuint32_t INT18:1;
\r
2564 vuint32_t INT17:1;
\r
2565 vuint32_t INT16:1;
\r
2566 vuint32_t INT15:1;
\r
2567 vuint32_t INT14:1;
\r
2568 vuint32_t INT13:1;
\r
2569 vuint32_t INT12:1;
\r
2570 vuint32_t INT11:1;
\r
2571 vuint32_t INT10:1;
\r
2572 vuint32_t INT09:1;
\r
2573 vuint32_t INT08:1;
\r
2574 vuint32_t INT07:1;
\r
2575 vuint32_t INT06:1;
\r
2576 vuint32_t INT05:1;
\r
2577 vuint32_t INT04:1;
\r
2578 vuint32_t INT03:1;
\r
2579 vuint32_t INT02:1;
\r
2580 vuint32_t INT01:1;
\r
2581 vuint32_t INT00:1;
\r
2583 } IRQRL; /* DMA Interrupt Request Low */
\r
2588 vuint32_t ERR63:1;
\r
2589 vuint32_t ERR62:1;
\r
2590 vuint32_t ERR61:1;
\r
2591 vuint32_t ERR60:1;
\r
2592 vuint32_t ERR59:1;
\r
2593 vuint32_t ERR58:1;
\r
2594 vuint32_t ERR57:1;
\r
2595 vuint32_t ERR56:1;
\r
2596 vuint32_t ERR55:1;
\r
2597 vuint32_t ERR54:1;
\r
2598 vuint32_t ERR53:1;
\r
2599 vuint32_t ERR52:1;
\r
2600 vuint32_t ERR51:1;
\r
2601 vuint32_t ERR50:1;
\r
2602 vuint32_t ERR49:1;
\r
2603 vuint32_t ERR48:1;
\r
2604 vuint32_t ERR47:1;
\r
2605 vuint32_t ERR46:1;
\r
2606 vuint32_t ERR45:1;
\r
2607 vuint32_t ERR44:1;
\r
2608 vuint32_t ERR43:1;
\r
2609 vuint32_t ERR42:1;
\r
2610 vuint32_t ERR41:1;
\r
2611 vuint32_t ERR40:1;
\r
2612 vuint32_t ERR39:1;
\r
2613 vuint32_t ERR38:1;
\r
2614 vuint32_t ERR37:1;
\r
2615 vuint32_t ERR36:1;
\r
2616 vuint32_t ERR35:1;
\r
2617 vuint32_t ERR34:1;
\r
2618 vuint32_t ERR33:1;
\r
2619 vuint32_t ERR32:1;
\r
2621 } ERH; /* DMA Error High */
\r
2626 vuint32_t ERR31:1;
\r
2627 vuint32_t ERR30:1;
\r
2628 vuint32_t ERR29:1;
\r
2629 vuint32_t ERR28:1;
\r
2630 vuint32_t ERR27:1;
\r
2631 vuint32_t ERR26:1;
\r
2632 vuint32_t ERR25:1;
\r
2633 vuint32_t ERR24:1;
\r
2634 vuint32_t ERR23:1;
\r
2635 vuint32_t ERR22:1;
\r
2636 vuint32_t ERR21:1;
\r
2637 vuint32_t ERR20:1;
\r
2638 vuint32_t ERR19:1;
\r
2639 vuint32_t ERR18:1;
\r
2640 vuint32_t ERR17:1;
\r
2641 vuint32_t ERR16:1;
\r
2642 vuint32_t ERR15:1;
\r
2643 vuint32_t ERR14:1;
\r
2644 vuint32_t ERR13:1;
\r
2645 vuint32_t ERR12:1;
\r
2646 vuint32_t ERR11:1;
\r
2647 vuint32_t ERR10:1;
\r
2648 vuint32_t ERR09:1;
\r
2649 vuint32_t ERR08:1;
\r
2650 vuint32_t ERR07:1;
\r
2651 vuint32_t ERR06:1;
\r
2652 vuint32_t ERR05:1;
\r
2653 vuint32_t ERR04:1;
\r
2654 vuint32_t ERR03:1;
\r
2655 vuint32_t ERR02:1;
\r
2656 vuint32_t ERR01:1;
\r
2657 vuint32_t ERR00:1;
\r
2659 } ERL; /* DMA Error Low */
\r
2660 uint32_t edma_reserved1[52];
\r
2668 vuint8_t GRPPRI:2;
\r
2672 } CPR[64]; /* Channel n Priority */
\r
2674 uint32_t edma_reserved2[944];
\r
2676 /****************************************************************************/
\r
2677 /* DMA2 Transfer Control Descriptor */
\r
2678 /****************************************************************************/
\r
2680 struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */
\r
2681 vuint32_t SADDR; /* source address */
\r
2683 vuint16_t SMOD:5; /* source address modulo */
\r
2684 vuint16_t SSIZE:3; /* source transfer size */
\r
2685 vuint16_t DMOD:5; /* destination address modulo */
\r
2686 vuint16_t DSIZE:3; /* destination transfer size */
\r
2687 vint16_t SOFF; /* signed source address offset */
\r
2689 vuint32_t NBYTES; /* inner (
\93minor
\94) byte count */
\r
2691 vint32_t SLAST; /* last destination address adjustment, or
\r
2693 scatter/gather address (if e_sg = 1) */
\r
2694 vuint32_t DADDR; /* destination address */
\r
2696 vuint16_t CITERE_LINK:1;
\r
2697 vuint16_t CITER:15;
\r
2699 vint16_t DOFF; /* signed destination address offset */
\r
2701 vint32_t DLAST_SGA;
\r
2703 vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */
\r
2704 vuint16_t BITER:15;
\r
2706 vuint16_t BWC:2; /* bandwidth control */
\r
2707 vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */
\r
2708 vuint16_t DONE:1; /* channel done */
\r
2709 vuint16_t ACTIVE:1; /* channel active */
\r
2710 vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */
\r
2711 vuint16_t E_SG:1; /* enable scatter/gather descriptor */
\r
2712 vuint16_t D_REQ:1; /* disable ipd_req when done */
\r
2713 vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
\r
2714 vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
\r
2715 vuint16_t START:1; /* explicit channel start */
\r
2716 } TCD[64]; /* transfer_control_descriptor */
\r
2720 struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */
\r
2722 struct tcd_alt1_t {
\r
2723 vuint32_t SADDR; /* source address */
\r
2725 vuint16_t SMOD:5; /* source address modulo */
\r
2726 vuint16_t SSIZE:3; /* source transfer size */
\r
2727 vuint16_t DMOD:5; /* destination address modulo */
\r
2728 vuint16_t DSIZE:3; /* destination transfer size */
\r
2729 vint16_t SOFF; /* signed source address offset */
\r
2731 vuint32_t NBYTES; /* inner (
\93minor
\94) byte count */
\r
2733 vint32_t SLAST; /* last destination address adjustment, or
\r
2735 scatter/gather address (if e_sg = 1) */
\r
2736 vuint32_t DADDR; /* destination address */
\r
2738 vuint16_t CITERE_LINK:1;
\r
2739 vuint16_t CITERLINKCH:6;
\r
2740 vuint16_t CITER:9;
\r
2742 vint16_t DOFF; /* signed destination address offset */
\r
2744 vint32_t DLAST_SGA;
\r
2746 vuint16_t BITERE_LINK:1; /* beginning (
\93major
\94) iteration count */
\r
2747 vuint16_t BITERLINKCH:6;
\r
2748 vuint16_t BITER:9;
\r
2750 vuint16_t BWC:2; /* bandwidth control */
\r
2751 vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */
\r
2752 vuint16_t DONE:1; /* channel done */
\r
2753 vuint16_t ACTIVE:1; /* channel active */
\r
2754 vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */
\r
2755 vuint16_t E_SG:1; /* enable scatter/gather descriptor */
\r
2756 vuint16_t D_REQ:1; /* disable ipd_req when done */
\r
2757 vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
\r
2758 vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
\r
2759 vuint16_t START:1; /* explicit channel start */
\r
2760 } TCD[64]; /* transfer_control_descriptor */
\r
2762 /****************************************************************************/
\r
2763 /* MODULE : INTC */
\r
2764 /****************************************************************************/
\r
2774 } MCR; /* Module Configuration Register */
\r
2776 int32_t INTC_reserved00;
\r
2784 } CPR; /* Current Priority Register */
\r
2786 uint32_t intc_reserved1;
\r
2791 vuint32_t VTBA:21;
\r
2792 vuint32_t INTVEC:9;
\r
2795 } IACKR; /* Interrupt Acknowledge Register */
\r
2797 uint32_t intc_reserved2;
\r
2804 } EOIR; /* End of Interrupt Register */
\r
2806 uint32_t intc_reserved3;
\r
2815 } SSCIR[8]; /* Software Set/Clear Interruput Register */
\r
2817 uint32_t intc_reserved4[6];
\r
2825 } PSR[358]; /* Software Set/Clear Interrupt Register */
\r
2828 /****************************************************************************/
\r
2829 /* MODULE : EQADC */
\r
2830 /****************************************************************************/
\r
2831 struct EQADC_tag {
\r
2836 vuint32_t ESSIE:2;
\r
2840 } MCR; /* Module Configuration Register */
\r
2842 int32_t EQADC_reserved00;
\r
2850 } NMSFR; /* Null Message Send Format Register */
\r
2858 } ETDFR; /* External Trigger Digital Filter Register */
\r
2863 vuint32_t CFPUSH:32;
\r
2865 } CFPR[6]; /* CFIFO Push Registers */
\r
2867 uint32_t eqadc_reserved1;
\r
2869 uint32_t eqadc_reserved2;
\r
2875 vuint32_t RFPOP:16;
\r
2877 } RFPR[6]; /* Result FIFO Pop Registers */
\r
2879 uint32_t eqadc_reserved3;
\r
2881 uint32_t eqadc_reserved4;
\r
2888 vuint16_t CFINV:1;
\r
2893 } CFCR[6]; /* CFIFO Control Registers */
\r
2895 uint32_t eqadc_reserved5;
\r
2901 vuint16_t TORIE:1;
\r
2903 vuint16_t EOQIE:1;
\r
2904 vuint16_t CFUIE:1;
\r
2909 vuint16_t RFOIE:1;
\r
2914 } IDCR[6]; /* Interrupt and DMA Control Registers */
\r
2916 uint32_t eqadc_reserved6;
\r
2933 vuint32_t CFCTR:4;
\r
2934 vuint32_t TNXTPTR:4;
\r
2935 vuint32_t RFCTR:4;
\r
2936 vuint32_t POPNXTPTR:4;
\r
2938 } FISR[6]; /* FIFO and Interrupt Status Registers */
\r
2940 uint32_t eqadc_reserved7;
\r
2942 uint32_t eqadc_reserved8;
\r
2948 vuint16_t TCCF:11;
\r
2950 } CFTCR[6]; /* CFIFO Transfer Counter Registers */
\r
2952 uint32_t eqadc_reserved9;
\r
2964 vuint32_t LCFTCB0:4;
\r
2965 vuint32_t TC_LCFTCB0:11;
\r
2967 } CFSSR0; /* CFIFO Status Register 0 */
\r
2979 vuint32_t LCFTCB1:4;
\r
2980 vuint32_t TC_LCFTCB1:11;
\r
2982 } CFSSR1; /* CFIFO Status Register 1 */
\r
2994 vuint32_t ECBNI:1;
\r
2995 vuint32_t LCFTSSI:4;
\r
2996 vuint32_t TC_LCFTSSI:11;
\r
2998 } CFSSR2; /* CFIFO Status Register 2 */
\r
3013 uint32_t eqadc_reserved11;
\r
3023 } SSICR; /* SSI Control Register */
\r
3030 vuint32_t RDATA:26;
\r
3032 } SSIRDR; /* SSI Recieve Data Register */
\r
3034 uint32_t eqadc_reserved12[17];
\r
3044 uint32_t eqadc_reserved13[12];
\r
3048 uint32_t eqadc_reserved14[32];
\r
3058 uint32_t eqadc_reserved15[12];
\r
3063 /****************************************************************************/
\r
3064 /* MODULE : DSPI */
\r
3065 /****************************************************************************/
\r
3071 vuint32_t CONT_SCKE:1;
\r
3072 vuint32_t DCONF:2;
\r
3075 vuint32_t PCSSE:1;
\r
3078 vuint32_t PCSIS5:1;
\r
3079 vuint32_t PCSIS4:1;
\r
3080 vuint32_t PCSIS3:1;
\r
3081 vuint32_t PCSIS2:1;
\r
3082 vuint32_t PCSIS1:1;
\r
3083 vuint32_t PCSIS0:1;
\r
3086 vuint32_t DIS_TXF:1;
\r
3087 vuint32_t DIS_RXF:1;
\r
3088 vuint32_t CLR_TXF:1;
\r
3089 vuint32_t CLR_RXF:1;
\r
3090 vuint32_t SMPL_PT:2;
\r
3094 } MCR; /* Module Configuration Register */
\r
3096 uint32_t dspi_reserved1;
\r
3101 vuint32_t TCNT:16;
\r
3113 vuint32_t LSBFE:1;
\r
3114 vuint32_t PCSSCK:2;
\r
3118 vuint32_t CSSCK:4;
\r
3123 } CTAR[8]; /* Clock and Transfer Attributes Registers */
\r
3129 vuint32_t TXRXS:1;
\r
3140 vuint32_t TXCTR:4;
\r
3141 vuint32_t TXNXTPTR:4;
\r
3142 vuint32_t RXCTR:4;
\r
3143 vuint32_t POPNXTPTR:4;
\r
3145 } SR; /* Status Register */
\r
3150 vuint32_t TCFRE:1;
\r
3152 vuint32_t EOQFRE:1;
\r
3153 vuint32_t TFUFRE:1;
\r
3155 vuint32_t TFFFRE:1;
\r
3156 vuint32_t TFFFDIRS:1;
\r
3158 vuint32_t RFOFRE:1;
\r
3160 vuint32_t RFDFRE:1;
\r
3161 vuint32_t RFDFDIRS:1;
\r
3164 } RSER; /* DMA/Interrupt Request Select and Enable Register */
\r
3172 vuint32_t CTCNT:1;
\r
3180 vuint32_t TXDATA:16;
\r
3182 } PUSHR; /* PUSH TX FIFO Register */
\r
3188 vuint32_t RXDATA:16;
\r
3190 } POPR; /* POP RX FIFO Register */
\r
3195 vuint32_t TXCMD:16;
\r
3196 vuint32_t TXDATA:16;
\r
3198 } TXFR[4]; /* Transmit FIFO Registers */
\r
3200 vuint32_t DSPI_reserved_txf[12];
\r
3206 vuint32_t RXDATA:16;
\r
3208 } RXFR[4]; /* Transmit FIFO Registers */
\r
3210 vuint32_t DSPI_reserved_rxf[12];
\r
3217 vuint32_t MTOCNT:6;
\r
3223 vuint32_t DCONT:1;
\r
3224 vuint32_t DSICTAS:3;
\r
3226 vuint32_t DPCS5:1;
\r
3227 vuint32_t DPCS4:1;
\r
3228 vuint32_t DPCS3:1;
\r
3229 vuint32_t DPCS2:1;
\r
3230 vuint32_t DPCS1:1;
\r
3231 vuint32_t DPCS0:1;
\r
3233 } DSICR; /* DSI Configuration Register */
\r
3239 vuint32_t SER_DATA:16;
\r
3241 } SDR; /* DSI Serialization Data Register */
\r
3247 vuint32_t ASER_DATA:16;
\r
3249 } ASDR; /* DSI Alternate Serialization Data Register */
\r
3255 vuint32_t COMP_DATA:16;
\r
3257 } COMPR; /* DSI Transmit Comparison Register */
\r
3263 vuint32_t DESER_DATA:16;
\r
3265 } DDR; /* DSI deserialization Data Register */
\r
3268 /****************************************************************************/
\r
3269 /* MODULE : eSCI */
\r
3270 /****************************************************************************/
\r
3277 vuint32_t LOOPS:1;
\r
3278 vuint32_t SCISDOZ:1;
\r
3294 } CR1; /* Control Register 1 */
\r
3302 vuint16_t IEBERR:1;
\r
3303 vuint16_t RXDMA:1;
\r
3304 vuint16_t TXDMA:1;
\r
3305 vuint16_t BRK13:1;
\r
3307 vuint16_t BESM13:1;
\r
3308 vuint16_t SBSTP:1;
\r
3315 } CR2; /* Control Register 2 */
\r
3325 } DR; /* Data Register */
\r
3342 vuint32_t RXRDY:1;
\r
3343 vuint32_t TXRDY:1;
\r
3344 vuint32_t LWAKE:1;
\r
3346 vuint32_t PBERR:1;
\r
3348 vuint32_t CKERR:1;
\r
3353 } SR; /* Status Register */
\r
3378 } LCR; /* LIN Control Register */
\r
3382 } LTR; /* LIN Transmit Register */
\r
3386 } LRR; /* LIN Recieve Register */
\r
3390 } LPR; /* LIN CRC Polynom Register */
\r
3393 /****************************************************************************/
\r
3394 /* MODULE : FlexCAN */
\r
3395 /****************************************************************************/
\r
3396 struct FLEXCAN2_tag {
\r
3404 vuint32_t NOTRDY:1;
\r
3406 vuint32_t SOFTRST:1;
\r
3407 vuint32_t FRZACK:1;
\r
3413 vuint32_t MDISACK:1;
\r
3419 vuint32_t MAXMB:6;
\r
3421 } MCR; /* Module Configuration Register */
\r
3426 vuint32_t PRESDIV:8;
\r
3428 vuint32_t PSEG1:3;
\r
3429 vuint32_t PSEG2:3;
\r
3430 vuint32_t BOFFMSK:1;
\r
3431 vuint32_t ERRMSK:1;
\r
3432 vuint32_t CLKSRC:1;
\r
3438 vuint32_t BOFFREC:1;
\r
3442 vuint32_t PROPSEG:3;
\r
3444 } CR; /* Control Register */
\r
3448 } TIMER; /* Free Running Timer */
\r
3449 int32_t FLEXCAN_reserved00;
\r
3457 } RXGMASK; /* RX Global Mask */
\r
3465 } RX14MASK; /* RX 14 Mask */
\r
3473 } RX15MASK; /* RX 15 Mask */
\r
3479 vuint32_t RXECNT:8;
\r
3480 vuint32_t TXECNT:8;
\r
3482 } ECR; /* Error Counter Register */
\r
3491 vuint32_t BIT1ERR:1;
\r
3492 vuint32_t BIT0ERR:1;
\r
3493 vuint32_t ACKERR:1;
\r
3494 vuint32_t CRCERR:1;
\r
3495 vuint32_t FRMERR:1;
\r
3496 vuint32_t STFERR:1;
\r
3497 vuint32_t TXWRN:1;
\r
3498 vuint32_t RXWRN:1;
\r
3501 vuint32_t FLTCONF:2;
\r
3503 vuint32_t BOFFINT:1;
\r
3504 vuint32_t ERRINT:1;
\r
3507 } ESR; /* Error and Status Register */
\r
3512 vuint32_t BUF63M:1;
\r
3513 vuint32_t BUF62M:1;
\r
3514 vuint32_t BUF61M:1;
\r
3515 vuint32_t BUF60M:1;
\r
3516 vuint32_t BUF59M:1;
\r
3517 vuint32_t BUF58M:1;
\r
3518 vuint32_t BUF57M:1;
\r
3519 vuint32_t BUF56M:1;
\r
3520 vuint32_t BUF55M:1;
\r
3521 vuint32_t BUF54M:1;
\r
3522 vuint32_t BUF53M:1;
\r
3523 vuint32_t BUF52M:1;
\r
3524 vuint32_t BUF51M:1;
\r
3525 vuint32_t BUF50M:1;
\r
3526 vuint32_t BUF49M:1;
\r
3527 vuint32_t BUF48M:1;
\r
3528 vuint32_t BUF47M:1;
\r
3529 vuint32_t BUF46M:1;
\r
3530 vuint32_t BUF45M:1;
\r
3531 vuint32_t BUF44M:1;
\r
3532 vuint32_t BUF43M:1;
\r
3533 vuint32_t BUF42M:1;
\r
3534 vuint32_t BUF41M:1;
\r
3535 vuint32_t BUF40M:1;
\r
3536 vuint32_t BUF39M:1;
\r
3537 vuint32_t BUF38M:1;
\r
3538 vuint32_t BUF37M:1;
\r
3539 vuint32_t BUF36M:1;
\r
3540 vuint32_t BUF35M:1;
\r
3541 vuint32_t BUF34M:1;
\r
3542 vuint32_t BUF33M:1;
\r
3543 vuint32_t BUF32M:1;
\r
3545 } IMRH; /* Interruput Masks Register */
\r
3550 vuint32_t BUF31M:1;
\r
3551 vuint32_t BUF30M:1;
\r
3552 vuint32_t BUF29M:1;
\r
3553 vuint32_t BUF28M:1;
\r
3554 vuint32_t BUF27M:1;
\r
3555 vuint32_t BUF26M:1;
\r
3556 vuint32_t BUF25M:1;
\r
3557 vuint32_t BUF24M:1;
\r
3558 vuint32_t BUF23M:1;
\r
3559 vuint32_t BUF22M:1;
\r
3560 vuint32_t BUF21M:1;
\r
3561 vuint32_t BUF20M:1;
\r
3562 vuint32_t BUF19M:1;
\r
3563 vuint32_t BUF18M:1;
\r
3564 vuint32_t BUF17M:1;
\r
3565 vuint32_t BUF16M:1;
\r
3566 vuint32_t BUF15M:1;
\r
3567 vuint32_t BUF14M:1;
\r
3568 vuint32_t BUF13M:1;
\r
3569 vuint32_t BUF12M:1;
\r
3570 vuint32_t BUF11M:1;
\r
3571 vuint32_t BUF10M:1;
\r
3572 vuint32_t BUF09M:1;
\r
3573 vuint32_t BUF08M:1;
\r
3574 vuint32_t BUF07M:1;
\r
3575 vuint32_t BUF06M:1;
\r
3576 vuint32_t BUF05M:1;
\r
3577 vuint32_t BUF04M:1;
\r
3578 vuint32_t BUF03M:1;
\r
3579 vuint32_t BUF02M:1;
\r
3580 vuint32_t BUF01M:1;
\r
3581 vuint32_t BUF00M:1;
\r
3583 } IMRL; /* Interruput Masks Register */
\r
3588 vuint32_t BUF63I:1;
\r
3589 vuint32_t BUF62I:1;
\r
3590 vuint32_t BUF61I:1;
\r
3591 vuint32_t BUF60I:1;
\r
3592 vuint32_t BUF59I:1;
\r
3593 vuint32_t BUF58I:1;
\r
3594 vuint32_t BUF57I:1;
\r
3595 vuint32_t BUF56I:1;
\r
3596 vuint32_t BUF55I:1;
\r
3597 vuint32_t BUF54I:1;
\r
3598 vuint32_t BUF53I:1;
\r
3599 vuint32_t BUF52I:1;
\r
3600 vuint32_t BUF51I:1;
\r
3601 vuint32_t BUF50I:1;
\r
3602 vuint32_t BUF49I:1;
\r
3603 vuint32_t BUF48I:1;
\r
3604 vuint32_t BUF47I:1;
\r
3605 vuint32_t BUF46I:1;
\r
3606 vuint32_t BUF45I:1;
\r
3607 vuint32_t BUF44I:1;
\r
3608 vuint32_t BUF43I:1;
\r
3609 vuint32_t BUF42I:1;
\r
3610 vuint32_t BUF41I:1;
\r
3611 vuint32_t BUF40I:1;
\r
3612 vuint32_t BUF39I:1;
\r
3613 vuint32_t BUF38I:1;
\r
3614 vuint32_t BUF37I:1;
\r
3615 vuint32_t BUF36I:1;
\r
3616 vuint32_t BUF35I:1;
\r
3617 vuint32_t BUF34I:1;
\r
3618 vuint32_t BUF33I:1;
\r
3619 vuint32_t BUF32I:1;
\r
3621 } IFRH; /* Interruput Flag Register */
\r
3626 vuint32_t BUF31I:1;
\r
3627 vuint32_t BUF30I:1;
\r
3628 vuint32_t BUF29I:1;
\r
3629 vuint32_t BUF28I:1;
\r
3630 vuint32_t BUF27I:1;
\r
3631 vuint32_t BUF26I:1;
\r
3632 vuint32_t BUF25I:1;
\r
3633 vuint32_t BUF24I:1;
\r
3634 vuint32_t BUF23I:1;
\r
3635 vuint32_t BUF22I:1;
\r
3636 vuint32_t BUF21I:1;
\r
3637 vuint32_t BUF20I:1;
\r
3638 vuint32_t BUF19I:1;
\r
3639 vuint32_t BUF18I:1;
\r
3640 vuint32_t BUF17I:1;
\r
3641 vuint32_t BUF16I:1;
\r
3642 vuint32_t BUF15I:1;
\r
3643 vuint32_t BUF14I:1;
\r
3644 vuint32_t BUF13I:1;
\r
3645 vuint32_t BUF12I:1;
\r
3646 vuint32_t BUF11I:1;
\r
3647 vuint32_t BUF10I:1;
\r
3648 vuint32_t BUF09I:1;
\r
3649 vuint32_t BUF08I:1;
\r
3650 vuint32_t BUF07I:1;
\r
3651 vuint32_t BUF06I:1;
\r
3652 vuint32_t BUF05I:1;
\r
3653 vuint32_t BUF04I:1;
\r
3654 vuint32_t BUF03I:1;
\r
3655 vuint32_t BUF02I:1;
\r
3656 vuint32_t BUF01I:1;
\r
3657 vuint32_t BUF00I:1;
\r
3659 } IFRL; /* Interruput Flag Register */
\r
3661 uint32_t flexcan2_reserved2[19];
\r
3673 vuint32_t LENGTH:4;
\r
3674 vuint32_t TIMESTAMP:16;
\r
3682 vuint32_t STD_ID:11;
\r
3683 vuint32_t EXT_ID:18;
\r
3688 vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
\r
3689 vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
\r
3690 vuint32_t W[2]; /* Data buffer in words (32 bits) */
\r
3691 vuint32_t R[2]; /* Data buffer in words (32 bits) */
\r
3697 /* Define memories */
\r
3700 #define SRAM_START 0x40000000
\r
3701 #define SRAM_SIZE 0x10000
\r
3702 #define SRAM_END 0x4000FFFF
\r
3704 #define FLASH_START 0x0
\r
3705 #define FLASH_SIZE 0x200000
\r
3706 #define FLASH_END 0x1FFFFF
\r
3709 /* Define instances of modules */
\r
3710 #define PBRIDGE_A (*( struct PBRIDGE_A_tag *) 0xC3F00000)
\r
3711 #define FMPLL (*( struct FMPLL_tag *) 0xC3F80000)
\r
3712 #define EBI (*( struct EBI_tag *) 0xC3F84000)
\r
3713 #define FLASH (*( struct FLASH_tag *) 0xC3F88000)
\r
3714 #define SIU (*( struct SIU_tag *) 0xC3F90000)
\r
3716 #define EMIOS (*( struct EMIOS_tag *) 0xC3FA0000)
\r
3717 #define ETPU (*( struct ETPU_tag *) 0xC3FC0000)
\r
3718 #define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)
\r
3719 #define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)
\r
3720 #define ETPU_DATA_RAM_END 0xC3FC8BFC
\r
3721 #define CODE_RAM (*( uint32_t *) 0xC3FD0000)
\r
3722 #define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)
\r
3724 #define PBRIDGE_B (*( struct PBRIDGE_B_tag *) 0xFFF00000)
\r
3725 #define XBAR (*( struct XBAR_tag *) 0xFFF04000)
\r
3726 #define ECSM (*( struct ECSM_tag *) 0xFFF40000)
\r
3727 #define EDMA (*( struct EDMA_tag *) 0xFFF44000)
\r
3728 #define INTC (*( struct INTC_tag *) 0xFFF48000)
\r
3730 #define EQADC (*( struct EQADC_tag *) 0xFFF80000)
\r
3732 #define DSPI_A (*( struct DSPI_tag *) 0xFFF90000)
\r
3733 #define DSPI_B (*( struct DSPI_tag *) 0xFFF94000)
\r
3734 #define DSPI_C (*( struct DSPI_tag *) 0xFFF98000)
\r
3735 #define DSPI_D (*( struct DSPI_tag *) 0xFFF9C000)
\r
3737 #define ESCI_A (*( struct ESCI_tag *) 0xFFFB0000)
\r
3738 #define ESCI_B (*( struct ESCI_tag *) 0xFFFB4000)
\r
3740 #define CAN_A (*( struct FLEXCAN2_tag *) 0xFFFC0000)
\r
3741 #define CAN_B (*( struct FLEXCAN2_tag *) 0xFFFC4000)
\r
3742 #define CAN_C (*( struct FLEXCAN2_tag *) 0xFFFC8000)
\r
3748 #ifdef __cplusplus
\r
3751 #endif /* ifdef _MPC5554_H */
\r
3752 /*********************************************************************
\r
3755 * Freescale Semiconductor, INC. All Rights Reserved.
\r
3756 * You are hereby granted a copyright license to use, modify, and
\r
3757 * distribute the SOFTWARE so long as this entire notice is
\r
3758 * retained without alteration in any modified and/or redistributed
\r
3759 * versions, and that such modified versions are clearly identified
\r
3760 * as such. No licenses are granted by implication, estoppel or
\r
3761 * otherwise under any patents or trademarks of Freescale
\r
3762 * Semiconductor, Inc. This software is provided on an "AS IS"
\r
3763 * basis and without warranty.
\r
3765 * To the maximum extent permitted by applicable law, Freescale
\r
3766 * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
\r
3767 * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
\r
3768 * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
\r
3769 * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
\r
3770 * AND ANY ACCOMPANYING WRITTEN MATERIALS.
\r
3772 * To the maximum extent permitted by applicable law, IN NO EVENT
\r
3773 * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
\r
3774 * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
\r
3775 * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
\r
3776 * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
\r
3778 * Freescale Semiconductor assumes no responsibility for the
\r
3779 * maintenance and support of this software
\r
3781 ********************************************************************/
\r
projects / arc.git / blob