1 /* -------------------------------- Arctic Core ------------------------------
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2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
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4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
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6 * This source code is free software; you can redistribute it and/or modify it
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7 * under the terms of the GNU General Public License version 2 as published by the
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8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
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10 * This program is distributed in the hope that it will be useful, but
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11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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14 * -------------------------------- Arctic Core ------------------------------*/
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17 #include "Std_Types.h"
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23 #define GET_PIN_PORT(_pin) (_pin >> 8)
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24 #define GET_PIN_PIN(_pin) (_pin & 0x1F)
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25 #define GET_PIN_MASK(_pin) (1 << (_pin & 0x1F))
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29 PORT_UNINITIALIZED = 0, PORT_INITIALIZED,
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33 typedef volatile struct
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44 } Port_RegisterType;
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47 #define PORT_NOT_CONFIGURED 0x00000000
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49 #define PORT_0_BASE ((Port_RegisterType *)0xFFF7BC30) // GIO Port A
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50 #define PORT_1_BASE ((Port_RegisterType *)0xFFF7BC50) // GIO Port B
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51 #define PORT_2_BASE ((Port_RegisterType *)0xFFF7B848) // N2HET1 Base
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52 #define PORT_3_BASE ((Port_RegisterType *)0xFFFFF76C) // DMM used as a GIO
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53 #define PORT_4_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)
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54 #define PORT_5_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)
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55 #define PORT_6_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)
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56 #define PORT_7_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)
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57 #define PORT_8_BASE ((Port_RegisterType *)0xFFF7DDE0) // DCAN1 TX IO Control Register
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58 #define PORT_9_BASE ((Port_RegisterType *)0xFFF7DFE0) // DCAN2 TX IO Control Register
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59 #define PORT_10_BASE ((Port_RegisterType *)0xFFF7E1E0) // DCAN3 TX IO Control Register
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60 #define PORT_NUMBER_OF_PORTS 11
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62 static Port_RegisterType * const Port_Base[] =
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77 typedef volatile uint32 PinMuxBase;
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79 #define PINMUX0 ((PinMuxBase *)0xFFFFEB10)
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80 #define PINMUX1 ((PinMuxBase *)0xFFFFEB14)
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81 #define PINMUX2 ((PinMuxBase *)0xFFFFEB18)
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82 #define PINMUX3 ((PinMuxBase *)0xFFFFEB1C)
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83 #define PINMUX4 ((PinMuxBase *)0xFFFFEB20)
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84 #define PINMUX5 ((PinMuxBase *)0xFFFFEB24)
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85 #define PINMUX6 ((PinMuxBase *)0xFFFFEB28)
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86 #define PINMUX7 ((PinMuxBase *)0xFFFFEB2C)
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87 #define PINMUX8 ((PinMuxBase *)0xFFFFEB30)
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88 #define PINMUX9 ((PinMuxBase *)0xFFFFEB34)
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89 #define PINMUX10 ((PinMuxBase *)0xFFFFEB38)
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90 #define PINMUX11 ((PinMuxBase *)0xFFFFEB3C)
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91 #define PINMUX12 ((PinMuxBase *)0xFFFFEB40)
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92 #define PINMUX13 ((PinMuxBase *)0xFFFFEB44)
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93 #define PINMUX14 ((PinMuxBase *)0xFFFFEB48)
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94 #define PINMUX15 ((PinMuxBase *)0xFFFFEB4C)
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95 #define PINMUX16 ((PinMuxBase *)0xFFFFEB50)
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96 #define PINMUX17 ((PinMuxBase *)0xFFFFEB54)
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97 #define PINMUX18 ((PinMuxBase *)0xFFFFEB58)
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98 #define PINMUX19 ((PinMuxBase *)0xFFFFEB5C)
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99 #define PINMUX20 ((PinMuxBase *)0xFFFFEB60)
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100 #define PINMUX21 ((PinMuxBase *)0xFFFFEB64)
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101 #define PINMUX22 ((PinMuxBase *)0xFFFFEB68)
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102 #define PINMUX23 ((PinMuxBase *)0xFFFFEB6C)
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103 #define PINMUX24 ((PinMuxBase *)0xFFFFEB70)
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104 #define PINMUX25 ((PinMuxBase *)0xFFFFEB74)
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105 #define PINMUX26 ((PinMuxBase *)0xFFFFEB78)
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106 #define PINMUX27 ((PinMuxBase *)0xFFFFEB7C)
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107 #define PINMUX28 ((PinMuxBase *)0xFFFFEB80)
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108 #define PINMUX29 ((PinMuxBase *)0xFFFFEB84)
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109 #define PINMUX30 ((PinMuxBase *)0xFFFFEB88)
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111 static PinMuxBase * PinMux_Base[] =
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146 static Port_StateType _portState = PORT_UNINITIALIZED;
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147 static const Port_ConfigType * _configPtr = &PortConfigData;
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149 #if PORT_DEV_ERROR_DETECT == STD_ON
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150 #define VALIDATE_PARAM_CONFIG(_ptr,_api) \
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151 if( (_ptr)==((void *)0) ) { \
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152 Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_PARAM_CONFIG ); \
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156 #define VALIDATE_STATE_INIT(_api)\
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157 if(PORT_INITIALIZED!=_portState){\
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158 Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_UNINIT ); \
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162 #define VALIDATE_PARAM_PIN(_pin, _api)\
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163 if(GET_PIN_PORT(_pin) >= PORT_NUMBER_OF_PORTS || Port_Base[GET_PIN_PORT(_pin)] == PORT_NOT_CONFIGURED || GET_PIN_PIN(_pin) > 7 ){\
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164 Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_PARAM_PIN ); \
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169 #define VALIDATE_PARAM_CONFIG(_ptr,_api)
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170 #define VALIDATE_STATE_INIT(_api)
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171 #define VALIDATE_PARAM_PIN(_pin, _api)
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174 #if PORT_VERSION_INFO_API == STD_ON
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175 static Std_VersionInfoType _Port_VersionInfo =
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177 .vendorID = (uint16)1,
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178 .moduleID = (uint16) MODULE_ID_PORT,
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179 .instanceID = (uint8)1,
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180 .sw_major_version = (uint8)PORT_SW_MAJOR_VERSION,
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181 .sw_minor_version = (uint8)PORT_SW_MINOR_VERSION,
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182 .sw_patch_version = (uint8)PORT_SW_PATCH_VERSION,
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183 .ar_major_version = (uint8)PORT_AR_MAJOR_VERSION,
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184 .ar_minor_version = (uint8)PORT_AR_MINOR_VERSION,
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185 .ar_patch_version = (uint8)PORT_AR_PATCH_VERSION,
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189 void Port_RefreshPin(uint16 pinNumber) {
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190 uint32 port = GET_PIN_PORT(_configPtr->pins[pinNumber].pin);
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191 uint32 mask = GET_PIN_MASK(_configPtr->pins[pinNumber].pin);
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192 uint32 conf = _configPtr->pins[pinNumber].conf;
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194 uint32 pinmux = _configPtr->pins[pinNumber].pinmux;
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195 uint8 pinmuxFunctionNum = _configPtr->pins[pinNumber].pinmuxFunctionNum;
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196 uint8 pinmuxBaseNum = _configPtr->pins[pinNumber].pinmuxBaseNum;
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198 /* Enable Pin Muxing */
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199 kickerReg->KICKER0 = 0x83E70B13;
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200 kickerReg->KICKER1 = 0x95A4F1E0;
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202 /* ex.: Hack to connect N2HET1[27] (function 2) to pin A9 */
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203 *PinMux_Base[pinmuxBaseNum] &= (~(0xFF << pinmux));//
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204 *PinMux_Base[pinmuxBaseNum] |= (~(pinmuxFunctionNum << pinmux));
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206 /* Disable Pin Muxing */
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207 kickerReg->KICKER0 = 0x00000000;
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208 kickerReg->KICKER1 = 0x00000000;
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210 if (conf & PORT_FUNC) {
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211 // Don't do anything, let each driver configure???
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215 // Set pin direction
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216 if (conf & PORT_PIN_OUT) {
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217 Port_Base[port]->DIR |= mask;
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220 if (conf & PORT_ODE_ENABLE) {
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221 Port_Base[port]->PDR |= mask;
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223 Port_Base[port]->PDR &= ~mask;
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227 Port_Base[port]->DIR &= ~mask;
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230 // Set pull up or down or nothing.
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231 if (conf & PORT_PULL_NONE) {
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232 Port_Base[port]->PULDIS |= mask;
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235 Port_Base[port]->PULDIS &= ~mask;
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236 if (conf & PORT_PULL_UP) {
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237 Port_Base[port]->PSL |= mask;
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240 Port_Base[port]->PSL &= ~mask;
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246 void Port_Init(const Port_ConfigType *configType) { // note: HalCoGen: gioInit
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247 VALIDATE_PARAM_CONFIG(configType, PORT_INIT_ID);
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249 _configPtr = (Port_ConfigType *)configType;
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251 /* Bring GIO register out of reset. */
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253 gioREG->INTENACLR = 0xFF; // Interrupt Enable Clear Register
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254 gioREG->LVLCLR = 0xFF; // Interrupt Priority Clear Register
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256 for (uint16 i = 0; i < PORT_NUMBER_OF_PINS; i++) {
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257 Port_RefreshPin(i);
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260 for (uint16 i = 0; i < PORT_NUMBER_OF_PINS; i++) {
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265 _portState = PORT_INITIALIZED;
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270 void Dmm_Init(uint16 pinNumber) {
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272 dmmReg->GLBCTRL= 0x00000605; /* DMM switched ON, set 32 bit length */
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273 //dmmReg->GLBCTRL = 0x5; // don't use DMM_Reset
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275 uint32 port = GET_PIN_PORT(_configPtr->pins[pinNumber].pin);
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276 uint32 mask = GET_PIN_MASK(_configPtr->pins[pinNumber].pin);
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278 Port_Base[port]->FUN |= ~mask; // pin usage: 1 - functional, 0 - GIO
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279 //Port_Base[port]->FUN = 0x00000000;
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280 //Port_Base[port]->DIR = 0x00000001;
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281 Port_Base[port]->DIR = 0x7FFFF; // I/O selection: 0 - input, 1 - output (not necessary but assures that all DMM GIO pins are used as outputs in our example)
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282 Port_Base[port]->PSL &= ~mask; // pull-up/pull-down selection: 0 - pull-down, 1 - pull-up
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285 void Dmm_Reset(const Port_ConfigType *configType) {
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286 VALIDATE_PARAM_CONFIG(configType, PORT_INIT_ID);
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288 _configPtr = (Port_ConfigType *)configType;
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290 uint32 mask = GET_PIN_MASK(_configPtr->pins[0].pin);
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291 dmmReg->GLBCTRL |= mask;
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292 dmmReg->GLBCTRL &= ~mask;
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295 #if ( PORT_SET_PIN_DIRECTION_API == STD_ON )
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296 void Port_SetPinDirection( Port_PinType pin, Port_PinDirectionType direction )
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298 VALIDATE_STATE_INIT(PORT_SET_PIN_DIRECTION_ID);
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299 VALIDATE_PARAM_PIN(pin, PORT_SET_PIN_DIRECTION_ID);
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301 uint8 port = GET_PIN_PORT(pin); // ex.: LED1 - 0x021b >> 8 = 2 (uint8)
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302 uint32 mask = GET_PIN_MASK(pin); // ex.: LED1 - 1 << (0x1b) = 0x08000000 (uint32)
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304 if (direction & PORT_PIN_IN) {
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305 Port_Base[port]->DIR |= mask;
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308 Port_Base[port]->DIR &= ~mask;
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316 void Port_RefreshPortDirection( void )
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318 VALIDATE_STATE_INIT(PORT_REFRESH_PORT_DIRECTION_ID);
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319 for (uint16 i = 0; i < PORT_NUMBER_OF_PINS; i++) {
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320 if (!(_configPtr->pins[i].conf & PORT_DIRECTION_CHANGEABLE)) {
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321 Port_RefreshPin(i);
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328 #if PORT_VERSION_INFO_API == STD_ON
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329 void Port_GetVersionInfo(Std_VersionInfoType* versionInfo)
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331 VALIDATE_STATE_INIT(PORT_GET_VERSION_INFO_ID);
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332 memcpy(versionInfo, &_Port_VersionInfo, sizeof(Std_VersionInfoType));
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337 #if (PORT_SET_PIN_MODE_API == STD_ON)
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338 void Port_SetPinMode(Port_PinType Pin, Port_PinModeType Mode) {
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339 VALIDATE_STATE_INIT(PORT_SET_PIN_MODE_ID);
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340 VALIDATE_PARAM_PIN(Pin, PORT_SET_PIN_MODE_ID);
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342 #if (PORT_DEV_ERROR_DETECT == STD_ON)
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343 Det_ReportError(MODULE_ID_PORT, 0, PORT_SET_PIN_MODE_ID, PORT_E_MODE_UNCHANGEABLE );
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346 uint8 port = GET_PIN_PORT(Pin);
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347 uint8 pin = GET_PIN_PIN(Pin);
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348 uint32 mask = GET_PIN_MASK(Pin);
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350 Port_Base[port]->FUN &= ~mask;
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351 Port_Base[port]->FUN |= ((Mode & 1) << pin);
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