2 /**************************************************************************/
\r
3 /* FILE NAME: mpc5516.h COPYRIGHT (c) Freescale 2007 */
\r
4 /* VERSION: 1.0 All Rights Reserved */
\r
7 /* This file contain all of the register and bit field definitions for */
\r
9 /*========================================================================*/
\r
10 /* UPDATE HISTORY */
\r
11 /* REV AUTHOR DATE DESCRIPTION OF CHANGE */
\r
12 /* --- ----------- --------- --------------------- */
\r
13 /* 1.0 M. Stewart 05/Feb/07 Initial version. */
\r
14 /**************************************************************************/
\r
15 /*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
\r
22 #include "Compiler.h"
\r
23 #include "typedefs.h"
\r
31 #pragma ANSI_strict off
\r
34 /****************************************************************************/
\r
36 /****************************************************************************/
\r
37 CC_EXTENSION struct CRP_tag {
\r
47 vuint32_t TRIM32IRC:8;
\r
48 vuint32_t TRIMIRC:8;
\r
50 } CLKSRC; //Clock Source Register
\r
52 uint32_t crp_reserved1[3];
\r
61 vuint32_t RTCVAL:12;
\r
67 vuint32_t APIVAL:10;
\r
69 } RTCSC; //RTC Status and Control Register
\r
75 vuint32_t RTCCNT:27;
\r
77 } RTCCNT; //RTC Counter Register
\r
79 uint32_t crp_reserved2[6];
\r
89 } VREGSC; //VREG Trim Satus and Control Register
\r
91 uint32_t crp_reserved3[3];
\r
96 vuint32_t WKPSEL7:4;
\r
97 vuint32_t WKPSEL6:4;
\r
98 vuint32_t WKPSEL5:4;
\r
99 vuint32_t WKPSEL4:4;
\r
100 vuint32_t WKPSEL3:4;
\r
101 vuint32_t WKPSEL2:4;
\r
102 vuint32_t WKPSEL1:4;
\r
103 vuint32_t WKPSEL0:4;
\r
105 } WKPINSEL; //Wakeup Pin Source Select Register
\r
110 vuint32_t WKPDET7:2;
\r
111 vuint32_t WKPDET6:2;
\r
112 vuint32_t WKPDET5:2;
\r
113 vuint32_t WKPDET4:2;
\r
114 vuint32_t WKPDET3:2;
\r
115 vuint32_t WKPDET2:2;
\r
116 vuint32_t WKPDET1:2;
\r
117 vuint32_t WKPDET0:2;
\r
119 vuint32_t RTCOVREN:1;
\r
120 vuint32_t RTCWKEN:1; /* switched two fields JRichard 16MAY2007*/
\r
121 vuint32_t APIWKEN:1;
\r
123 vuint32_t WKCLKSEL:1;
\r
125 } WKSE; //Wakeup Source Enable Register
\r
127 /* } WKE; //Wakeup Source Enable Register */
\r
130 uint32_t crp_reserved4[2];
\r
135 vuint32_t Z1VEC:30;
\r
139 } Z1VEC; //Z1 Reset Vector Register
\r
144 vuint32_t Z0VEC:30;
\r
148 } Z0VEC; //Z0 Reset Vector Register
\r
153 vuint32_t RECPTR:30;
\r
154 vuint32_t FASTREC:1;
\r
157 } RECPRTR; //Reset Recovery Pointer Register
\r
159 uint32_t crp_reserved5;
\r
164 vuint32_t SLEEPF:1;
\r
167 vuint32_t WKRTCF:1;
\r
168 vuint32_t WKAPIF:1;
\r
169 vuint32_t WKRLLOVRF:1;
\r
170 vuint32_t PWKSRCF:8;
\r
174 vuint32_t PKREL:1; /* JRichard */
\r
175 //vuint32_t PKREN:1; /* JRichard */
\r
177 vuint32_t STOP12EN:1;
\r
178 vuint32_t RAMSEL:3;
\r
179 vuint32_t PWKSRIE:8;
\r
181 } PSCR; //Power Status and Control Register
\r
183 uint32_t crp_reserved6[3];
\r
188 vuint32_t LVI5IE:1;
\r
189 vuint32_t LVI5HIE:1;
\r
191 vuint32_t LVI5HF:1;
\r
192 vuint32_t LVILOCK:1;
\r
193 vuint32_t LVI5RE:1;
\r
196 } LVISC; //LVI Status and Control Register
\r
199 /****************************************************************************/
\r
200 /* MODULE : DMAMUX */
\r
201 /****************************************************************************/
\r
202 CC_EXTENSION struct DMAMUX_tag {
\r
210 } CHCONFIG[16]; /* DMA Channel Configuration Register */
\r
213 /****************************************************************************/
\r
214 /* MODULE : DSPI */
\r
215 /****************************************************************************/
\r
216 #include "ip_dspi.h"
\r
218 /****************************************************************************/
\r
219 /* MODULE : External Bus Interface (EBI) */
\r
220 /****************************************************************************/
\r
221 CC_EXTENSION struct CS_tag {
\r
222 union { /* Base Register Bank */
\r
238 union { /* Option Register Bank */
\r
252 union { /* Module Configuration Register */
\r
256 vuint32_t SIZEEN:1;
\r
270 uint32_t EBI_reserved1;
\r
272 union { /* Transfer Error Status Register */
\r
281 union { /* Bus Monitor Control Register */
\r
291 struct CS_tag CS[4];
\r
293 uint32_t EBI_reserved2[4];
\r
295 /* Calibration registers */
\r
296 struct CS_tag CAL_CS[4];
\r
299 /****************************************************************************/
\r
300 /* MODULE : eDMA */
\r
301 /****************************************************************************/
\r
302 #include "ip_edma.h"
\r
305 /****************************************************************************/
\r
306 /* MODULE : EMIOS */
\r
307 /****************************************************************************/
\r
308 CC_EXTENSION struct EMIOS_tag {
\r
312 vuint32_t DOZEEN:1;
\r
323 } MCR; /* Module Configuration Register */
\r
354 } GFLAG; /* Global FLAG Register */
\r
385 } OUDIS; /* Output Update Disable Register */
\r
389 } UCDIS; /* Disable Channel Register */
\r
391 uint32_t emios_reserved1[4];
\r
395 vuint32_t R; /* Channel A Data Register */
\r
397 } CADR; /* JRichard */
\r
400 vuint32_t R; /* Channel B Data Register */
\r
402 } CBDR; /* JRichard */
\r
405 vuint32_t R; /* Channel Counter Register */
\r
407 } CCNTR; /* JRichard */
\r
414 vuint32_t ODISSL:2;
\r
416 vuint32_t UCPREN:1;
\r
417 // vuint32_t UCPEN:1; /* JRichard 16MAY2007 */
\r
424 vuint32_t FORCMA:1;
\r
425 vuint32_t FORCMB:1;
\r
432 } CCR; /* Channel Control Register */
\r
433 //} C; /* Channel Control Register */ /* JRichard*/
\r
447 //} S; /* JRichard Channel Status Register */
\r
450 vuint32_t R; /* Alternate Channel A Data Register */
\r
453 uint32_t emios_channel_reserved[2];
\r
458 /****************************************************************************/
\r
459 /* MODULE : EQADC */
\r
460 /****************************************************************************/
\r
461 CC_EXTENSION struct EQADC_tag {
\r
470 } MCR; /* Module Configuration Register */
\r
474 } TST; /* Test Register */
\r
482 } NMSFR; /* Null Message Send Format Register */
\r
490 } ETDFR; /* External Trigger Digital Filter Register */
\r
495 vuint32_t CFPUSH:32;
\r
497 } CFPR[6]; /* CFIFO Push Registers */
\r
499 uint32_t eqadc_reserved1;
\r
501 uint32_t eqadc_reserved2;
\r
507 vuint32_t RFPOP:16;
\r
509 } RFPR[6]; /* Result FIFO Pop Registers */
\r
511 uint32_t eqadc_reserved3;
\r
513 uint32_t eqadc_reserved4;
\r
525 } CFCR[6]; /* CFIFO Control Registers */
\r
527 uint32_t eqadc_reserved5;
\r
546 } IDCR[6]; /* Interrupt and DMA Control Registers */
\r
548 uint32_t eqadc_reserved6;
\r
566 vuint32_t TNXTPTR:4;
\r
568 vuint32_t POPNXTPTR:4;
\r
570 } FISR[6]; /* FIFO and Interrupt Status Registers */
\r
572 uint32_t eqadc_reserved7;
\r
574 uint32_t eqadc_reserved8;
\r
582 } CFTCR[6]; /* CFIFO Transfer Counter Registers */
\r
584 uint32_t eqadc_reserved9;
\r
596 vuint32_t LCFTCB0:4;
\r
597 vuint32_t TC_LCFTCB0:11;
\r
599 } CFSSR0; /* CFIFO Status Register 0 */
\r
611 vuint32_t LCFTCB1:4;
\r
612 vuint32_t TC_LCFTCB1:11;
\r
614 } CFSSR1; /* CFIFO Status Register 1 */
\r
627 vuint32_t LCFTSSI:4;
\r
628 vuint32_t TC_LCFTSSI:11;
\r
630 } CFSSR2; /* CFIFO Status Register 2 */
\r
645 uint32_t eqadc_reserved11;
\r
655 } SSICR; /* SSI Control Register */
\r
662 vuint32_t RDATA:26;
\r
664 } SSIRDR; /* SSI Recieve Data Register */
\r
666 uint32_t eqadc_reserved12[17];
\r
676 uint32_t eqadc_reserved13[12];
\r
680 uint32_t eqadc_reserved14[32];
\r
690 uint32_t eqadc_reserved15[12];
\r
695 /****************************************************************************/
\r
696 /* MODULE : eSCI */
\r
697 /****************************************************************************/
\r
698 CC_EXTENSION struct ESCI_tag {
\r
721 } CR1; /* Control Register 1 */
\r
729 vuint16_t IEBERR:1;
\r
734 vuint16_t BESM13:1;
\r
742 } CR2; /* Control Register 2 */
\r
752 } DR; /* Data Register */
\r
780 } SR; /* Status Register */
\r
805 } LCR; /* LIN Control Register */
\r
809 } LTR; /* LIN Transmit Register */
\r
813 } LRR; /* LIN Recieve Register */
\r
817 } LPR; /* LIN CRC Polynom Register */
\r
820 /****************************************************************************/
\r
821 /* MODULE : FLASH */
\r
822 /****************************************************************************/
\r
823 CC_EXTENSION struct FLASH_tag {
\r
824 union { /* Module Configuration Register */
\r
853 union { /* LML Register */
\r
865 //} LML; /* JRichard 7MAR2007 */
\r
867 union { /* HL Register */
\r
872 vuint32_t HBLOCK:4;
\r
875 //} HBL; /* JRichard 7MAR2007 */
\r
877 union { /* SLML Register */
\r
882 vuint32_t SSLOCK:1;
\r
884 vuint32_t SMLOCK:2;
\r
886 vuint32_t SLLOCK:8;
\r
889 //} SLL; /* JRichard 7MAR2007 */
\r
891 union { /* LMS Register */
\r
900 //} LMS; /* JRichard 7MAR2007 */
\r
909 //} HBS; /* JRichard 7MAR2007 */
\r
920 union { /* Platform Flash Configuration Register for Port 0 */
\r
948 union { /* Platform Flash Configuration Register for Port 1 */
\r
977 #include "ip_flexcan.h"
\r
980 CC_EXTENSION struct FMPLL_tag {
\r
981 union { /* JRichard */
\r
985 vuint32_t PREDIV:3;
\r
992 vuint32_t DISCLK:1;
\r
993 vuint32_t LOLIRQ:1;
\r
994 vuint32_t LOCIRQ:1;
\r
1000 //int32_t FMPLL_reserved1; /* JRichard */
\r
1002 union { /* Synthesiser Status Register */
\r
1009 vuint32_t PLLSEL:1;
\r
1010 vuint32_t PLLREF:1;
\r
1011 vuint32_t LOCKS:1;
\r
1014 vuint32_t CALDONE:1;
\r
1015 vuint32_t CALPASS:1;
\r
1024 vuint32_t EMODE:1;
\r
1025 vuint32_t CLKCFG:3;
\r
1027 vuint32_t EPREDIV:4;
\r
1037 vuint32_t LOCEN:1;
\r
1038 vuint32_t LOLRE:1;
\r
1039 vuint32_t LOCRE:1;
\r
1040 vuint32_t LOLIRQ:1;
\r
1041 vuint32_t LOCIRQ:1;
\r
1043 vuint32_t ERATE:2;
\r
1045 vuint32_t EDEPTH:3;
\r
1052 /****************************************************************************/
\r
1053 /* MODULE : i2c */
\r
1054 /****************************************************************************/
\r
1055 CC_EXTENSION struct I2C_tag {
\r
1062 } IBAD; /* Module Bus Address Register */
\r
1069 } IBFD; /* Module Bus Frequency Register */
\r
1081 vuint8_t IBDOZE:1;
\r
1083 } IBCR; /* Module Bus Control Register */
\r
1097 } IBSR; /* Module Status Register */
\r
1104 } IBDR; /* Module Data Register */
\r
1112 } IBIC; /* Module Interrupt Configuration Register */
\r
1115 /****************************************************************************/
\r
1116 /* MODULE : INTC */
\r
1117 /****************************************************************************/
\r
1118 CC_EXTENSION struct INTC_tag {
\r
1123 vuint32_t VTES_PRC1:1;
\r
1125 vuint32_t HVEN_PRC1:1;
\r
1127 vuint32_t VTES_PRC0:1;
\r
1129 vuint32_t HVEN_PRC0:1;
\r
1131 } MCR; /* Module Configuration Register */
\r
1133 int32_t INTC_reserved1;
\r
1141 } CPR_PRC0; /* Processor 0 Current Priority Register */
\r
1149 } CPR_PRC1; /* Processor 1 Current Priority Register */
\r
1154 vuint32_t VTBA_PRC0:21;
\r
1155 vuint32_t INTVEC_PRC0:9;
\r
1158 } IACKR_PRC0; /* Processor 0 Interrupt Acknowledge Register */
\r
1163 vuint32_t VTBA_PRC1:21;
\r
1164 vuint32_t INTVEC_PRC1:9;
\r
1167 } IACKR_PRC1; /* Processor 1 Interrupt Acknowledge Register */
\r
1174 } EOIR_PRC0; /* Processor 0 End of Interrupt Register */
\r
1181 } EOIR_PRC1; /* Processor 1 End of Interrupt Register */
\r
1190 } SSCIR[8]; /* Software Set/Clear Interruput Register */
\r
1192 uint32_t intc_reserved2[6];
\r
1197 vuint8_t PRC_SEL:2;
\r
1201 } PSR[294]; /* Software Set/Clear Interrupt Register */
\r
1204 /****************************************************************************/
\r
1205 /* MODULE : MCM */
\r
1206 /****************************************************************************/
\r
1207 CC_EXTENSION struct MCM_tag {
\r
1209 uint32_t mcm_reserved1[5];
\r
1211 uint16_t mcm_reserved2;
\r
1218 vuint16_t SWRWH:1;
\r
1223 } SWTCR; //Software Watchdog Timer Control
\r
1225 uint8_t mcm_reserved3[3];
\r
1229 } SWTSR; //SWT Service Register
\r
1231 uint8_t mcm_reserved4[3];
\r
1239 } SWTIR; //SWT Interrupt Register
\r
1241 uint32_t mcm_reserved5[1];
\r
1249 } MUDCR; //Misc. User Defined Control Register
\r
1251 uint32_t mcm_reserved6[6];
\r
1252 uint8_t mcm_reserved7[3];
\r
1261 } ECR; //ECC Configuration Register
\r
1263 uint8_t mcm_reserved8[3];
\r
1272 } ESR; //ECC Status Register
\r
1274 uint16_t mcm_reserved9;
\r
1280 vuint16_t FRCNCI:1;
\r
1281 vuint16_t FR1NCI:1;
\r
1283 vuint16_t ERRBIT:7;
\r
1285 } EEGR; //ECC Error Generation Register
\r
1287 uint32_t mcm_reserved10;
\r
1291 } FEAR; //Flash ECC Address Register
\r
1293 uint16_t mcm_reserved11;
\r
1301 } FEMR; //Flash ECC Master Register
\r
1308 vuint8_t PROTECTION:4;
\r
1310 } FEAT; //Flash ECC Attributes Register
\r
1314 } FEDRH; //Flash ECC Data High Register
\r
1318 } FEDRL; //Flash ECC Data Low Register
\r
1323 vuint32_t REAR:32;
\r
1325 } REAR; //RAM ECC Address
\r
1327 uint8_t mcm_reserved12;
\r
1334 } RESR; //RAM ECC Syndrome
\r
1342 } REMR; //RAM ECC Master
\r
1349 vuint8_t PROTECTION:1;
\r
1351 } REAT; // RAM ECC Attributes Register
\r
1355 } REDRH; //RAM ECC Data High Register
\r
1359 } REDRL; //RAMECC Data Low Register
\r
1362 /****************************************************************************/
\r
1363 /* MODULE : MPU */
\r
1364 /****************************************************************************/
\r
1365 CC_EXTENSION struct MPU_tag {
\r
1377 } CESR; /* Module Control/Error Status Register */
\r
1379 uint32_t mpu_reserved1[3];
\r
1384 vuint32_t EADDR:32;
\r
1391 vuint32_t EACD:16;
\r
1394 vuint32_t EATTR:3;
\r
1402 vuint32_t EADDR:32;
\r
1409 vuint32_t EACD:16;
\r
1412 vuint32_t EATTR:3;
\r
1420 vuint32_t EADDR:32;
\r
1427 vuint32_t EACD:16;
\r
1430 vuint32_t EATTR:3;
\r
1435 uint32_t mpu_reserved2[246];
\r
1441 vuint32_t SRTADDR:27;
\r
1444 } WORD0; /* Region Descriptor n Word 0 */
\r
1449 vuint32_t ENDADDR:27;
\r
1452 } WORD1; /* Region Descriptor n Word 1 */
\r
1458 vuint32_t M4RE0:1;
\r
1473 } WORD2; /* Region Descriptor n Word 2 */
\r
1479 vuint32_t PIDMASK:8;
\r
1483 } WORD3; /* Region Descriptor n Word 3 */
\r
1487 uint32_t mpu_reserved3[192];
\r
1508 } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */
\r
1510 /****************************************************************************/
\r
1511 /* MODULE : pit */
\r
1512 /****************************************************************************/
\r
1513 CC_EXTENSION struct PIT_tag {
\r
1578 uint32_t pit_reserved1[23];
\r
1644 uint32_t pit_reserved2[23];
\r
1674 vuint32_t ISEL4:1;
\r
1675 vuint32_t ISEL3:1;
\r
1676 vuint32_t ISEL2:1;
\r
1677 vuint32_t ISEL1:1;
\r
1686 vuint32_t PEN10:1;
\r
1711 /****************************************************************************/
\r
1712 /* MODULE : sem4 */
\r
1713 /****************************************************************************/
\r
1714 CC_EXTENSION struct SEMA4_tag {
\r
1721 } GATE[16]; /* Gate n Register */
\r
1723 uint32_t sema4_reserved1[12];
\r
1738 vuint32_t INE10:1;
\r
1739 vuint32_t INE11:1;
\r
1740 vuint32_t INE12:1;
\r
1741 vuint32_t INE13:1;
\r
1742 vuint32_t INE14:1;
\r
1743 vuint32_t INE15:1;
\r
1748 uint32_t sema4_reserved2[1];
\r
1763 vuint32_t INE10:1;
\r
1764 vuint32_t INE11:1;
\r
1765 vuint32_t INE12:1;
\r
1766 vuint32_t INE13:1;
\r
1767 vuint32_t INE14:1;
\r
1768 vuint32_t INE15:1;
\r
1773 uint32_t sema4_reserved3[13];
\r
1798 uint32_t sema4_reserved4[1];
\r
1823 uint32_t sema4_reserved5[29];
\r
1829 vuint32_t RSTGSM:2;
\r
1831 vuint32_t RSTGMS:3;
\r
1832 vuint32_t RSTGTN:8;
\r
1841 vuint32_t RSTNSM:2;
\r
1843 vuint32_t RSTNMS:3;
\r
1844 vuint32_t RSTNTN:8;
\r
1849 /****************************************************************************/
\r
1850 /* MODULE : SIU */
\r
1851 /****************************************************************************/
\r
1852 CC_EXTENSION struct SIU_tag {
\r
1853 int32_t SIU_reserved0;
\r
1855 union { /* MCU ID Register */
\r
1858 vuint32_t PARTNUM:16;
\r
1860 //vuint32_t MASKNUM:16;
\r
1861 vuint32_t MASKNUM:12;
\r
1865 int32_t SIU_reserved1;
\r
1867 union { /* Reset Status Register */
\r
1880 vuint32_t BOOTCFG:2;
\r
1885 union { /* System Reset Control Register */
\r
1898 union { /* External Interrupt Status Register */
\r
1904 vuint32_t EIF15:1;
\r
1905 vuint32_t EIF14:1;
\r
1906 vuint32_t EIF13:1;
\r
1907 vuint32_t EIF12:1;
\r
1908 vuint32_t EIF11:1;
\r
1909 vuint32_t EIF10:1;
\r
1923 union { /* DMA/Interrupt Request Enable Register */
\r
1929 vuint32_t EIRE15:1;
\r
1930 vuint32_t EIRE14:1;
\r
1931 vuint32_t EIRE13:1;
\r
1932 vuint32_t EIRE12:1;
\r
1933 vuint32_t EIRE11:1;
\r
1934 vuint32_t EIRE10:1;
\r
1935 vuint32_t EIRE9:1;
\r
1936 vuint32_t EIRE8:1;
\r
1937 vuint32_t EIRE7:1;
\r
1938 vuint32_t EIRE6:1;
\r
1939 vuint32_t EIRE5:1;
\r
1940 vuint32_t EIRE4:1;
\r
1941 vuint32_t EIRE3:1;
\r
1942 vuint32_t EIRE2:1;
\r
1943 vuint32_t EIRE1:1;
\r
1944 vuint32_t EIRE0:1;
\r
1948 union { /* DMA/Interrupt Select Register */
\r
1952 vuint32_t DIRS3:1;
\r
1953 vuint32_t DIRS2:1;
\r
1954 vuint32_t DIRS1:1;
\r
1955 vuint32_t DIRS0:1;
\r
1959 union { /* Overrun Status Register */
\r
1963 vuint32_t OVF15:1;
\r
1964 vuint32_t OVF14:1;
\r
1965 vuint32_t OVF13:1;
\r
1966 vuint32_t OVF12:1;
\r
1967 vuint32_t OVF11:1;
\r
1968 vuint32_t OVF10:1;
\r
1982 union { /* Overrun Request Enable Register */
\r
1986 vuint32_t ORE15:1;
\r
1987 vuint32_t ORE14:1;
\r
1988 vuint32_t ORE13:1;
\r
1989 vuint32_t ORE12:1;
\r
1990 vuint32_t ORE11:1;
\r
1991 vuint32_t ORE10:1;
\r
2005 union { /* External IRQ Rising-Edge Event Enable Register */
\r
2008 vuint32_t NREE0:1;
\r
2009 vuint32_t NREE1:1;
\r
2011 vuint32_t IREE15:1;
\r
2012 vuint32_t IREE14:1;
\r
2013 vuint32_t IREE13:1;
\r
2014 vuint32_t IREE12:1;
\r
2015 vuint32_t IREE11:1;
\r
2016 vuint32_t IREE10:1;
\r
2017 vuint32_t IREE9:1;
\r
2018 vuint32_t IREE8:1;
\r
2019 vuint32_t IREE7:1;
\r
2020 vuint32_t IREE6:1;
\r
2021 vuint32_t IREE5:1;
\r
2022 vuint32_t IREE4:1;
\r
2023 vuint32_t IREE3:1;
\r
2024 vuint32_t IREE2:1;
\r
2025 vuint32_t IREE1:1;
\r
2026 vuint32_t IREE0:1;
\r
2030 union { /* External IRQ Falling-Edge Event Enable Register */
\r
2033 vuint32_t NFEE0:1;
\r
2034 vuint32_t NFEE1:1;
\r
2036 vuint32_t IFEE15:1;
\r
2037 vuint32_t IFEE14:1;
\r
2038 vuint32_t IFEE13:1;
\r
2039 vuint32_t IFEE12:1;
\r
2040 vuint32_t IFEE11:1;
\r
2041 vuint32_t IFEE10:1;
\r
2042 vuint32_t IFEE9:1;
\r
2043 vuint32_t IFEE8:1;
\r
2044 vuint32_t IFEE7:1;
\r
2045 vuint32_t IFEE6:1;
\r
2046 vuint32_t IFEE5:1;
\r
2047 vuint32_t IFEE4:1;
\r
2048 vuint32_t IFEE3:1;
\r
2049 vuint32_t IFEE2:1;
\r
2050 vuint32_t IFEE1:1;
\r
2051 vuint32_t IFEE0:1;
\r
2055 union { /* External IRQ Digital Filter Register */
\r
2063 union { /* External IRQ Filtered Input Register */
\r
2086 int32_t SIU_reserved2;
\r
2087 int32_t SIU_reserved11;
\r
2089 union { /* Pad Configuration Registers */
\r
2105 int32_t SIU_reserved3[295];
\r
2107 union { /* GPIO Pin Data Output Registers */
\r
2115 int32_t SIU_reserved4[91];
\r
2117 union { /* GPIO Pin Data Input Registers */
\r
2125 int32_t SIU_reserved5[27];
\r
2127 union { /* IMUX Register */
\r
2130 vuint32_t TSEL3:2;
\r
2131 vuint32_t TSEL2:2;
\r
2132 vuint32_t TSEL1:2;
\r
2133 vuint32_t TSEL0:2;
\r
2138 union { /* IMUX Register */
\r
2141 vuint32_t ESEL15:2;
\r
2142 vuint32_t ESEL14:2;
\r
2143 vuint32_t ESEL13:2;
\r
2144 vuint32_t ESEL12:2;
\r
2145 vuint32_t ESEL11:2;
\r
2146 vuint32_t ESEL10:2;
\r
2147 vuint32_t ESEL9:2;
\r
2148 vuint32_t ESEL8:2;
\r
2149 vuint32_t ESEL7:2;
\r
2150 vuint32_t ESEL6:2;
\r
2151 vuint32_t ESEL5:2;
\r
2152 vuint32_t ESEL4:2;
\r
2153 vuint32_t ESEL3:2;
\r
2154 vuint32_t ESEL2:2;
\r
2155 vuint32_t ESEL1:2;
\r
2156 vuint32_t ESEL0:2;
\r
2160 union { /* IMUX Register */
\r
2163 vuint32_t SELEMIOS15:2;
\r
2164 vuint32_t SELEMIOS14:2;
\r
2165 vuint32_t SELEMIOS13:2;
\r
2166 vuint32_t SELEMIOS12:2;
\r
2167 vuint32_t SELEMIOS11:2;
\r
2168 vuint32_t SELEMIOS10:2;
\r
2169 vuint32_t SELEMIOS9:2;
\r
2170 vuint32_t SELEMIOS8:2;
\r
2171 vuint32_t SELEMIOS7:2;
\r
2172 vuint32_t SELEMIOS6:2;
\r
2173 vuint32_t SELEMIOS5:2;
\r
2174 vuint32_t SELEMIOS4:2;
\r
2175 vuint32_t SELEMIOS3:2;
\r
2176 vuint32_t SELEMIOS2:2;
\r
2177 vuint32_t SELEMIOS1:2;
\r
2178 vuint32_t SELEMIOS0:2;
\r
2182 int32_t SIU_reserved6[29];
\r
2184 union { /* Chip Configuration Register Register */
\r
2188 vuint32_t MATCH:1;
\r
2189 vuint32_t DISNEX:1;
\r
2194 union { /* External Clock Configuration Register Register */
\r
2202 union { /* Compare A High Register */
\r
2206 union { /* Compare A Low Register */
\r
2210 union { /* Compare B High Register */
\r
2214 union { /* Compare B Low Register */
\r
2218 int32_t SIU_reserved7[2];
\r
2220 union { /* System CLock Register */
\r
2223 vuint32_t SYSCLKSEL:2;
\r
2224 vuint32_t SYSCLKDIV:2;
\r
2225 vuint32_t SWTCLKSEL:1;
\r
2227 vuint32_t LPCLKDIV7:2;
\r
2228 vuint32_t LPCLKDIV6:2;
\r
2229 vuint32_t LPCLKDIV5:2;
\r
2230 vuint32_t LPCLKDIV4:2;
\r
2231 vuint32_t LPCLKDIV3:2;
\r
2232 vuint32_t LPCLKDIV2:2;
\r
2233 vuint32_t LPCLKDIV1:2;
\r
2234 vuint32_t LPCLKDIV0:2;
\r
2238 union { /* Halt Register */
\r
2242 union { /* Halt Acknowledge Register */
\r
2246 int32_t SIU_reserved8[149];
\r
2248 union { /* Parallel GPIO Pin Data Output Register */
\r
2256 union { /* Parallel GPIO Pin Data Output Register */
\r
2264 union { /* Parallel GPIO Pin Data Output Register */
\r
2272 union { /* Parallel GPIO Pin Data Output Register */
\r
2280 union { /* Parallel GPIO Pin Data Output Register */
\r
2289 int32_t SIU_reserved9[11];
\r
2291 union { /* Parallel GPIO Pin Data Input Register */
\r
2299 union { /* Parallel GPIO Pin Data Input Register */
\r
2307 union { /* Parallel GPIO Pin Data Input Register */
\r
2315 union { /* Parallel GPIO Pin Data Input Register */
\r
2323 union { /* Parallel GPIO Pin Data Input Register */
\r
2332 int32_t SIU_reserved10[11];
\r
2334 union { /* Masked Parallel GPIO Pin Data Input Register */
\r
2337 vuint32_t PA_MASK:16;
\r
2342 union { /* Masked Parallel GPIO Pin Data Input Register */
\r
2345 vuint32_t PB_MASK:16;
\r
2350 union { /* Masked Parallel GPIO Pin Data Input Register */
\r
2353 vuint32_t PC_MASK:16;
\r
2358 union { /* Masked Parallel GPIO Pin Data Input Register */
\r
2361 vuint32_t PD_MASK:16;
\r
2366 union { /* Masked Parallel GPIO Pin Data Input Register */
\r
2369 vuint32_t PE_MASK:16;
\r
2374 union { /* Masked Parallel GPIO Pin Data Input Register */
\r
2377 vuint32_t PF_MASK:16;
\r
2382 union { /* Masked Parallel GPIO Pin Data Input Register */
\r
2385 vuint32_t PG_MASK:16;
\r
2390 union { /* Masked Parallel GPIO Pin Data Input Register */
\r
2393 vuint32_t PH_MASK:16;
\r
2398 union { /* Masked Parallel GPIO Pin Data Input Register */
\r
2401 vuint32_t PJ_MASK:16;
\r
2407 /****************************************************************************/
\r
2408 /* MODULE : FlexRay */
\r
2409 /****************************************************************************/
\r
2411 CC_EXTENSION typedef union uMVR {
\r
2414 vuint16_t CHIVER:8; /* CHI Version Number */
\r
2415 vuint16_t PEVER:8; /* PE Version Number */
\r
2419 CC_EXTENSION typedef union uMCR {
\r
2422 vuint16_t MEN:1; /* module enable */
\r
2424 vuint16_t SCMD:1; /* single channel mode */
\r
2425 vuint16_t CHB:1; /* channel B enable */
\r
2426 vuint16_t CHA:1; /* channel A enable */
\r
2427 vuint16_t SFFE:1; /* synchronization frame filter enable */
\r
2429 vuint16_t CLKSEL:1; /* protocol engine clock source select */
\r
2430 vuint16_t PRESCALE:3; /* protocol engine clock prescaler */
\r
2434 CC_EXTENSION typedef union uSTBSCR {
\r
2437 vuint16_t WMD:1; /* write mode */
\r
2438 vuint16_t STBSSEL:7; /* strobe signal select */
\r
2440 vuint16_t ENB:1; /* strobe signal enable */
\r
2442 vuint16_t STBPSEL:2; /* strobe port select */
\r
2445 CC_EXTENSION typedef union uSTBPCR {
\r
2449 vuint16_t STB3EN:1; /* strobe port enable */
\r
2450 vuint16_t STB2EN:1; /* strobe port enable */
\r
2451 vuint16_t STB1EN:1; /* strobe port enable */
\r
2452 vuint16_t STB0EN:1; /* strobe port enable */
\r
2456 CC_EXTENSION typedef union uMBDSR {
\r
2460 vuint16_t MBSEG2DS:7; /* message buffer segment 2 data size */
\r
2462 vuint16_t MBSEG1DS:7; /* message buffer segment 1 data size */
\r
2466 CC_EXTENSION typedef union uMBSSUTR {
\r
2471 vuint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */
\r
2473 vuint16_t LAST_MB_UTIL:6; /* last message buffer utilized */
\r
2477 CC_EXTENSION typedef union uPOCR {
\r
2481 vuint16_t WME:1; /* write mode external correction command */
\r
2483 vuint16_t EOC_AP:2; /* external offset correction application */
\r
2484 vuint16_t ERC_AP:2; /* external rate correction application */
\r
2485 vuint16_t BSY:1; /* command write busy / write mode command */
\r
2487 vuint16_t POCCMD:4; /* protocol command */
\r
2490 /* protocol commands */
\r
2491 CC_EXTENSION typedef union uGIFER {
\r
2494 vuint16_t MIF:1; /* module interrupt flag */
\r
2495 vuint16_t PRIF:1; /* protocol interrupt flag */
\r
2496 vuint16_t CHIF:1; /* CHI interrupt flag */
\r
2497 vuint16_t WKUPIF:1; /* wakeup interrupt flag */
\r
2498 vuint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
\r
2499 vuint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
\r
2500 vuint16_t RBIF:1; /* receive message buffer interrupt flag */
\r
2501 vuint16_t TBIF:1; /* transmit buffer interrupt flag */
\r
2502 vuint16_t MIE:1; /* module interrupt enable */
\r
2503 vuint16_t PRIE:1; /* protocol interrupt enable */
\r
2504 vuint16_t CHIE:1; /* CHI interrupt enable */
\r
2505 vuint16_t WKUPIE:1; /* wakeup interrupt enable */
\r
2506 vuint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
\r
2507 vuint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
\r
2508 vuint16_t RBIE:1; /* receive message buffer interrupt enable */
\r
2509 vuint16_t TBIE:1; /* transmit buffer interrupt enable */
\r
2513 CC_EXTENSION typedef union uPIFR0 {
\r
2516 vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */
\r
2517 vuint16_t INTLIF:1; /* internal protocol error interrupt flag */
\r
2518 vuint16_t ILCFIF:1; /* illegal protocol configuration flag */
\r
2519 vuint16_t CSAIF:1; /* cold start abort interrupt flag */
\r
2520 vuint16_t MRCIF:1; /* missing rate correctio interrupt flag */
\r
2521 vuint16_t MOCIF:1; /* missing offset correctio interrupt flag */
\r
2522 vuint16_t CCLIF:1; /* clock correction limit reached interrupt flag */
\r
2523 vuint16_t MXSIF:1; /* max sync frames detected interrupt flag */
\r
2524 vuint16_t MTXIF:1; /* media access test symbol received flag */
\r
2525 vuint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
\r
2526 vuint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
\r
2527 vuint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
\r
2528 vuint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
\r
2529 vuint16_t TI2IF:1; /* timer 2 expired interrupt flag */
\r
2530 vuint16_t TI1IF:1; /* timer 1 expired interrupt flag */
\r
2531 vuint16_t CYSIF:1; /* cycle start interrupt flag */
\r
2535 CC_EXTENSION typedef union uPIFR1 {
\r
2538 vuint16_t EMCIF:1; /* error mode changed interrupt flag */
\r
2539 vuint16_t IPCIF:1; /* illegal protocol command interrupt flag */
\r
2540 vuint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
\r
2541 vuint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */
\r
2542 vuint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
\r
2543 vuint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
\r
2544 vuint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
\r
2545 vuint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
\r
2547 vuint16_t EVTIF:1; /* even cycle table written interrupt flag */
\r
2548 vuint16_t ODTIF:1; /* odd cycle table written interrupt flag */
\r
2552 CC_EXTENSION typedef union uPIER0 {
\r
2555 vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */
\r
2556 vuint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */
\r
2557 vuint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
\r
2558 vuint16_t CSAIE:1; /* cold start abort interrupt enable */
\r
2559 vuint16_t MRCIE:1; /* missing rate correctio interrupt enable */
\r
2560 vuint16_t MOCIE:1; /* missing offset correctio interrupt enable */
\r
2561 vuint16_t CCLIE:1; /* clock correction limit reached interrupt enable */
\r
2562 vuint16_t MXSIE:1; /* max sync frames detected interrupt enable */
\r
2563 vuint16_t MTXIE:1; /* media access test symbol received interrupt enable */
\r
2564 vuint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
\r
2565 vuint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
\r
2566 vuint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
\r
2567 vuint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
\r
2568 vuint16_t TI2IE:1; /* timer 2 expired interrupt enable */
\r
2569 vuint16_t TI1IE:1; /* timer 1 expired interrupt enable */
\r
2570 vuint16_t CYSIE:1; /* cycle start interrupt enable */
\r
2573 CC_EXTENSION typedef union uPIER1 {
\r
2576 vuint16_t EMCIE:1; /* error mode changed interrupt enable */
\r
2577 vuint16_t IPCIE:1; /* illegal protocol command interrupt enable */
\r
2578 vuint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
\r
2579 vuint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */
\r
2580 vuint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
\r
2581 vuint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
\r
2582 vuint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
\r
2583 vuint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
\r
2585 vuint16_t EVTIE:1; /* even cycle table written interrupt enable */
\r
2586 vuint16_t ODTIE:1; /* odd cycle table written interrupt enable */
\r
2590 CC_EXTENSION typedef union uCHIERFR {
\r
2593 vuint16_t FRLBEF:1; /* flame lost channel B error flag */
\r
2594 vuint16_t FRLAEF:1; /* frame lost channel A error flag */
\r
2595 vuint16_t PCMIEF:1; /* command ignored error flag */
\r
2596 vuint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
\r
2597 vuint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
\r
2598 vuint16_t MSBEF:1; /* message buffer search error flag */
\r
2599 vuint16_t MBUEF:1; /* message buffer utilization error flag */
\r
2600 vuint16_t LCKEF:1; /* lock error flag */
\r
2601 vuint16_t DBLEF:1; /* double transmit message buffer lock error flag */
\r
2602 vuint16_t SBCFEF:1; /* system bus communication failure error flag */
\r
2603 vuint16_t FIDEF:1; /* frame ID error flag */
\r
2604 vuint16_t DPLEF:1; /* dynamic payload length error flag */
\r
2605 vuint16_t SPLEF:1; /* static payload length error flag */
\r
2606 vuint16_t NMLEF:1; /* network management length error flag */
\r
2607 vuint16_t NMFEF:1; /* network management frame error flag */
\r
2608 vuint16_t ILSAEF:1; /* illegal access error flag */
\r
2611 CC_EXTENSION typedef union uMBIVEC {
\r
2616 vuint16_t TBIVEC:6; /* transmit buffer interrupt vector */
\r
2618 vuint16_t RBIVEC:6; /* receive buffer interrupt vector */
\r
2622 CC_EXTENSION typedef union uPSR0 {
\r
2625 vuint16_t ERRMODE:2; /* error mode */
\r
2626 vuint16_t SLOTMODE:2; /* slot mode */
\r
2628 vuint16_t PROTSTATE:3; /* protocol state */
\r
2629 vuint16_t SUBSTATE:4; /* protocol sub state */
\r
2631 vuint16_t WAKEUPSTATUS:3; /* wakeup status */
\r
2635 /* protocol states */
\r
2636 /* protocol sub-states */
\r
2637 /* wakeup status */
\r
2638 CC_EXTENSION typedef union uPSR1 {
\r
2641 vuint16_t CSAA:1; /* cold start attempt abort flag */
\r
2642 vuint16_t SCP:1; /* cold start path */
\r
2644 vuint16_t REMCSAT:5; /* remanining coldstart attempts */
\r
2645 vuint16_t CPN:1; /* cold start noise path */
\r
2646 vuint16_t HHR:1; /* host halt request pending */
\r
2647 vuint16_t FRZ:1; /* freeze occured */
\r
2648 vuint16_t APTAC:5; /* allow passive to active counter */
\r
2651 CC_EXTENSION typedef union uPSR2 {
\r
2654 vuint16_t NBVB:1; /* NIT boundary violation on channel B */
\r
2655 vuint16_t NSEB:1; /* NIT syntax error on channel B */
\r
2656 vuint16_t STCB:1; /* symbol window transmit conflict on channel B */
\r
2657 vuint16_t SBVB:1; /* symbol window boundary violation on channel B */
\r
2658 vuint16_t SSEB:1; /* symbol window syntax error on channel B */
\r
2659 vuint16_t MTB:1; /* media access test symbol MTS received on channel B */
\r
2660 vuint16_t NBVA:1; /* NIT boundary violation on channel A */
\r
2661 vuint16_t NSEA:1; /* NIT syntax error on channel A */
\r
2662 vuint16_t STCA:1; /* symbol window transmit conflict on channel A */
\r
2663 vuint16_t SBVA:1; /* symbol window boundary violation on channel A */
\r
2664 vuint16_t SSEA:1; /* symbol window syntax error on channel A */
\r
2665 vuint16_t MTA:1; /* media access test symbol MTS received on channel A */
\r
2666 vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
\r
2669 CC_EXTENSION typedef union uPSR3 {
\r
2673 vuint16_t WUB:1; /* wakeup symbol received on channel B */
\r
2674 vuint16_t ABVB:1; /* aggregated boundary violation on channel B */
\r
2675 vuint16_t AACB:1; /* aggregated additional communication on channel B */
\r
2676 vuint16_t ACEB:1; /* aggregated content error on channel B */
\r
2677 vuint16_t ASEB:1; /* aggregated syntax error on channel B */
\r
2678 vuint16_t AVFB:1; /* aggregated valid frame on channel B */
\r
2680 vuint16_t WUA:1; /* wakeup symbol received on channel A */
\r
2681 vuint16_t ABVA:1; /* aggregated boundary violation on channel A */
\r
2682 vuint16_t AACA:1; /* aggregated additional communication on channel A */
\r
2683 vuint16_t ACEA:1; /* aggregated content error on channel A */
\r
2684 vuint16_t ASEA:1; /* aggregated syntax error on channel A */
\r
2685 vuint16_t AVFA:1; /* aggregated valid frame on channel A */
\r
2688 CC_EXTENSION typedef union uCIFRR {
\r
2692 vuint16_t MIFR:1; /* module interrupt flag */
\r
2693 vuint16_t PRIFR:1; /* protocol interrupt flag */
\r
2694 vuint16_t CHIFR:1; /* CHI interrupt flag */
\r
2695 vuint16_t WUPIFR:1; /* wakeup interrupt flag */
\r
2696 vuint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */
\r
2697 vuint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */
\r
2698 vuint16_t RBIFR:1; /* receive message buffer interrupt flag */
\r
2699 vuint16_t TBIFR:1; /* transmit buffer interrupt flag */
\r
2702 CC_EXTENSION typedef union uSFCNTR {
\r
2705 vuint16_t SFEVB:4; /* sync frames channel B, even cycle */
\r
2706 vuint16_t SFEVA:4; /* sync frames channel A, even cycle */
\r
2707 vuint16_t SFODB:4; /* sync frames channel B, odd cycle */
\r
2708 vuint16_t SFODA:4; /* sync frames channel A, odd cycle */
\r
2712 CC_EXTENSION typedef union uSFTCCSR {
\r
2715 vuint16_t ELKT:1; /* even cycle tables lock and unlock trigger */
\r
2716 vuint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */
\r
2717 vuint16_t CYCNUM:6; /* cycle number */
\r
2718 vuint16_t ELKS:1; /* even cycle tables lock status */
\r
2719 vuint16_t OLKS:1; /* odd cycle tables lock status */
\r
2720 vuint16_t EVAL:1; /* even cycle tables valid */
\r
2721 vuint16_t OVAL:1; /* odd cycle tables valid */
\r
2723 vuint16_t OPT:1; /*one pair trigger */
\r
2724 vuint16_t SDVEN:1; /* sync frame deviation table enable */
\r
2725 vuint16_t SIDEN:1; /* sync frame ID table enable */
\r
2728 CC_EXTENSION typedef union uSFIDRFR {
\r
2732 vuint16_t SYNFRID:10; /* sync frame rejection ID */
\r
2736 CC_EXTENSION typedef union uTICCR {
\r
2740 vuint16_t T2CFG:1; /* timer 2 configuration */
\r
2741 vuint16_t T2REP:1; /* timer 2 repetitive mode */
\r
2743 vuint16_t T2SP:1; /* timer 2 stop */
\r
2744 vuint16_t T2TR:1; /* timer 2 trigger */
\r
2745 vuint16_t T2ST:1; /* timer 2 state */
\r
2747 vuint16_t T1REP:1; /* timer 1 repetitive mode */
\r
2749 vuint16_t T1SP:1; /* timer 1 stop */
\r
2750 vuint16_t T1TR:1; /* timer 1 trigger */
\r
2751 vuint16_t T1ST:1; /* timer 1 state */
\r
2755 CC_EXTENSION typedef union uTI1CYSR {
\r
2759 vuint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */
\r
2761 vuint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */
\r
2766 CC_EXTENSION typedef union uSSSR {
\r
2769 vuint16_t WMD:1; /* write mode */
\r
2771 vuint16_t SEL:2; /* static slot number */
\r
2773 vuint16_t SLOTNUMBER:11; /* selector */
\r
2777 CC_EXTENSION typedef union uSSCCR {
\r
2780 vuint16_t WMD:1; /* write mode */
\r
2782 vuint16_t SEL:2; /* selector */
\r
2784 vuint16_t CNTCFG:2; /* counter configuration */
\r
2785 vuint16_t MCY:1; /* multi cycle selection */
\r
2786 vuint16_t VFR:1; /* valid frame selection */
\r
2787 vuint16_t SYF:1; /* sync frame selection */
\r
2788 vuint16_t NUF:1; /* null frame selection */
\r
2789 vuint16_t SUF:1; /* startup frame selection */
\r
2790 vuint16_t STATUSMASK:4; /* slot status mask */
\r
2793 CC_EXTENSION typedef union uSSR {
\r
2796 vuint16_t VFB:1; /* valid frame on channel B */
\r
2797 vuint16_t SYB:1; /* valid sync frame on channel B */
\r
2798 vuint16_t NFB:1; /* valid null frame on channel B */
\r
2799 vuint16_t SUB:1; /* valid startup frame on channel B */
\r
2800 vuint16_t SEB:1; /* syntax error on channel B */
\r
2801 vuint16_t CEB:1; /* content error on channel B */
\r
2802 vuint16_t BVB:1; /* boundary violation on channel B */
\r
2803 vuint16_t TCB:1; /* tx conflict on channel B */
\r
2804 vuint16_t VFA:1; /* valid frame on channel A */
\r
2805 vuint16_t SYA:1; /* valid sync frame on channel A */
\r
2806 vuint16_t NFA:1; /* valid null frame on channel A */
\r
2807 vuint16_t SUA:1; /* valid startup frame on channel A */
\r
2808 vuint16_t SEA:1; /* syntax error on channel A */
\r
2809 vuint16_t CEA:1; /* content error on channel A */
\r
2810 vuint16_t BVA:1; /* boundary violation on channel A */
\r
2811 vuint16_t TCA:1; /* tx conflict on channel A */
\r
2814 CC_EXTENSION typedef union uMTSCFR {
\r
2817 vuint16_t MTE:1; /* media access test symbol transmission enable */
\r
2819 vuint16_t CYCCNTMSK:6; /* cycle counter mask */
\r
2821 vuint16_t CYCCNTVAL:6; /* cycle counter value */
\r
2825 CC_EXTENSION typedef union uRSBIR {
\r
2828 vuint16_t WMD:1; /* write mode */
\r
2830 vuint16_t SEL:2; /* selector */
\r
2832 vuint16_t RSBIDX:7; /* receive shadow buffer index */
\r
2836 CC_EXTENSION typedef union uRFDSR {
\r
2839 vuint16_t FIFODEPTH:8; /* fifo depth */
\r
2841 vuint16_t ENTRYSIZE:7; /* entry size */
\r
2845 CC_EXTENSION typedef union uRFRFCFR {
\r
2848 vuint16_t WMD:1; /* write mode */
\r
2849 vuint16_t IBD:1; /* interval boundary */
\r
2850 vuint16_t SEL:2; /* filter number */
\r
2852 vuint16_t SID:11; /* slot ID */
\r
2856 CC_EXTENSION typedef union uRFRFCTR {
\r
2860 vuint16_t F3MD:1; /* filter mode */
\r
2861 vuint16_t F2MD:1; /* filter mode */
\r
2862 vuint16_t F1MD:1; /* filter mode */
\r
2863 vuint16_t F0MD:1; /* filter mode */
\r
2865 vuint16_t F3EN:1; /* filter enable */
\r
2866 vuint16_t F2EN:1; /* filter enable */
\r
2867 vuint16_t F1EN:1; /* filter enable */
\r
2868 vuint16_t F0EN:1; /* filter enable */
\r
2871 CC_EXTENSION typedef union uPCR0 {
\r
2874 vuint16_t ACTION_POINT_OFFSET:6;
\r
2875 vuint16_t STATIC_SLOT_LENGTH:10;
\r
2879 CC_EXTENSION typedef union uPCR1 {
\r
2883 vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
\r
2887 CC_EXTENSION typedef union uPCR2 {
\r
2890 vuint16_t MINISLOT_AFTER_ACTION_POINT:6;
\r
2891 vuint16_t NUMBER_OF_STATIC_SLOTS:10;
\r
2895 CC_EXTENSION typedef union uPCR3 {
\r
2898 vuint16_t WAKEUP_SYMBOL_RX_LOW:6;
\r
2899 vuint16_t MINISLOT_ACTION_POINT_OFFSET:5;
\r
2900 vuint16_t COLDSTART_ATTEMPTS:5;
\r
2904 CC_EXTENSION typedef union uPCR4 {
\r
2907 vuint16_t CAS_RX_LOW_MAX:7;
\r
2908 vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
\r
2912 CC_EXTENSION typedef union uPCR5 {
\r
2915 vuint16_t TSS_TRANSMITTER:4;
\r
2916 vuint16_t WAKEUP_SYMBOL_TX_LOW:6;
\r
2917 vuint16_t WAKEUP_SYMBOL_RX_IDLE:6;
\r
2921 CC_EXTENSION typedef union uPCR6 {
\r
2925 vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
\r
2926 vuint16_t MACRO_INITIAL_OFFSET_A:7;
\r
2930 CC_EXTENSION typedef union uPCR7 {
\r
2933 vuint16_t DECODING_CORRECTION_B:9;
\r
2934 vuint16_t MICRO_PER_MACRO_NOM_HALF:7;
\r
2938 CC_EXTENSION typedef union uPCR8 {
\r
2941 vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
\r
2942 vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
\r
2943 vuint16_t WAKEUP_SYMBOL_TX_IDLE:8;
\r
2947 CC_EXTENSION typedef union uPCR9 {
\r
2950 vuint16_t MINISLOT_EXISTS:1;
\r
2951 vuint16_t SYMBOL_WINDOW_EXISTS:1;
\r
2952 vuint16_t OFFSET_CORRECTION_OUT:14;
\r
2956 CC_EXTENSION typedef union uPCR10 {
\r
2959 vuint16_t SINGLE_SLOT_ENABLED:1;
\r
2960 vuint16_t WAKEUP_CHANNEL:1;
\r
2961 vuint16_t MACRO_PER_CYCLE:14;
\r
2965 CC_EXTENSION typedef union uPCR11 {
\r
2968 vuint16_t KEY_SLOT_USED_FOR_STARTUP:1;
\r
2969 vuint16_t KEY_SLOT_USED_FOR_SYNC:1;
\r
2970 vuint16_t OFFSET_CORRECTION_START:14;
\r
2974 CC_EXTENSION typedef union uPCR12 {
\r
2977 vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
\r
2978 vuint16_t KEY_SLOT_HEADER_CRC:11;
\r
2982 CC_EXTENSION typedef union uPCR13 {
\r
2985 vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
\r
2986 vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
\r
2990 CC_EXTENSION typedef union uPCR14 {
\r
2993 vuint16_t RATE_CORRECTION_OUT:11;
\r
2994 vuint16_t LISTEN_TIMEOUT_H:5;
\r
2998 CC_EXTENSION typedef union uPCR15 {
\r
3001 vuint16_t LISTEN_TIMEOUT_L:16;
\r
3005 CC_EXTENSION typedef union uPCR16 {
\r
3008 vuint16_t MACRO_INITIAL_OFFSET_B:7;
\r
3009 vuint16_t NOISE_LISTEN_TIMEOUT_H:9;
\r
3013 CC_EXTENSION typedef union uPCR17 {
\r
3016 vuint16_t NOISE_LISTEN_TIMEOUT_L:16;
\r
3020 CC_EXTENSION typedef union uPCR18 {
\r
3023 vuint16_t WAKEUP_PATTERN:6;
\r
3024 vuint16_t KEY_SLOT_ID:10;
\r
3028 CC_EXTENSION typedef union uPCR19 {
\r
3031 vuint16_t DECODING_CORRECTION_A:9;
\r
3032 vuint16_t PAYLOAD_LENGTH_STATIC:7;
\r
3036 CC_EXTENSION typedef union uPCR20 {
\r
3039 vuint16_t MICRO_INITIAL_OFFSET_B:8;
\r
3040 vuint16_t MICRO_INITIAL_OFFSET_A:8;
\r
3044 CC_EXTENSION typedef union uPCR21 {
\r
3047 vuint16_t EXTERN_RATE_CORRECTION:3;
\r
3048 vuint16_t LATEST_TX:13;
\r
3052 CC_EXTENSION typedef union uPCR22 {
\r
3056 vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
\r
3057 vuint16_t MICRO_PER_CYCLE_H:4;
\r
3061 CC_EXTENSION typedef union uPCR23 {
\r
3064 vuint16_t micro_per_cycle_l:16;
\r
3068 CC_EXTENSION typedef union uPCR24 {
\r
3071 vuint16_t CLUSTER_DRIFT_DAMPING:5;
\r
3072 vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
\r
3073 vuint16_t MICRO_PER_CYCLE_MIN_H:4;
\r
3077 CC_EXTENSION typedef union uPCR25 {
\r
3080 vuint16_t MICRO_PER_CYCLE_MIN_L:16;
\r
3084 CC_EXTENSION typedef union uPCR26 {
\r
3087 vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
\r
3088 vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
\r
3089 vuint16_t MICRO_PER_CYCLE_MAX_H:4;
\r
3093 CC_EXTENSION typedef union uPCR27 {
\r
3096 vuint16_t MICRO_PER_CYCLE_MAX_L:16;
\r
3100 CC_EXTENSION typedef union uPCR28 {
\r
3103 vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
\r
3104 vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
\r
3108 CC_EXTENSION typedef union uPCR29 {
\r
3111 vuint16_t EXTERN_OFFSET_CORRECTION:3;
\r
3112 vuint16_t MINISLOTS_MAX:13;
\r
3116 CC_EXTENSION typedef union uPCR30 {
\r
3120 vuint16_t SYNC_NODE_MAX:4;
\r
3124 CC_EXTENSION typedef struct uMSG_BUFF_CCS {
\r
3129 vuint16_t MCM:1; /* message buffer commit mode */
\r
3130 vuint16_t MBT:1; /* message buffer type */
\r
3131 vuint16_t MTD:1; /* message buffer direction */
\r
3132 vuint16_t CMT:1; /* commit for transmission */
\r
3133 vuint16_t EDT:1; /* enable / disable trigger */
\r
3134 vuint16_t LCKT:1; /* lock request trigger */
\r
3135 vuint16_t MBIE:1; /* message buffer interrupt enable */
\r
3137 vuint16_t DUP:1; /* data updated */
\r
3138 vuint16_t DVAL:1; /* data valid */
\r
3139 vuint16_t EDS:1; /* lock status */
\r
3140 vuint16_t LCKS:1; /* enable / disable status */
\r
3141 vuint16_t MBIF:1; /* message buffer interrupt flag */
\r
3147 vuint16_t MTM:1; /* message buffer transmission mode */
\r
3148 vuint16_t CHNLA:1; /* channel assignement */
\r
3149 vuint16_t CHNLB:1; /* channel assignement */
\r
3150 vuint16_t CCFE:1; /* cycle counter filter enable */
\r
3151 vuint16_t CCFMSK:6; /* cycle counter filter mask */
\r
3152 vuint16_t CCFVAL:6; /* cycle counter filter value */
\r
3159 vuint16_t FID:11; /* frame ID */
\r
3167 vuint16_t MBIDX:7; /* message buffer index */
\r
3171 CC_EXTENSION typedef union uSYSBADHR {
\r
3174 CC_EXTENSION typedef union uSYSBADLR {
\r
3177 CC_EXTENSION typedef union uPADR {
\r
3180 CC_EXTENSION typedef union uPDAR {
\r
3183 CC_EXTENSION typedef union uCASERCR {
\r
3186 CC_EXTENSION typedef union uCBSERCR {
\r
3189 CC_EXTENSION typedef union uCYCTR {
\r
3192 CC_EXTENSION typedef union uMTCTR {
\r
3195 CC_EXTENSION typedef union uSLTCTAR {
\r
3198 CC_EXTENSION typedef union uSLTCTBR {
\r
3201 CC_EXTENSION typedef union uRTCORVR {
\r
3204 CC_EXTENSION typedef union uOFCORVR {
\r
3207 CC_EXTENSION typedef union uSFTOR {
\r
3210 CC_EXTENSION typedef union uSFIDAFVR {
\r
3213 CC_EXTENSION typedef union uSFIDAFMR {
\r
3216 CC_EXTENSION typedef union uNMVR {
\r
3219 CC_EXTENSION typedef union uNMVLR {
\r
3222 CC_EXTENSION typedef union uT1MTOR {
\r
3225 CC_EXTENSION typedef union uTI2CR0 {
\r
3228 CC_EXTENSION typedef union uTI2CR1 {
\r
3231 CC_EXTENSION typedef union uSSCR {
\r
3234 CC_EXTENSION typedef union uRFSR {
\r
3237 CC_EXTENSION typedef union uRFSIR {
\r
3240 CC_EXTENSION typedef union uRFARIR {
\r
3243 CC_EXTENSION typedef union uRFBRIR {
\r
3246 CC_EXTENSION typedef union uRFMIDAFVR {
\r
3249 CC_EXTENSION typedef union uRFMIAFMR {
\r
3252 CC_EXTENSION typedef union uRFFIDRFVR {
\r
3255 CC_EXTENSION typedef union uRFFIDRFMR {
\r
3258 CC_EXTENSION typedef union uLDTXSLAR {
\r
3261 CC_EXTENSION typedef union uLDTXSLBR {
\r
3265 typedef struct FR_tag {
\r
3266 volatile MVR_t MVR; /*module version register *//*0 */
\r
3267 volatile MCR_t MCR; /*module configuration register *//*2 */
\r
3268 volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */
\r
3269 volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */
\r
3270 volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */
\r
3271 volatile STBPCR_t STBPCR; /*strobe port control register *//*A */
\r
3272 volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */
\r
3273 volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */
\r
3274 volatile PADR_t PADR; /*PE address register *//*10 */
\r
3275 volatile PDAR_t PDAR; /*PE data register *//*12 */
\r
3276 volatile POCR_t POCR; /*Protocol operation control register *//*14 */
\r
3277 volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
\r
3278 volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
\r
3279 volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
\r
3280 volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
\r
3281 volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
\r
3282 volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */
\r
3283 volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */
\r
3284 volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */
\r
3285 volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */
\r
3286 volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */
\r
3287 volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */
\r
3288 volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */
\r
3289 volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */
\r
3290 volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
\r
3291 volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
\r
3292 volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */
\r
3293 volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */
\r
3294 volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */
\r
3295 volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */
\r
3296 volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
\r
3297 vuint16_t reserved3[1]; /*3E */
\r
3298 volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */
\r
3299 volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
\r
3300 volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */
\r
3301 volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */
\r
3302 volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */
\r
3303 volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */
\r
3304 volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */
\r
3305 volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
\r
3306 volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
\r
3307 volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */
\r
3308 volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */
\r
3309 volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */
\r
3310 volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */
\r
3311 volatile SSSR_t SSSR; /*slot status selection register *//*64 */
\r
3312 volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
\r
3313 volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */
\r
3314 volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */
\r
3315 volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */
\r
3316 volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */
\r
3317 volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
\r
3318 volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */
\r
3319 volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
\r
3320 volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
\r
3321 volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */
\r
3322 volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */
\r
3323 volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
\r
3324 volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */
\r
3325 volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
\r
3326 volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
\r
3327 volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */
\r
3328 volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */
\r
3329 volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */
\r
3330 volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */
\r
3331 volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */
\r
3332 volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */
\r
3333 volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */
\r
3334 volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */
\r
3335 volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */
\r
3336 volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */
\r
3337 volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */
\r
3338 volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */
\r
3339 volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */
\r
3340 volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */
\r
3341 volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
\r
3342 volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
\r
3343 volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
\r
3344 volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
\r
3345 volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
\r
3346 volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
\r
3347 volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
\r
3348 volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
\r
3349 volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
\r
3350 volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
\r
3351 volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
\r
3352 volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
\r
3353 volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
\r
3354 volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
\r
3355 volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
\r
3356 volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
\r
3357 volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
\r
3358 volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
\r
3359 volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
\r
3360 volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
\r
3361 volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
\r
3362 vuint16_t reserved2[17];
\r
3363 volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */
\r
3366 CC_EXTENSION typedef union uF_HEADER /* frame header */
\r
3370 vuint16_t HDCRC:11; /* Header CRC */
\r
3372 vuint16_t CYCCNT:6; /* Cycle Count */
\r
3374 vuint16_t PLDLEN:7; /* Payload Length */
\r
3376 vuint16_t PPI:1; /* Payload Preamble Indicator */
\r
3377 vuint16_t NUF:1; /* Null Frame Indicator */
\r
3378 vuint16_t SYF:1; /* Sync Frame Indicator */
\r
3379 vuint16_t SUF:1; /* Startup Frame Indicator */
\r
3380 vuint16_t FID:11; /* Frame ID */
\r
3382 vuint16_t WORDS[3];
\r
3384 CC_EXTENSION typedef union uS_STSTUS /* slot status */
\r
3387 vuint16_t VFB:1; /* Valid Frame on channel B */
\r
3388 vuint16_t SYB:1; /* Sync Frame Indicator channel B */
\r
3389 vuint16_t NFB:1; /* Null Frame Indicator channel B */
\r
3390 vuint16_t SUB:1; /* Startup Frame Indicator channel B */
\r
3391 vuint16_t SEB:1; /* Syntax Error on channel B */
\r
3392 vuint16_t CEB:1; /* Content Error on channel B */
\r
3393 vuint16_t BVB:1; /* Boundary Violation on channel B */
\r
3394 vuint16_t CH:1; /* Channel */
\r
3395 vuint16_t VFA:1; /* Valid Frame on channel A */
\r
3396 vuint16_t SYA:1; /* Sync Frame Indicator channel A */
\r
3397 vuint16_t NFA:1; /* Null Frame Indicator channel A */
\r
3398 vuint16_t SUA:1; /* Startup Frame Indicator channel A */
\r
3399 vuint16_t SEA:1; /* Syntax Error on channel A */
\r
3400 vuint16_t CEA:1; /* Content Error on channel A */
\r
3401 vuint16_t BVA:1; /* Boundary Violation on channel A */
\r
3405 vuint16_t VFB:1; /* Valid Frame on channel B */
\r
3406 vuint16_t SYB:1; /* Sync Frame Indicator channel B */
\r
3407 vuint16_t NFB:1; /* Null Frame Indicator channel B */
\r
3408 vuint16_t SUB:1; /* Startup Frame Indicator channel B */
\r
3409 vuint16_t SEB:1; /* Syntax Error on channel B */
\r
3410 vuint16_t CEB:1; /* Content Error on channel B */
\r
3411 vuint16_t BVB:1; /* Boundary Violation on channel B */
\r
3412 vuint16_t TCB:1; /* Tx Conflict on channel B */
\r
3413 vuint16_t VFA:1; /* Valid Frame on channel A */
\r
3414 vuint16_t SYA:1; /* Sync Frame Indicator channel A */
\r
3415 vuint16_t NFA:1; /* Null Frame Indicator channel A */
\r
3416 vuint16_t SUA:1; /* Startup Frame Indicator channel A */
\r
3417 vuint16_t SEA:1; /* Syntax Error on channel A */
\r
3418 vuint16_t CEA:1; /* Content Error on channel A */
\r
3419 vuint16_t BVA:1; /* Boundary Violation on channel A */
\r
3420 vuint16_t TCA:1; /* Tx Conflict on channel A */
\r
3425 typedef struct uMB_HEADER /* message buffer header */
\r
3427 F_HEADER_t FRAME_HEADER;
\r
3428 vuint16_t DATA_OFFSET;
\r
3429 S_STATUS_t SLOT_STATUS;
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3432 /* Define memories */
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3434 #define SRAM_START 0x40000000
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3435 #define SRAM_SIZE 0x10000
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3436 #define SRAM_END 0x4000FFFF
\r
3438 #define FLASH_START 0x0
\r
3439 #define FLASH_SIZE 0x100000
\r
3440 #define FLASH_END 0xFFFFF
\r
3442 /* Define instances of modules */
\r
3443 //#define PBRIDGE_A (*( volatile struct PBRIDGE_A_tag *) 0xC3F00000)
\r
3444 #define MPU (*( volatile struct MPU_tag *) 0xFFF10000)
\r
3445 #define SEMA4 (*( volatile struct SEMA4_tag *) 0xFFF14000)
\r
3447 #define MCM (*( volatile struct MCM_tag *) 0xFFF40000)
\r
3448 #define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000)
\r
3449 #define INTC (*( volatile struct INTC_tag *) 0xFFF48000)
\r
3451 #define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000)
\r
3453 #define I2C (*( volatile struct I2C_tag *) 0xFFF88000)
\r
3455 #define DSPI_A (*( volatile struct DSPI_tag *) 0xFFF90000)
\r
3456 #define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000)
\r
3457 #define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000)
\r
3458 #define DSPI_D (*( volatile struct DSPI_tag *) 0xFFF9C000)
\r
3460 #define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFA0000)
\r
3461 #define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFA4000)
\r
3462 #define ESCI_C (*( volatile struct ESCI_tag *) 0xFFFA8000)
\r
3463 #define ESCI_D (*( volatile struct ESCI_tag *) 0xFFFAC000)
\r
3464 #define ESCI_E (*( volatile struct ESCI_tag *) 0xFFFB0000)
\r
3465 #define ESCI_F (*( volatile struct ESCI_tag *) 0xFFFB4000)
\r
3466 #define ESCI_G (*( volatile struct ESCI_tag *) 0xFFFB8000)
\r
3467 #define ESCI_H (*( volatile struct ESCI_tag *) 0xFFFBC000)
\r
3469 #define CAN_A (*( volatile struct FLEXCAN_tag *) 0xFFFC0000)
\r
3470 #define CAN_B (*( volatile struct FLEXCAN_tag *) 0xFFFC4000)
\r
3471 #define CAN_C (*( volatile struct FLEXCAN_tag *) 0xFFFC8000)
\r
3472 #define CAN_D (*( volatile struct FLEXCAN_tag *) 0xFFFCC000)
\r
3473 #define CAN_E (*( volatile struct FLEXCAN_tag *) 0xFFFD0000)
\r
3474 #define CAN_F (*( volatile struct FLEXCAN_tag *) 0xFFFD4000)
\r
3475 #define FR (*( volatile struct FR_tag *) 0xFFFD8000)
\r
3476 #define DMAMUX (*( volatile struct DMAMUX_tag *) 0xFFFDC000)
\r
3477 #define PIT (*( volatile struct PIT_tag *) 0xFFFE0000)
\r
3478 #define EMIOS (*( volatile struct EMIOS_tag *) 0xFFFE4000)
\r
3479 #define SIU (*( volatile struct SIU_tag *) 0xFFFE8000)
\r
3480 #define CRP (*( volatile struct CRP_tag *) 0xFFFEC000)
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3481 #define FMPLL (*( volatile struct FMPLL_tag *) 0xFFFF0000)
\r
3482 #define EBI (*( volatile struct EBI_tag *) 0xFFFF4000)
\r
3483 #define FLASH (*( volatile struct FLASH_tag *) 0xFFFF8000)
\r
3489 #ifdef __cplusplus
\r
3492 #endif /* ifdef _MPC5516_H */
\r
projects / arc.git / blob