1 /* -------------------------------- Arctic Core ------------------------------
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2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
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4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
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6 * This source code is free software; you can redistribute it and/or modify it
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7 * under the terms of the GNU General Public License version 2 as published by the
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8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
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10 * This program is distributed in the hope that it will be useful, but
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11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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14 * -------------------------------- Arctic Core ------------------------------*/
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18 #include "mpc55xx.h"
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21 #include "CanIf_Cbk.h"
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23 #if defined(USE_DEM)
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36 /* CONFIGURATION NOTES
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37 * ------------------------------------------------------------------
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38 * - CanHandleType must be CAN_ARC_HANDLE_TYPE_BASIC
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39 * i.e. CanHandleType=CAN_ARC_HANDLE_TYPE_FULL NOT supported
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40 * i.e CanIdValue is NOT supported
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41 * - All CanXXXProcessing must be CAN_ARC_PROCESS_TYPE_INTERRUPT
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42 * ie CAN_ARC_PROCESS_TYPE_POLLED not supported
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43 * - To select the Mailboxes to use in the CAN controller use Can_Arc_MbMask
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44 * - HOH's for Tx are global and Rx are for each controller
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45 * - CanControllerTimeQuanta is NOT used. The other CanControllerXXX selects
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46 * the proper time-quanta
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47 * - Can_Arc_MbMask for Tx HOH must NOT overlap Can_Arc_MbMask for Rx.
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48 * - ONLY global mask is supported( NOT 14,15 and individual )
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49 * - Numbering the CanObjectId for Tx:
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50 * To do this correctly there are a number of things that are good to know
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51 * 1. HTH's have unique numbers.
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52 * 2. One HTH/HRH is maped to one HOH
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53 * 3. The extension Can_Arc_MbMask binds FULL CAN boxes together.
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58 * ---------------------
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63 * 17 | The use of Can_Arc_MbMask=0x000f0000 binds these to HTH 16
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64 * 18 | ( bits 16 to 19 set here )
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72 * C - Controller number
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76 /* IMPLEMENTATION NOTES
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77 * -----------------------------------------------
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78 * - A HOH us unique for a controller( not a config-set )
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79 * - Hrh's are numbered for each controller from 0
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80 * - HOH is numbered for each controller in sequences of 0-31
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81 * ( since we have 6 controllers and Hth is only uint8( See Can_Write() proto )
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82 * - loopback in HW NOT supported
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83 * - 32 of 64 boxes supported ( limited by Hth type )
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84 * - Fifo in HW NOT supported
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88 * -----------------------------------------------
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89 * - Can Hardware unit - One or multiple Can controllers of the same type.
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90 * - Hrh - HOH with receive definitions
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91 * - Hth - HOH with transmit definitions
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96 * ------------------------------------------------------------------
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97 * This controller should really be called FlexCan+ or something because
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98 * it's enhanced with:
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99 * - A RX Fifo !!!!! ( yep, it's fantastic ;) )
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100 * - A better matching process. From 25.4.4
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101 * "By programming more than one MB with the same ID, received messages will
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102 * be queued into the MBs. The CPU can examine the time stamp field of the
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103 * MBs to determine the order in which the messages arrived."
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105 * Soo, now it seems that Freescale have finally done something right.
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108 //-------------------------------------------------------------------
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110 // Number of mailboxes used for each controller ( power of 2 only )
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111 // ( It's NOT supported to set this to 64 )
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112 #define MAX_NUM_OF_MAILBOXES 32
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114 #if defined(CFG_MPC5567)
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115 #define GET_CONTROLLER(_controller) \
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116 ((struct FLEXCAN2_tag *)(0xFFFC0000 + 0x4000*(_controller)))
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118 #define GET_CONTROLLER(_controller) \
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119 ((struct FLEXCAN_tag *)(0xFFFC0000 + 0x4000*(_controller)))
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122 #define GET_CONTROLLER_CONFIG(_controller) \
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123 &Can_Global.config->CanConfigSet->CanController[(_controller)]
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125 #define GET_CALLBACKS() \
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126 (Can_Global.config->CanConfigSet->CanCallbacks)
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128 #define GET_PRIVATE_DATA(_controller) \
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129 &CanUnit[_controller]
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131 #define GET_CONTROLLER_CNT() (CAN_CONTROLLER_CNT)
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133 #define INSTALL_HANDLER4(_name, _can_entry, _vector, _priority, _app)\
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135 ISR_INSTALL_ISR2(_name, _can_entry, _vector+0, _priority, _app); \
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136 ISR_INSTALL_ISR2(_name, _can_entry, _vector+1, _priority, _app); \
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137 ISR_INSTALL_ISR2(_name, _can_entry, _vector+2, _priority, _app); \
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138 ISR_INSTALL_ISR2(_name, _can_entry, _vector+3, _priority, _app); \
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140 #define INSTALL_HANDLER16(_name, _can_entry, _vector, _priority, _app)\
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142 INSTALL_HANDLER4(_name, _can_entry, _vector+0, _priority, _app); \
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143 INSTALL_HANDLER4(_name, _can_entry, _vector+4, _priority, _app); \
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144 INSTALL_HANDLER4(_name, _can_entry, _vector+8, _priority, _app); \
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145 INSTALL_HANDLER4(_name, _can_entry, _vector+12,_priority, _app); \
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147 //-------------------------------------------------------------------
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149 #if ( CAN_DEV_ERROR_DETECT == STD_ON )
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150 #define VALIDATE(_exp,_api,_err ) \
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152 Det_ReportError(MODULE_ID_CAN,0,_api,_err); \
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153 return CAN_NOT_OK; \
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156 #define VALIDATE_NO_RV(_exp,_api,_err ) \
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158 Det_ReportError(MODULE_ID_CAN,0,_api,_err); \
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162 #define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x, _y, _z, _q)
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164 #define VALIDATE(_exp,_api,_err )
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165 #define VALIDATE_NO_RV(_exp,_api,_err )
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166 #define DET_REPORTERROR(_x,_y,_z,_q)
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169 #if defined(USE_DEM)
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170 #define VALIDATE_DEM_NO_RV(_exp,_err ) \
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172 Dem_ReportErrorStatus(_err, DEM_EVENT_STATUS_FAILED); \
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176 #define VALIDATE_DEM_NO_RV(_exp,_err )
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179 //-------------------------------------------------------------------
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181 // Message box status defines
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182 #define MB_TX_ONCE 0xc
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183 #define MB_INACTIVE 0x8
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185 #define MB_ABORT 0x9
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187 //-------------------------------------------------------------------
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192 } Can_DriverStateType;
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198 vuint32_t TWRNINT:1;
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199 vuint32_t RWRNINT:1;
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200 vuint32_t BIT1ERR:1;
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201 vuint32_t BIT0ERR:1;
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202 vuint32_t ACKERR:1;
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203 vuint32_t CRCERR:1;
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204 vuint32_t FRMERR:1;
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205 vuint32_t STFERR:1;
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210 vuint32_t FLTCONF:2;
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212 vuint32_t BOFFINT:1;
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213 vuint32_t ERRINT:1;
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214 vuint32_t WAKINT:1;
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216 } ESRType; /* Error and Status Register */
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218 #if defined(CFG_MPC5567)
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219 typedef struct FLEXCAN2_tag flexcan_t;
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221 typedef struct FLEXCAN_tag flexcan_t;
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224 // Mapping between HRH and Controller//HOH
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225 typedef struct Can_Arc_ObjectHOHMapStruct
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227 uint32 HxHRef; // Reference to HRH or HTH
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228 CanControllerIdType CanControllerRef; // Reference to controller
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229 const Can_HardwareObjectType* CanHOHRef; // Reference to HOH.
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230 } Can_Arc_ObjectHOHMapType;
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232 /* Type for holding global information used by the driver */
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234 Can_DriverStateType initRun;
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237 const Can_ConfigType *config;
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239 // One bit for each channel that is configured.
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240 // Used to determine if validity of a channel
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242 // 0 - NOT configured
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244 // Maps the a channel id to a configured channel id
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245 uint8 channelMap[CAN_CONTROLLER_CNT];
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247 // This is a map that maps the HTH:s with the controller and Hoh. It is built
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248 // during Can_Init and is used to make things faster during a transmit.
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249 Can_Arc_ObjectHOHMapType CanHTHMap[NUM_OF_HTHS];
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253 Can_GlobalType Can_Global =
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255 .initRun = CAN_UNINIT,
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259 /* Type for holding information about each controller */
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261 CanIf_ControllerModeType state;
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263 // Interrupt masks that is for all Mb's in this controller
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264 uint32 Can_Arc_RxMbMask;
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265 uint32 Can_Arc_TxMbMask;
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267 // Used at IFLG in controller at startup
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271 Can_Arc_StatisticsType stats;
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273 // Data stored for Txconfirmation callbacks to CanIf
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274 PduIdType swPduHandles[MAX_NUM_OF_MAILBOXES];
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279 Can_UnitType CanUnit[CAN_CONTROLLER_CNT] =
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282 .state = CANIF_CS_UNINIT,
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284 .state = CANIF_CS_UNINIT,
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286 #if defined(MPC5516) || defined(MPC5517) || defined(CFG_MPC5567)
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288 .state = CANIF_CS_UNINIT,
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290 .state = CANIF_CS_UNINIT,
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292 .state = CANIF_CS_UNINIT,
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295 #if defined(MPC5516) || defined(MPC5517)
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297 .state = CANIF_CS_UNINIT,
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303 //-------------------------------------------------------------------
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305 //-------------------------------------------------------------------
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307 * Function that finds the Hoh( HardwareObjectHandle ) from a Hth
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308 * A HTH may connect to one or several HOH's. Just find the first one.
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310 * @param hth The transmit handle
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311 * @returns Ptr to the Hoh
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313 static const Can_HardwareObjectType * Can_FindHoh( Can_Arc_HTHType hth , uint32* controller)
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315 const Can_HardwareObjectType *hohObj;
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316 const Can_Arc_ObjectHOHMapType *map;
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317 const Can_ControllerConfigType *canHwConfig;
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319 map = &Can_Global.CanHTHMap[hth];
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321 // Verify that this is the correct map
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322 if (map->HxHRef != hth)
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324 DET_REPORTERROR(MODULE_ID_CAN, 0, 0x6, CAN_E_PARAM_HANDLE);
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327 canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[map->CanControllerRef]);
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329 hohObj = map->CanHOHRef;
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331 // Verify that this is the correct Hoh type
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332 if ( hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)
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334 *controller = map->CanControllerRef;
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338 DET_REPORTERROR(MODULE_ID_CAN, 0, 0x6, CAN_E_PARAM_HANDLE);
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343 //-------------------------------------------------------------------
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345 static void Can_Isr( int unit );
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346 static void Can_Err( int unit );
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347 static void Can_BusOff( int unit );
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349 void Can_A_Isr( void ) { Can_Isr(CAN_CTRL_A); }
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350 void Can_B_Isr( void ) { Can_Isr(CAN_CTRL_B); }
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351 #if defined(MPC5516) || defined(MPC5517) || defined(MPC5567)
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352 void Can_C_Isr( void ) { Can_Isr(CAN_CTRL_C); }
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353 void Can_D_Isr( void ) { Can_Isr(CAN_CTRL_D); }
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354 void Can_E_Isr( void ) { Can_Isr(CAN_CTRL_E); }
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356 #if defined(MPC5516) || defined(MPC5517)
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357 void Can_F_Isr( void ) { Can_Isr(CAN_CTRL_F); }
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360 void Can_A_Err( void ) { Can_Err(CAN_CTRL_A); }
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361 void Can_B_Err( void ) { Can_Err(CAN_CTRL_B); }
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362 #if defined(MPC5516) || defined(MPC5517) || defined(MPC5567)
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363 void Can_C_Err( void ) { Can_Err(CAN_CTRL_C); }
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364 void Can_D_Err( void ) { Can_Err(CAN_CTRL_D); }
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365 void Can_E_Err( void ) { Can_Err(CAN_CTRL_E); }
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367 #if defined(MPC5516) || defined(MPC5517)
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368 void Can_F_Err( void ) { Can_Err(CAN_CTRL_F); }
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371 void Can_A_BusOff( void ) { Can_BusOff(CAN_CTRL_A); }
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372 void Can_B_BusOff( void ) { Can_BusOff(CAN_CTRL_B); }
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373 #if defined(MPC5516) || defined(MPC5517) || defined(MPC5567)
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374 void Can_C_BusOff( void ) { Can_BusOff(CAN_CTRL_C); }
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375 void Can_D_BusOff( void ) { Can_BusOff(CAN_CTRL_D); }
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376 void Can_E_BusOff( void ) { Can_BusOff(CAN_CTRL_E); }
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378 #if defined(MPC5516) || defined(MPC5517)
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379 void Can_F_BusOff( void ) { Can_BusOff(CAN_CTRL_F); }
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381 //-------------------------------------------------------------------
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385 * Hardware error ISR for CAN
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387 * @param unit CAN controller number( from 0 )
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390 static void Can_Err( int unit ) {
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391 flexcan_t *canHw = GET_CONTROLLER(unit);
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392 Can_Arc_ErrorType err;
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396 esr.R = canHw->ESR.R;
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398 err.B.ACKERR = esr.B.ACKERR;
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399 err.B.BIT0ERR = esr.B.BIT0ERR;
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400 err.B.BIT1ERR = esr.B.BIT1ERR;
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401 err.B.CRCERR = esr.B.CRCERR;
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402 err.B.FRMERR = esr.B.FRMERR;
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403 err.B.STFERR = esr.B.STFERR;
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404 err.B.RXWRN = esr.B.RXWRN;
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405 err.B.TXWRN = esr.B.TXWRN;
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407 if (GET_CALLBACKS()->Arc_Error != NULL)
\r
409 GET_CALLBACKS()->Arc_Error(unit, err );
\r
412 canHw->ESR.B.ERRINT = 1;
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416 // Uses 25.4.5.1 Transmission Abort Mechanism
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417 static void Can_AbortTx( flexcan_t *canHw, Can_UnitType *canUnit ) {
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421 // Find our Tx boxes.
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422 mbMask = canUnit->Can_Arc_TxMbMask;
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424 // Loop over the Mb's set to abort
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425 for (; mbMask; mbMask&=~(1<<mbNr)) {
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426 mbNr = ilog2(mbMask);
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428 canHw->BUF[mbNr].CS.B.CODE = MB_ABORT;
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431 if( canHw->BUF[mbNr].CS.B.CODE != MB_ABORT ) {
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434 // it's not sent... or being sent.
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435 // Just wait for it
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437 while( canHw->IFRL.R == (1<<mbNr) )
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446 // Ack tx interrupts
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447 canHw->IFRL.R = canUnit->Can_Arc_TxMbMask;
\r
448 canUnit->iflagStart = canUnit->Can_Arc_TxMbMask;
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451 //-------------------------------------------------------------------
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454 * BussOff ISR for CAN
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456 * @param unit CAN controller number( from 0 )
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458 static void Can_BusOff( int unit ) {
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459 flexcan_t *canHw = GET_CONTROLLER(unit);
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460 Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);
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461 Can_Arc_ErrorType err;
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464 if ( canHw->ESR.B.TWRNINT )
\r
466 err.B.TXWRN = canHw->ESR.B.TXWRN;
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467 canUnit->stats.txErrorCnt++;
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468 canHw->ESR.B.TWRNINT = 1;
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471 if ( canHw->ESR.B.RWRNINT )
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473 err.B.RXWRN = canHw->ESR.B.RXWRN;
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474 canUnit->stats.rxErrorCnt++;
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475 canHw->ESR.B.RWRNINT = 1;
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480 if (GET_CALLBACKS()->Arc_Error != NULL)
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482 GET_CALLBACKS()->Arc_Error( unit, err );
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486 if( canHw->ESR.B.BOFFINT ) {
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488 canUnit->stats.boffCnt++;
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489 if (GET_CALLBACKS()->ControllerBusOff != NULL)
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491 GET_CALLBACKS()->ControllerBusOff(unit);
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493 Can_SetControllerMode(unit, CAN_T_STOP); // CANIF272
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495 canHw->ESR.B.BOFFINT = 1;
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497 Can_AbortTx( canHw, canUnit ); // CANIF273
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501 //-------------------------------------------------------------------
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504 * ISR for CAN. Normal Rx/Tx operation
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506 * @param unit CAN controller number( from 0 )
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508 static void Can_Isr(int unit) {
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510 flexcan_t *canHw= GET_CONTROLLER(unit);
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511 const Can_ControllerConfigType *canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[unit]);
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512 uint32 iFlagLow = canHw->IFRL.R;
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513 Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);
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515 // Read interrupt flags to seeTxConfirmation what interrupt triggered the interrupt
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516 if (iFlagLow & canHw->IMRL.R) {
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519 #if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S)
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521 // FIFO code NOT tested
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522 if (canHw->MCR.B.FEN) {
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525 if (iFlagLow & (1<<7)) {
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526 canUnit->stats.fifoOverflow++;
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527 canHw->IFRL.B.BUF07I = 1;
\r
531 if (iFlagLow & (1<<6)) {
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532 canUnit->stats.fifoWarning++;
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533 canHw->IFRL.B.BUF06I = 1;
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536 // Pop fifo "realtime"
\r
537 while (canHw->IFRL.B.BUF05I) {
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539 // TODO MAHI: Must read the entire data-buffer to unlock??
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540 if (GET_CALLBACKS()->RxIndication != NULL)
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542 GET_CALLBACKS()->RxIndication((-1), canHw->BUF[0].ID.B.EXT_ID,
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543 canHw->BUF[0].CS.B.LENGTH, (uint8 *)&canHw->BUF[0].DATA.W[0] );
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545 // Clear the interrupt
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546 canHw->IFRL.B.BUF05I = 1;
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553 const Can_HardwareObjectType *hohObj;
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560 // Loop over all the Hoh's
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564 hohObj= canHwConfig->Can_Arc_Hoh;
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569 mbMask = hohObj->Can_Arc_MbMask & iFlagLow;
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571 if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)
\r
573 // Loop over the Mb's for this Hoh
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574 for (; mbMask; mbMask&=~(1<<mbNr)) {
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575 mbNr = ilog2(mbMask);
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577 // Do the necessary dummy reads to keep controller happy
\r
578 data = canHw->BUF[mbNr].CS.R;
\r
579 data = canHw->BUF[mbNr].DATA.W[0];
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581 // According to autosar MSB shuould be set if extended
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582 if (hohObj->CanIdType == CAN_ID_TYPE_EXTENDED) {
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583 id = canHw->BUF[mbNr].ID.R;
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586 id = canHw->BUF[mbNr].ID.B.STD_ID;
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589 if (GET_CALLBACKS()->RxIndication != NULL)
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591 GET_CALLBACKS()->RxIndication(hohObj->CanObjectId,
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593 canHw->BUF[mbNr].CS.B.LENGTH,
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594 (uint8 *)&canHw->BUF[mbNr].DATA.W[0] );
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596 // Increment statistics
\r
597 canUnit->stats.rxSuccessCnt++;
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599 // unlock MB (dummy read timer)
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600 (void)canHw->TIMER.R;
\r
603 canHw->IFRL.R = (1<<mbNr);
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606 } while ( !hohObj->Can_Arc_EOL);
\r
609 hohObj= canHwConfig->Can_Arc_Hoh;
\r
614 if (hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)
\r
616 mbMask = hohObj->Can_Arc_MbMask & iFlagLow;
\r
618 // Loop over the Mb's for this Hoh
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619 for (; mbMask; mbMask&=~(1<<mbNr)) {
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620 mbNr = ilog2(mbMask);
\r
622 if (GET_CALLBACKS()->TxConfirmation != NULL)
\r
624 GET_CALLBACKS()->TxConfirmation(canUnit->swPduHandles[mbNr]);
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626 canUnit->swPduHandles[mbNr] = 0; // Is this really necessary ??
\r
629 canUnit->iflagStart |= (1<<mbNr);
\r
630 canHw->IFRL.R = (1<<mbNr);
\r
633 } while ( !hohObj->Can_Arc_EOL);
\r
636 // Note! Over 32 boxes is not implemented
\r
637 // Other reasons that we end up here
\r
638 // - Interupt on a masked box
\r
641 if (canHwConfig->Can_Arc_Fifo) {
\r
644 * Do not enable RxFIFO. See [Freescale Device Errata MPC5510ACE, Rev. 10 APR 2009, errata ID: 14593].
\r
648 * NOT tested at all
\r
650 while (canHw->IFRL.B.BUF05I) {
\r
652 // TODO MAHI: Must read the entire data-buffer to unlock??
\r
653 if (GET_CALLBACKS()->RxIndication != NULL)
\r
655 GET_CALLBACKS()->RxIndication((-1), canHw->BUF[0].ID.B.EXT_ID,
\r
656 canHw->BUF[0].CS.B.LENGTH, (uint8 *)&canHw->BUF[0].DATA.W[0] );
\r
658 // Increment statistics
\r
659 canUnit->stats.rxSuccessCnt++;
\r
661 // Clear the interrupt
\r
662 canHw->IFRL.B.BUF05I = 1;
\r
667 //-------------------------------------------------------------------
\r
669 #define INSTALL_HANDLER4(_name,_can_entry, _vector,_priority,_app)\
\r
670 ISR_INSTALL_ISR2(_name,_can_entry, _vector+0,_priority,_app) \
\r
671 ISR_INSTALL_ISR2(_name,_can_entry, _vector+1,_priority,_app) \
\r
672 ISR_INSTALL_ISR2(_name,_can_entry, _vector+2,_priority,_app) \
\r
673 ISR_INSTALL_ISR2(_name,_can_entry, _vector+3,_priority,_app)
\r
675 #define INSTALL_HANDLER16(_name,_can_entry, _vector,_priority,_app)\
\r
676 INSTALL_HANDLER4(_name,_can_entry, _vector+0,_priority,_app) \
\r
677 INSTALL_HANDLER4(_name,_can_entry, _vector+4,_priority,_app) \
\r
678 INSTALL_HANDLER4(_name,_can_entry, _vector+8,_priority,_app) \
\r
679 INSTALL_HANDLER4(_name,_can_entry, _vector+12,_priority,_app)
\r
681 // This initiates ALL can controllers
\r
682 void Can_Init( const Can_ConfigType *config ) {
\r
683 Can_UnitType *canUnit;
\r
684 const Can_ControllerConfigType *canHwConfig;
\r
687 VALIDATE_NO_RV( (Can_Global.initRun == CAN_UNINIT), 0x0, CAN_E_TRANSITION );
\r
688 VALIDATE_NO_RV( (config != NULL ), 0x0, CAN_E_PARAM_POINTER );
\r
691 Can_Global.config = config;
\r
692 Can_Global.initRun = CAN_READY;
\r
695 for (int configId=0; configId < CAN_ARC_CTRL_CONFIG_CNT; configId++) {
\r
696 canHwConfig = GET_CONTROLLER_CONFIG(configId);
\r
697 ctlrId = canHwConfig->CanControllerId;
\r
699 // Assign the configuration channel used later..
\r
700 Can_Global.channelMap[canHwConfig->CanControllerId] = configId;
\r
701 Can_Global.configured |= (1<<ctlrId);
\r
703 canUnit = GET_PRIVATE_DATA(ctlrId);
\r
704 canUnit->state = CANIF_CS_STOPPED;
\r
706 canUnit->lock_cnt = 0;
\r
709 memset(&canUnit->stats, 0, sizeof(Can_Arc_StatisticsType));
\r
711 Can_InitController(ctlrId, canHwConfig);
\r
713 // Loop through all Hoh:s and map them into the HTHMap
\r
714 const Can_HardwareObjectType* hoh;
\r
715 hoh = canHwConfig->Can_Arc_Hoh;
\r
721 if (hoh->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)
\r
723 Can_Global.CanHTHMap[hoh->CanObjectId].CanControllerRef = canHwConfig->CanControllerId;
\r
724 Can_Global.CanHTHMap[hoh->CanObjectId].CanHOHRef = hoh;
\r
725 Can_Global.CanHTHMap[hoh->CanObjectId].HxHRef = hoh->CanObjectId;
\r
727 } while (!hoh->Can_Arc_EOL);
\r
730 // Could install handlers depending on HW objects to trap more errors
\r
731 // in configuration
\r
732 switch( canHwConfig->CanControllerId ) {
\r
734 ISR_INSTALL_ISR2( "Can", Can_A_BusOff, FLEXCAN_A_ESR_BOFF_INT, 2, 0);
\r
735 ISR_INSTALL_ISR2( "Can", Can_A_Err, FLEXCAN_A_ESR_ERR_INT, 2, 0 );
\r
736 INSTALL_HANDLER16( "Can", Can_A_Isr, FLEXCAN_A_IFLAG1_BUF0I, 2, 0 );
\r
737 ISR_INSTALL_ISR2( "Can", Can_A_Isr, FLEXCAN_A_IFLAG1_BUF31_16I, 2, 0 );
\r
740 ISR_INSTALL_ISR2( "Can", Can_B_BusOff, FLEXCAN_B_ESR_BOFF_INT, 2, 0 );
\r
741 ISR_INSTALL_ISR2( "Can", Can_B_Err, FLEXCAN_B_ESR_ERR_INT, 2, 0 );
\r
742 INSTALL_HANDLER16( "Can", Can_B_Isr, FLEXCAN_B_IFLAG1_BUF0I, 2, 0 );
\r
743 ISR_INSTALL_ISR2( "Can", Can_B_Isr, FLEXCAN_B_IFLAG1_BUF31_16I, 2, 0 );
\r
745 #if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(MPC5567)
\r
747 ISR_INSTALL_ISR2( "Can", Can_C_BusOff, FLEXCAN_C_ESR_BOFF_INT, 2, 0 );
\r
748 ISR_INSTALL_ISR2( "Can", Can_C_Err, FLEXCAN_C_ESR_ERR_INT, 2, 0 );
\r
749 INSTALL_HANDLER16( "Can", Can_C_Isr, FLEXCAN_C_IFLAG1_BUF0I, 2, 0 );
\r
750 ISR_INSTALL_ISR2( "Can", Can_C_Isr, FLEXCAN_C_IFLAG1_BUF31_16I, 2, 0 );
\r
753 ISR_INSTALL_ISR2( "Can", Can_D_BusOff, FLEXCAN_D_ESR_BOFF_INT, 2, 0 );
\r
754 ISR_INSTALL_ISR2( "Can", Can_D_Err, FLEXCAN_D_ESR_ERR_INT, 2, 0 );
\r
755 INSTALL_HANDLER16( "Can", Can_D_Isr, FLEXCAN_D_IFLAG1_BUF0I, 2, 0 );
\r
756 ISR_INSTALL_ISR2( "Can", Can_D_Isr, FLEXCAN_D_IFLAG1_BUF31_16I, 2, 0 );
\r
759 ISR_INSTALL_ISR2( "Can", Can_E_BusOff, FLEXCAN_E_ESR_BOFF_INT, 2, 0 );
\r
760 ISR_INSTALL_ISR2( "Can", Can_E_Err, FLEXCAN_E_ESR_ERR_INT, 2, 0 );
\r
761 INSTALL_HANDLER16( "Can", Can_E_Isr, FLEXCAN_E_IFLAG1_BUF0I, 2, 0 );
\r
762 ISR_INSTALL_ISR2( "Can", Can_E_Isr, FLEXCAN_E_IFLAG1_BUF31_16I, 2, 0 );
\r
765 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
\r
767 ISR_INSTALL_ISR2( "Can", Can_F_BusOff, FLEXCAN_F_ESR_BOFF_INT, 2, 0 );
\r
768 ISR_INSTALL_ISR2( "Can", Can_F_Err, FLEXCAN_F_ESR_ERR_INT, 2, 0 );
\r
769 INSTALL_HANDLER16( "Can", Can_F_Isr, FLEXCAN_F_IFLAG1_BUF0I, 2, 0 );
\r
770 ISR_INSTALL_ISR2( "Can", Can_F_Isr, FLEXCAN_F_IFLAG1_BUF31_16I, 2, 0 );
\r
780 // Unitialize the module
\r
783 Can_UnitType *canUnit;
\r
784 const Can_ControllerConfigType *canHwConfig;
\r
787 for (int configId=0; configId < CAN_ARC_CTRL_CONFIG_CNT; configId++) {
\r
788 canHwConfig = GET_CONTROLLER_CONFIG(configId);
\r
789 ctlrId = canHwConfig->CanControllerId;
\r
791 canUnit = GET_PRIVATE_DATA(ctlrId);
\r
792 canUnit->state = CANIF_CS_UNINIT;
\r
794 Can_DisableControllerInterrupts(ctlrId);
\r
796 canUnit->lock_cnt = 0;
\r
799 memset(&canUnit->stats, 0, sizeof(Can_Arc_StatisticsType));
\r
802 Can_Global.config = NULL;
\r
803 Can_Global.initRun = CAN_UNINIT;
\r
808 void Can_InitController( uint8 controller, const Can_ControllerConfigType *config) {
\r
816 Can_UnitType *canUnit;
\r
817 uint8 cId = controller;
\r
818 const Can_ControllerConfigType *canHwConfig;
\r
819 const Can_HardwareObjectType *hohObj;
\r
821 VALIDATE_NO_RV( (Can_Global.initRun == CAN_READY), 0x2, CAN_E_UNINIT );
\r
822 VALIDATE_NO_RV( (config != NULL ), 0x2,CAN_E_PARAM_POINTER);
\r
823 VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x2, CAN_E_PARAM_CONTROLLER );
\r
825 canUnit = GET_PRIVATE_DATA(controller);
\r
827 VALIDATE_NO_RV( (canUnit->state==CANIF_CS_STOPPED), 0x2, CAN_E_TRANSITION );
\r
829 canHw = GET_CONTROLLER(cId);
\r
830 canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[cId]);
\r
832 // Start this baby up
\r
833 canHw->MCR.B.MDIS = 0;
\r
835 // Wait for it to reset
\r
836 if( !SIMULATOR() ) {
\r
837 // Make a reset so we have a known state
\r
838 //canHw->MCR.B.SOFTRST = 1; /* commented out for step-in debug mode */
\r
839 //while( canHw->MCR.B.SOFTRST == 1);
\r
840 // Freeze to write all mem mapped registers ( see 25.4.8.1 )
\r
841 canHw->MCR.B.FRZ = 1;
\r
842 //while( canHw->MCR.B.FRZACK == 0);
\r
845 #if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S)
\r
847 // FIFO implemenation not tested
\r
848 if( config->Can_Arc_Fifo ) {
\r
849 canHw->MCR.B.FEN = 1; // Enable FIFO
\r
850 canHw->MCR.B.IDAM = 0; // We want extended id's to match with
\r
852 canHw->MCR.B.BCC = 1; // Enable all nice features
\r
854 /* Use Fsys derivate */
\r
855 canHw->CR.B.CLKSRC = 1;
\r
856 canHw->MCR.B.MAXMB = MAX_NUM_OF_MAILBOXES - 1;
\r
858 /* Disable selfreception */
\r
859 canHw->MCR.B.SRXDIS = !config->Can_Arc_Loopback;
\r
861 // Clock calucation
\r
862 // -------------------------------------------------------------------
\r
864 // * 1 TQ = Sclk period( also called SCK )
\r
865 // * Ftq = Fcanclk / ( PRESDIV + 1 ) = Sclk
\r
866 // ( Fcanclk can come from crystal or from the peripheral dividers )
\r
869 // TQ = 1/Ftq = (PRESDIV+1)/Fcanclk --> PRESDIV = (TQ * Fcanclk - 1 )
\r
870 // TQ is between 8 and 25
\r
872 // Calculate the number of timequanta's
\r
873 // From "Protocol Timing"( chap. 25.4.7.4 )
\r
874 tq1 = ( config->CanControllerPropSeg + config->CanControllerSeg1 + 2);
\r
875 tq2 = (config->CanControllerSeg2 + 1);
\r
876 tq = 1 + tq1 + tq2;
\r
878 // Check TQ limitations..
\r
879 VALIDATE_DEM_NO_RV(( (tq1>=4) && (tq1<=16)), CAN_E_TIMEOUT );
\r
880 VALIDATE_DEM_NO_RV(( (tq2>=2) && (tq2<=8)), CAN_E_TIMEOUT );
\r
881 VALIDATE_DEM_NO_RV(( (tq>8) && (tq<25 )), CAN_E_TIMEOUT );
\r
883 // Assume we're using the peripheral clock instead of the crystal.
\r
884 clock = McuE_GetPeripheralClock( (McuE_PeriperalClock_t) config->CanCpuClockRef );
\r
886 canHw->CR.B.PRESDIV = clock/(config->CanControllerBaudRate*1000*tq) - 1;
\r
887 canHw->CR.B.PROPSEG = config->CanControllerPropSeg;
\r
888 canHw->CR.B.PSEG1 = config->CanControllerSeg1;
\r
889 canHw->CR.B.PSEG2 = config->CanControllerSeg2;
\r
890 canHw->CR.B.SMP = 1; // 3 samples better than 1 ??
\r
891 canHw->CR.B.LPB = config->Can_Arc_Loopback;
\r
892 canHw->CR.B.BOFFREC = 1; // Disable bus off recovery
\r
894 #if defined(CFG_MPC5606S)
\r
895 SIU.PSMI[0].R = 0x00;
\r
896 SIU.PSMI[1].R = 0x00;
\r
899 #if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S)
\r
900 // Check if we use individual masks. If so accept anything(=0) for now
\r
901 if( canHw->MCR.B.BCC ) {
\r
902 i = (config->Can_Arc_Fifo ? 8 : 0 );
\r
904 canHw->RXIMR[i].R = 0;
\r
908 #if defined(CFG_MPC5567)
\r
909 // Enable individual Rx ID masking and the reception queue features.
\r
910 canHw->MCR.B.MBFEN = 1;
\r
913 if( config->Can_Arc_Fifo ) {
\r
914 // Clear ID's in FIFO also, MUST set extended bit here
\r
915 uint32_t *fifoId = (uint32_t*)(((uint8_t *)canHw)+0xe0);
\r
916 for(int k=0;k<8;k++) {
\r
917 fifoId[k] = 0x40000000; // accept extended frames
\r
921 // Mark all slots as inactive( depending on fifo )
\r
922 i = (config->Can_Arc_Fifo ? 8 : 0 );
\r
923 for(; i < 63; i++) {
\r
924 //canHw->BUF[i].CS.B.CODE = 0;
\r
925 canHw->BUF[i].CS.R = 0;
\r
926 canHw->BUF[i].ID.R = 0;
\r
930 /* Build a global interrupt/mb mask for all Hoh's */
\r
933 Can_FilterMaskType mask = 0xffffffff;
\r
936 hohObj = canHwConfig->Can_Arc_Hoh;
\r
941 mbMask = hohObj->Can_Arc_MbMask;
\r
944 if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)
\r
946 for(;mbMask;mbMask&=~(1<<mbNr)) {
\r
947 mbNr = ilog2(mbMask);
\r
948 canHw->BUF[mbNr].CS.B.CODE = MB_RX;
\r
949 if ( hohObj->CanIdType == CAN_ID_TYPE_EXTENDED )
\r
951 canHw->BUF[mbNr].CS.B.IDE = 1;
\r
952 #if defined(CFG_MPC5567)
\r
953 canHw->RXIMR[mbNr].B.MI = *hohObj->CanFilterMaskRef;
\r
955 canHw->BUF[mbNr].ID.R = *hohObj->CanFilterMaskRef; // Write 29-bit MB IDs
\r
960 canHw->BUF[mbNr].CS.B.IDE = 0;
\r
961 #if defined(CFG_MPC5567)
\r
962 canHw->RXIMR[mbNr].B.MI = *hohObj->CanFilterMaskRef;
\r
964 canHw->BUF[mbNr].ID.B.STD_ID = *hohObj->CanFilterMaskRef;
\r
969 // Add to global mask
\r
970 canUnit->Can_Arc_RxMbMask |= hohObj->Can_Arc_MbMask;
\r
971 if( hohObj->CanFilterMaskRef != NULL ) {
\r
972 mask &= *hohObj->CanFilterMaskRef;
\r
977 canUnit->Can_Arc_TxMbMask |= hohObj->Can_Arc_MbMask;
\r
979 } while( !hohObj->Can_Arc_EOL );
\r
981 #if defined(CFM_MPC5567)
\r
984 canHw->RXGMASK.R = mask;
\r
986 canHw->RX14MASK.R = 0;
\r
987 canHw->RX15MASK.R = 0;
\r
991 canUnit->iflagStart = canUnit->Can_Arc_TxMbMask;
\r
993 canUnit->state = CANIF_CS_STOPPED;
\r
994 Can_EnableControllerInterrupts(cId);
\r
1000 Can_ReturnType Can_SetControllerMode( uint8 controller, Can_StateTransitionType transition ) {
\r
1002 Can_ReturnType rv = CAN_OK;
\r
1003 VALIDATE( (controller < GET_CONTROLLER_CNT()), 0x3, CAN_E_PARAM_CONTROLLER );
\r
1005 Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);
\r
1007 VALIDATE( (canUnit->state!=CANIF_CS_UNINIT), 0x3, CAN_E_UNINIT );
\r
1008 canHw = GET_CONTROLLER(controller);
\r
1010 switch(transition )
\r
1013 canHw->MCR.B.FRZ = 0;
\r
1014 canHw->MCR.B.HALT = 0;
\r
1015 canUnit->state = CANIF_CS_STARTED;
\r
1016 imask_t state = McuE_EnterCriticalSection();
\r
1017 if (canUnit->lock_cnt == 0) // REQ CAN196
\r
1019 Can_EnableControllerInterrupts(controller);
\r
1021 McuE_ExitCriticalSection(state);
\r
1023 case CAN_T_WAKEUP: //CAN267
\r
1024 case CAN_T_SLEEP: //CAN258, CAN290
\r
1025 // Should be reported to DEM but DET is the next best
\r
1026 VALIDATE(canUnit->state == CANIF_CS_STOPPED, 0x3, CAN_E_TRANSITION);
\r
1029 canHw->MCR.B.FRZ = 1;
\r
1030 canHw->MCR.B.HALT = 1;
\r
1031 canUnit->state = CANIF_CS_STOPPED;
\r
1032 Can_AbortTx( canHw, canUnit ); // CANIF282
\r
1035 // Should be reported to DEM but DET is the next best
\r
1036 VALIDATE(canUnit->state == CANIF_CS_STOPPED, 0x3, CAN_E_TRANSITION);
\r
1043 void Can_DisableControllerInterrupts( uint8 controller )
\r
1045 Can_UnitType *canUnit;
\r
1048 VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x4, CAN_E_PARAM_CONTROLLER );
\r
1050 canUnit = GET_PRIVATE_DATA(controller);
\r
1052 VALIDATE_NO_RV( (canUnit->state!=CANIF_CS_UNINIT), 0x4, CAN_E_UNINIT );
\r
1054 imask_t state = McuE_EnterCriticalSection();
\r
1055 if(canUnit->lock_cnt > 0 )
\r
1057 // Interrupts already disabled
\r
1058 canUnit->lock_cnt++;
\r
1059 McuE_ExitCriticalSection(state);
\r
1062 canUnit->lock_cnt++;
\r
1063 McuE_ExitCriticalSection(state);
\r
1065 /* Don't try to be intelligent, turn everything off */
\r
1066 canHw = GET_CONTROLLER(controller);
\r
1068 /* Turn off the interrupt mailboxes */
\r
1069 canHw->IMRH.R = 0;
\r
1070 canHw->IMRL.R = 0;
\r
1072 /* Turn off the bus off/tx warning/rx warning and error */
\r
1073 canHw->MCR.B.WRNEN = 0; /* Disable warning int */
\r
1074 canHw->CR.B.ERRMSK = 0; /* Disable error interrupt */
\r
1075 canHw->CR.B.BOFFMSK = 0; /* Disable bus-off interrupt */
\r
1076 canHw->CR.B.TWRNMSK = 0; /* Disable Tx warning */
\r
1077 canHw->CR.B.RWRNMSK = 0; /* Disable Rx warning */
\r
1080 void Can_EnableControllerInterrupts( uint8 controller ) {
\r
1081 Can_UnitType *canUnit;
\r
1083 const Can_ControllerConfigType *canHwConfig;
\r
1084 VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x5, CAN_E_PARAM_CONTROLLER );
\r
1086 canUnit = GET_PRIVATE_DATA(controller);
\r
1088 VALIDATE_NO_RV( (canUnit->state!=CANIF_CS_UNINIT), 0x5, CAN_E_UNINIT );
\r
1090 imask_t state = McuE_EnterCriticalSection();
\r
1091 if( canUnit->lock_cnt > 1 )
\r
1093 // IRQ should still be disabled so just decrement counter
\r
1094 canUnit->lock_cnt--;
\r
1095 McuE_ExitCriticalSection(state);
\r
1097 } else if (canUnit->lock_cnt == 1)
\r
1099 canUnit->lock_cnt = 0;
\r
1101 McuE_ExitCriticalSection(state);
\r
1103 canHw = GET_CONTROLLER(controller);
\r
1105 canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[controller]);
\r
1107 canHw->IMRH.R = 0;
\r
1108 canHw->IMRL.R = 0;
\r
1110 if( canHwConfig->CanRxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {
\r
1111 /* Turn on the interrupt mailboxes */
\r
1112 canHw->IMRL.R = canUnit->Can_Arc_RxMbMask;
\r
1115 if( canHwConfig->CanTxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {
\r
1116 /* Turn on the interrupt mailboxes */
\r
1117 canHw->IMRL.R |= canUnit->Can_Arc_TxMbMask;
\r
1120 // BusOff here represents all errors and warnings
\r
1121 if( canHwConfig->CanBusOffProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {
\r
1122 canHw->MCR.B.WRNEN = 1; /* Turn On warning int */
\r
1124 canHw->CR.B.ERRMSK = 1; /* Enable error interrupt */
\r
1125 canHw->CR.B.BOFFMSK = 1; /* Enable bus-off interrupt */
\r
1126 canHw->CR.B.TWRNMSK = 1; /* Enable Tx warning */
\r
1127 canHw->CR.B.RWRNMSK = 1; /* Enable Rx warning */
\r
1133 Can_ReturnType Can_Write( Can_Arc_HTHType hth, Can_PduType *pduInfo ) {
\r
1136 Can_ReturnType rv = CAN_OK;
\r
1139 const Can_HardwareObjectType *hohObj;
\r
1140 uint32 controller;
\r
1143 VALIDATE( (Can_Global.initRun == CAN_READY), 0x6, CAN_E_UNINIT );
\r
1144 VALIDATE( (pduInfo != NULL), 0x6, CAN_E_PARAM_POINTER );
\r
1145 VALIDATE( (pduInfo->length <= 8), 0x6, CAN_E_PARAM_DLC );
\r
1146 VALIDATE( (hth < NUM_OF_HTHS ), 0x6, CAN_E_PARAM_HANDLE );
\r
1148 hohObj = Can_FindHoh(hth, &controller);
\r
1149 if (hohObj == NULL)
\r
1150 return CAN_NOT_OK;
\r
1152 Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);
\r
1154 canHw = GET_CONTROLLER(controller);
\r
1155 oldMsr = McuE_EnterCriticalSection();
\r
1156 iflag = canHw->IFRL.R & canUnit->Can_Arc_TxMbMask;
\r
1158 // check for any free box
\r
1159 // Normally we would just use the iflag to get the free box
\r
1160 // but that does not work the first time( iflag == 0 ) so we
\r
1161 // create one( iflagStart )
\r
1162 if( iflag | canUnit->iflagStart ) {
\r
1163 mbNr = ilog2((iflag | canUnit->iflagStart)); // find mb number
\r
1165 canHw->IFRL.R = (1<<mbNr);
\r
1166 canUnit->iflagStart &= ~(1<<mbNr);
\r
1168 // Setup message box type
\r
1169 if( hohObj->CanIdType == CAN_ID_TYPE_EXTENDED ) {
\r
1170 canHw->BUF[mbNr].CS.B.IDE = 1;
\r
1171 } else if ( hohObj->CanIdType == CAN_ID_TYPE_STANDARD ) {
\r
1172 canHw->BUF[mbNr].CS.B.IDE = 0;
\r
1174 // No support for mixed in this processor
\r
1179 canHw->BUF[mbNr].CS.B.CODE = MB_INACTIVE; // Hold the transmit buffer inactive
\r
1180 if( hohObj->CanIdType == CAN_ID_TYPE_EXTENDED ) {
\r
1181 canHw->BUF[mbNr].ID.R = pduInfo->id; // Write 29-bit MB IDs
\r
1183 assert( !(pduInfo->id & 0xfffff800) );
\r
1184 canHw->BUF[mbNr].ID.B.STD_ID = pduInfo->id;
\r
1187 #if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S)
\r
1188 canHw->BUF[mbNr].ID.B.PRIO = 1; // Set Local Priority
\r
1191 memset(&canHw->BUF[mbNr].DATA, 0, 8);
\r
1192 memcpy(&canHw->BUF[mbNr].DATA, pduInfo->sdu, pduInfo->length);
\r
1194 canHw->BUF[mbNr].CS.B.SRR = 1;
\r
1195 canHw->BUF[mbNr].CS.B.RTR = 0;
\r
1197 canHw->BUF[mbNr].CS.B.LENGTH = pduInfo->length;
\r
1198 canHw->BUF[mbNr].CS.B.CODE = MB_TX_ONCE; // Write tx once code
\r
1199 timer = canHw->TIMER.R; // Unlock Message buffers
\r
1201 canUnit->stats.txSuccessCnt++;
\r
1203 // Store pdu handle in unit to be used by TxConfirmation
\r
1204 canUnit->swPduHandles[mbNr] = pduInfo->swPduHandle;
\r
1209 McuE_ExitCriticalSection(oldMsr);
\r
1214 void Can_MainFunction_Read( void ) {
\r
1216 /* NOT SUPPORTED */
\r
1219 void Can_MainFunction_BusOff( void ) {
\r
1220 /* Bus-off polling events */
\r
1222 /* NOT SUPPORTED */
\r
1225 void Can_MainFunction_Wakeup( void ) {
\r
1226 /* Wakeup polling events */
\r
1228 /* NOT SUPPORTED */
\r
1233 * Get send/receive/error statistics for a controller
\r
1235 * @param controller The controller
\r
1236 * @param stats Pointer to data to copy statistics to
\r
1239 void Can_Arc_GetStatistics( uint8 controller, Can_Arc_StatisticsType *stats)
\r
1241 Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);
\r
1242 *stats = canUnit->stats;
\r