2 * Configuration of module: Port (Port_Cfg.h)
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4 * Created by: Arccore AB
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7 * Configured for (MCU): HCS12
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9 * Module vendor: ArcCore
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10 * Generator version: 2.0.2
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12 * Generated by Arctic Studio (http://arccore.com)
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13 * on Thu Mar 10 14:35:00 CET 2011
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17 #if !(((PORT_SW_MAJOR_VERSION == 1) && (PORT_SW_MINOR_VERSION == 0)) )
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18 #error Port: Configuration file expected BSW module version to be 1.0.*
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25 #include "Std_Types.h"
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28 /** Build version info API */
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29 #define PORT_VERSION_INFO_API STD_ON
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30 /** Enable Development Error Trace */
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31 #define PORT_DEV_ERROR_DETECT STD_ON
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32 /** Build change pin direction API */
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33 #define PORT_SET_PIN_DIRECTION_API STD_OFF
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34 /** Allow Pin mode changes during runtime (not avail on this CPU) */
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35 #define PORT_SET_PIN_MODE_API STD_OFF
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37 /** Parameter to enable/disable configuration on a port */
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38 #define PORTA_CONFIGURABLE STD_OFF
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39 #define PORTB_CONFIGURABLE STD_ON
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40 #define PORTE_CONFIGURABLE STD_OFF
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41 #define PORTK_CONFIGURABLE STD_OFF
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42 #define PORTH_CONFIGURABLE STD_ON
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43 #define PORTJ_CONFIGURABLE STD_ON
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44 #define PORTM_CONFIGURABLE STD_ON
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45 #define PORTP_CONFIGURABLE STD_ON
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46 #define PORTS_CONFIGURABLE STD_ON
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47 #define PORTT_CONFIGURABLE STD_ON
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49 #define PORT_A_BASE 0x0100
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50 #define PORT_B_BASE 0x0200
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51 #define PORT_E_BASE 0x0300
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52 #define PORT_K_BASE 0x0400
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53 #define PORT_H_BASE 0x0500
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54 #define PORT_J_BASE 0x0600
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55 #define PORT_M_BASE 0x0700
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56 #define PORT_P_BASE 0x0800
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57 #define PORT_S_BASE 0x0900
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58 #define PORT_T_BASE 0x0A00
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59 #define PORT_BITMASK 0x00FF
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60 #define PORT_BASEMASK 0xFF00;
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62 /** HW specific symbolic names of pins */
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66 PORT_PA0 = PORT_A_BASE,
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74 PORT_PB0 = PORT_B_BASE,
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82 PORT_PE0 = PORT_E_BASE,
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90 PORT_PH0 = PORT_H_BASE,
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98 PORT_PJ0 = PORT_J_BASE,
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106 PORT_PK0 = PORT_K_BASE,
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114 PORT_PM0 = PORT_M_BASE,
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122 PORT_PP0 = PORT_P_BASE,
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130 PORT_PS0 = PORT_S_BASE,
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138 PORT_PT0 = PORT_T_BASE,
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148 /** Top level configuration container */
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149 /** @req PORT073 */
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152 const uint8_t corePullUpRegister; // PUCR
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153 const uint8_t coreReducedDriveRegister; // RDRIV
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154 const uint8_t modeRoutingRegister; // MODRR
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158 * a direction (input or output)
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159 * a default out value
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160 * a mask that is 0 if the direction is allowed to change during runtime
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163 * a reduced drive conf (power saving)
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164 * a pull enable conf (enable pull-up/pull-down
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165 * a pull direction conf (pull-up or pull-down)
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166 * a wired mode (enable open drain outputs)
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168 #if ( PORTA_CONFIGURABLE == STD_ON )
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169 const uint8_t portADirection;
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170 const uint8_t portAOutValue;
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171 const uint8_t portAMask;
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174 #if ( PORTB_CONFIGURABLE == STD_ON )
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175 const uint8_t portBDirection;
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176 const uint8_t portBOutValue;
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177 const uint8_t portBMask;
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180 #if ( PORTE_CONFIGURABLE == STD_ON )
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181 const uint8_t portEDirection;
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182 const uint8_t portEOutValue;
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183 const uint8_t portEMask;
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186 #if ( PORTK_CONFIGURABLE == STD_ON )
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187 const uint8_t portKDirection;
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188 const uint8_t portKOutValue;
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189 const uint8_t portKMask;
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192 #if ( PORTH_CONFIGURABLE == STD_ON )
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193 const uint8_t portHDirection;
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194 const uint8_t portHOutValue;
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195 const uint8_t portHMask;
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196 const uint8_t portHPullEnableRegister;
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197 const uint8_t portHPullPolarityRegsiter;
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198 const uint8_t portHReducedDriveRegister;
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201 #if ( PORTJ_CONFIGURABLE == STD_ON )
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202 const uint8_t portJDirection;
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203 const uint8_t portJOutValue;
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204 const uint8_t portJMask;
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205 const uint8_t portJPullEnableRegister;
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206 const uint8_t portJPullPolarityRegsiter;
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207 const uint8_t portJReducedDriveRegister;
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210 #if ( PORTM_CONFIGURABLE == STD_ON )
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211 const uint8_t portMDirection;
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212 const uint8_t portMOutValue;
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213 const uint8_t portMMask;
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214 const uint8_t portMPullEnableRegister;
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215 const uint8_t portMPullPolarityRegsiter;
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216 const uint8_t portMWiredModeRegsiter;
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217 const uint8_t portMReducedDriveRegister;
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220 #if ( PORTP_CONFIGURABLE == STD_ON )
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221 const uint8_t portPDirection;
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222 const uint8_t portPOutValue;
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223 const uint8_t portPMask;
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224 const uint8_t portPPullEnableRegister;
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225 const uint8_t portPPullPolarityRegsiter;
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226 const uint8_t portPReducedDriveRegister;
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229 #if ( PORTS_CONFIGURABLE == STD_ON )
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230 const uint8_t portSDirection;
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231 const uint8_t portSOutValue;
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232 const uint8_t portSMask;
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233 const uint8_t portSPullEnableRegister;
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234 const uint8_t portSPullPolarityRegsiter;
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235 const uint8_t portSWiredModeRegsiter;
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236 const uint8_t portSReducedDriveRegister;
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239 #if ( PORTT_CONFIGURABLE == STD_ON )
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240 const uint8_t portTDirection;
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241 const uint8_t portTOutValue;
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242 const uint8_t portTMask;
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243 const uint8_t portTPullEnableRegister;
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244 const uint8_t portTPullPolarityRegsiter;
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245 const uint8_t portTReducedDriveRegister;
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249 /** Instance of the top level configuration container */
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250 extern const Port_ConfigType PortConfigData;
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252 #define PORT_PIN_NAME_SDA PORT_PJ6
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253 #define PORT_PIN_NAME_SCL PORT_PJ7
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254 #define PORT_PIN_NAME_TXD PORT_PM1
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255 #define PORT_PIN_NAME_RXD PORT_PM0
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256 #define PORT_PIN_NAME_PB0 PORT_PB0
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257 #define PORT_PIN_NAME_PB1 PORT_PB1
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258 #define PORT_PIN_NAME_PB2 PORT_PB2
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259 #define PORT_PIN_NAME_PB3 PORT_PB3
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260 #define PORT_PIN_NAME_PB4 PORT_PB4
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261 #define PORT_PIN_NAME_PB5 PORT_PB5
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262 #define PORT_PIN_NAME_PB6 PORT_PB6
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263 #define PORT_PIN_NAME_PB7 PORT_PB7
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264 #define PORT_PIN_NAME_PH0 PORT_PH0
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265 #define PORT_PIN_NAME_PH1 PORT_PH1
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266 #define PORT_PIN_NAME_PH2 PORT_PH2
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267 #define PORT_PIN_NAME_PH3 PORT_PH3
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268 #define PORT_PIN_NAME_PH4 PORT_PH4
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269 #define PORT_PIN_NAME_PH5 PORT_PH5
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270 #define PORT_PIN_NAME_PH6 PORT_PH6
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271 #define PORT_PIN_NAME_PH7 PORT_PH7
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272 #define PORT_PIN_NAME_PT0 PORT_PT0
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273 #define PORT_PIN_NAME_PT1 PORT_PT1
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274 #define PORT_PIN_NAME_BEEPER PORT_PT2
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275 #define PORT_PIN_NAME_PP0 PORT_PP0
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276 #define PORT_PIN_NAME_PP1 PORT_PP1
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277 #define PORT_PIN_NAME_RXD0 PORT_PS0
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278 #define PORT_PIN_NAME_TXD0 PORT_PS1
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279 #define PORT_PIN_NAME_RXD1 PORT_PS2
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280 #define PORT_PIN_NAME_TXD1 PORT_PS3
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281 #define PORT_PIN_NAME_PM6 PORT_PM6
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282 #define PORT_PIN_NAME_PM7 PORT_PM7
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283 #endif /*PORT_CFG_H_*/
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