1 /* -------------------------------- Arctic Core ------------------------------
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2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
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4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
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6 * This source code is free software; you can redistribute it and/or modify it
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7 * under the terms of the GNU General Public License version 2 as published by the
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8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
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10 * This program is distributed in the hope that it will be useful, but
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11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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14 * -------------------------------- Arctic Core ------------------------------*/
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21 .global g_pfnVectors
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22 .global Default_Handler
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34 * @brief This is the code that gets called when the processor first
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35 * starts execution following a reset event. Only the absolutely
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36 * necessary set is performed, after which the application
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37 * supplied main() routine is called.
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41 .section .text.Reset_Handler
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43 .type Reset_Handler, %function
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46 /* Set big endian state */
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49 /* Copy the data segment initializers from flash to SRAM */
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77 orr r12, r1, #0x0002
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80 orr r12, r1, #0x0007
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83 orr r12, r1, #0x000B
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86 orr r12, r1, #0x0003
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90 /* System level configuration */
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91 mrc p15,0,r11,c1,c0,0 /* Read current system configuration */
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92 mov r12, #0x40000000 /* Set THUMB instruction set mode for interrupts and exceptions */
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94 mcr p15,0,r12,c1,c0,0 /* Write new configuration */
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97 Init_Stack_Pointers:
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124 CopyInitializedData:
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125 ldr r0, =_sdata /* r0 holds start of data in ram */
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126 ldr r3, =_edata /* r3 holds end of data in ram */
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127 ldr r5, =_sidata /* r5 start of data in flash */
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128 movs r1, #0 /* r1 is the counter */
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132 ldr r4, [r5, r1] /* read current position in flash */
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133 str r4, [r0, r1] /* store current position in ram */
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134 adds r1, r1, #4 /* increment counter */
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137 adds r2, r0, r1 /* are we at the final position? */
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138 cmp r2, r3 /* ... */
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139 bcc CopyDataInit /* nope, continue */
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141 /* Fill zero areas */
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142 ldr r2, =_sbss /* r2 holds the start address */
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143 ldr r5, =_ebss /* r5 holds the end address */
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146 ldr r2, =_sstack /* r2 holds the start address */
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147 ldr r5, =_estack /* r5 holds the end address */
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150 /* Call the application's entry point.*/
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156 /* Zero fill the bss segment. */
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167 /* Go back to sys mode for easier debugging.
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168 Save link register*/
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170 /* We don't want to use the IRQ mode
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171 so swich back to sys mode. */
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174 /* Restore link register again */
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178 .size Reset_Handler, .-Reset_Handler
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181 * @brief This is the code that gets called when the processor receives an
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182 * unexpected interrupt. This simply enters an infinite loop, preserving
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183 * the system state for examination by a debugger.
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188 .section .text.Default_Handler,"ax",%progbits
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192 .size Default_Handler, .-Default_Handler
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195 /******************************************************************************
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196 * Interrupt and exception vectors. Vectors start at addr 0x0.
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197 ******************************************************************************/
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198 .section .int_vecs,"ax",%progbits
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199 .extern Irq_Handler
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201 b Reset_Handler /* Reset? */
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202 b Dummy_Irq /* Undef? */
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203 b Irq_Handler /* SVC, to be able to use SVC instruction. */
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204 b Dummy_Irq /* Prefetch */
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205 b Dummy_Irq /* data */
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206 b Dummy_Irq /* ? */
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207 b Irq_Handler /* IRQ */
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208 b Irq_Handler /* FIR */
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