[PSR] IRC_SR register values in interrupts

[Michal Sojka]

On Fri, Jan 12 2018, beranj25 at fel.cvut.cz wrote:
> Besides, in some cases (tens of hundred thousands interrupts) I read  
> zero from IRC_IRQ_MON, but interrupt source is setup to rising edge,  
> so I'd expect '1' every time.

There could be several reasons for this.

1) The interrupt is set pending at the time of rising edge. However the
   handler invocation can be delayed (as we measured in Task 6) so when
   the handler is executed, the triggering condition may no longer be
   true.

2) As far as I know, there are two possible sources of IRC interrupts.
   One is generated directly in the motor electronics (this signal
   should be visible via IRC_IRQ_MON), the second is generated in the
   FPGA (which is a port of the Zynq chip) based on IRC_A and IRC_B
   signals. I think that the example code uses the second signal for
   interrupt generation. Although both IRQ signals should be quite
   similar, there are some changes. I think that the IRQ pulses
   generated by FPGA are shorter.

Best regards,
-Michal Sojka