ML403

FPGA HW&SW development environment

Software

• Xilinx tools
  • ISE 9.2i -- package for FPGA HW design; compiles input (HDL, netlist, schematics) and optimizes output bitstream according to given user constraints (mainly timing and pin assignment). In our work, ISE programs are almost exclusively invoked by EDK tools.
  • EDK 9.2i -- package for FPGA HW&SW embedded system development; contains libraries of embedded computer IP cores and serves to glue HW FPGA cores together with software.
  • Chipscope 9.1i (optional) -- logic analyzer inside of FPGA. Dedicated IP core sends measured waveforms by JTAG to Chipscope analyzer, running on PC with GUI.
• open-source software
  • libusb-driver -- much better replacement/emulator of driver for Xilinx USB-JTAG adapter
  • gcc 4.3.2, binutils, glibc -- development of system-less as well as Linux SW for PowerPC, contained in Xilinx Virtex-4 hybrid FPGA
  • Linux 2.6.27-rc4 PowerPC kernel containing Xilinx Virtex support

Hardware

• Xilinx Virtex-4 XC4VFX12 hybrid FPGA IC on ML405 evaluation board

Xilinx FPGA HW&SW development

Running Linux on FPGA embedded system

System HW is created by XPS (Xilinx Platform Studio, the essential part of EDK). The system is composed of library IP cores: the main processor (actually a hard-core in case of PowerPC), peripherals (UART, Ethernet), clock modules, memory drivers and various bridges, and possibly also user developed HDL IP cores. XPS provides a way to instantiate each core once or more times in one system, to interconnect the cores either by defined interfaces (buses), or by generic named signals. Global clock is defined, which will imply timing constraints. Also a pin map is defined for signals, which should be pinned out of the FPGA package. For standard buses, XPS can also allocate memory resources and divide them between selected peripherals to avoid bus collision.

All the mentioned hardware description is stored in a single file, system.mhs. From this file, XPS can create netlists and then invoke several ISE tools, to compile whole hardware into an output bitstream.

XPS initial work flow to get HW running with Linux or a system-less software:

• Get an initial design either by copying a directory tree from a working one, or start it by XPS Base System Builder (GUI wizard).

Configuration of open-source software for Xilinx Virtex-4

Toolchain binaries for Debian

Invoke next line to add rtime cross-dev into packages sources list

echo deb ftp://rtime.felk.cvut.cz/debian unstable main >/etc/apt/sources.list.d/rtime-debs.list

Update packages cache (aptitude update) Check, that libmpfr1ldbl and libgmp3c2 packages are installed and select next packages

binutils-powerpc-elf
binutils-powerpc-linux-gnu
gcc-powerpc-elf
gcc-powerpc-linux-gnu
glibc-powerpc-linux-gnu

This tool-chain was compiled according to How to build GNU cross-compilers page.

Linux kernel and U-Boot sources

mkdir src
cd src
git clone  git://git.xilinx.com/u-boot-xlnx.git
git clone  git://git.xilinx.com/gen-mhs-devtree.git
git clone --reference /usr/src/linux-devel git://git.xilinx.com/linux-2.6-xlnx.git

mkdir -p build/ml403/linux
cd build/ml403/linux

U-Boot

http://xilinx.wikidot.com/u-boot

 make ml405_config
 make

PowerPC assembly caveats

Possible problems with "m" constrains [1]

The right use of "m" constrains requires evaluation of automatic update suffixes, use of "o" constrains should be safe

 asm volatile ("lwz%U1%X1 %0, %1":"=r"(val):"m"(*reg_p));