View source for XC2V1000-kit

This page describes "Virtes-II Demo Board" DS-BD-V2MB1000 from DS-KIT-MBLAZE-V2-SET by Memec.

Following instructions are verified on these systems:
* Ubuntu 10.10 - 64-bit


See also http://rtime.felk.cvut.cz/hw/index.php/XC2S100-kit


== ISE Design Suite ==

=== Installation ===

I recommend to use ISE 9.2 (NOT the WebPack edition!) as it is the last version supporting XC2V1000 which ID key can be obtained from their web page. Distribution also contains 64-bit linux binaries (which is not true for some newer versions).

Supported devices are: Virtex(E), Virtex-2(P), Virtex-4, Virtex-5, Spartan-2(E), Spartan-3(E,A,AN,ADSP).

However to install 64-bit version, appropriate setup (not the default) must be launched (at least in my case).
 $ ./ISE_DVD_92i/bin/lin64/setup


If floorplanner, pace or fpga_editor doesn't work for you and all required libraries are installed, probably DISPLAY variable is set to something like ":0.0" instead of ":0".

To correct this I have renamed all mentioned executable to *.bin and put this script in a place of each one:
 #!/bin/bash
 export DISPLAY=:0
 $0.bin $*

I you use ft2232 based JTAG cable and open-source drivers then you can accordingly rename impact executable and put script similar to the following one in a place of the original impact to force linker loading the open-source driver.
 #!/bin/bash
 LD_PRELOAD=/opt/Xilinx/usbjtag/libusb-driver-64.so $0.bin $*

Now, when you want to use Xilinx tools from command line, you have to only execute xilinx settings script in current shell:
 $ . /opt/Xilinx/9.2_64/settings.sh

=== Documentation ===

ISE Design Suite documentation does not describe everything (some command line arguments, etc.), but otherwise it's quite extensive and contains lot of useful information about xilinx devices, VHDL and Verilog codding, code examples of various entities (memories, FSMs, multipliers, ...) and much more.


== JTAG Cable ==

ISE Impact with driver from http://www.rmdir.de/~michael/xilinx/ and general FTDI 2232 based converter USB -> JTAG can be used. Download that driver and follow instructions in README file (I didn't have to configure udev). Then make sure the drive is preloaded when launching impact - see [[#ISE Design Suite|ISE Design Suite]] section.


== Editing & building ==

I recommend to use Emacs editor in conjuction with vhdl-mode, which is a very powerful tool. It is totaly incomparable with ISE IDE and I haven't found any other editor with similar capabilities. See http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html.

You should always download the newest version of vhdl-mode as there are some bugs fixed. Emacs 23.1.1 + vhdl-mode 3.33.28 works well for me.


== I/O Connections ==

  # file: Virtex2.ucf
  # I/O connections constraints file of DS-BD-V2MB1000 board
  
  #==============================================================================#
  # Clock & Reset                                                                #
  #==============================================================================#
  # Pins are fliped in manual
  NET "CLK_100MHz"        LOC = "B11" |     PERIOD =  10.0 ns LOW   5.0 ns;
  NET "CLK_24MHz"         LOC = "A11" |     PERIOD =  41.7 ns LOW  20.9 ns;
  
  # Reset is negated!
  NET "RESETn"            LOC = "B6";
  
  
  #==============================================================================#
  # 7-Segment Display                                                            #
  #==============================================================================#
  
  NET "DISPLAY1<0>"       LOC = "D9";
  NET "DISPLAY1<1>"       LOC = "C9";
  NET "DISPLAY1<2>"       LOC = "F11";
  NET "DISPLAY1<3>"       LOC = "F9";
  NET "DISPLAY1<4>"       LOC = "F10";
  NET "DISPLAY1<5>"       LOC = "D10";
  NET "DISPLAY1<6>"       LOC = "C10";
  
  NET "DISPLAY2<0>"       LOC = "B9";
  NET "DISPLAY2<1>"       LOC = "A8";
  NET "DISPLAY2<2>"       LOC = "B8";
  NET "DISPLAY2<3>"       LOC = "E7";
  NET "DISPLAY2<4>"       LOC = "E8";
  NET "DISPLAY2<5>"       LOC = "E10";
  NET "DISPLAY2<6>"       LOC = "E9";
  
  
  #==============================================================================#
  # Buttons & Switches                                                           #
  #==============================================================================#
  
  NET "BTN1"              LOC = "D7";
  NET "BTN2"              LOC = "A6";
  
  NET "DIP<1>"            LOC = "B4";
  NET "DIP<2>"            LOC = "A4";
  NET "DIP<3>"            LOC = "C4";
  NET "DIP<4>"            LOC = "C5";
  NET "DIP<5>"            LOC = "B5";
  NET "DIP<6>"            LOC = "A5";
  NET "DIP<7>"            LOC = "D6";
  NET "DIP<8>"            LOC = "C6";
  
  
  #==============================================================================#
  # RS-232 Port                                                                  #
  #==============================================================================#
  
  NET "TXD"               LOC = "A7";     # output from the board (from FPGA)
  NET "RXD"               LOC = "B7";     # input to the board (to FPGA)
  
  
  #==============================================================================#
  # DDR Memory Interface                                                         #
  #==============================================================================#
  
  NET "DDR_A<0>"          LOC = "B18";
  NET "DDR_A<1>"          LOC = "A18";
  NET "DDR_A<2>"          LOC = "B17";
  NET "DDR_A<3>"          LOC = "A17";
  NET "DDR_A<4>"          LOC = "N17";
  NET "DDR_A<5>"          LOC = "P18";
  NET "DDR_A<6>"          LOC = "P17";
  NET "DDR_A<7>"          LOC = "M18";
  NET "DDR_A<8>"          LOC = "M19";
  NET "DDR_A<9>"          LOC = "M20";
  NET "DDR_A<10>"         LOC = "A19";
  NET "DDR_A<11>"         LOC = "N18";
  NET "DDR_A<12>"         LOC = "N20";
  
  NET "DDR_D<0>"          LOC = "Y12";
  NET "DDR_D<1>"          LOC = "Y22";
  NET "DDR_D<2>"          LOC = "W21";
  NET "DDR_D<3>"          LOC = "V21";
  NET "DDR_D<4>"          LOC = "V22";
  NET "DDR_D<5>"          LOC = "U21";
  NET "DDR_D<6>"          LOC = "U22";
  NET "DDR_D<7>"          LOC = "T21";
  NET "DDR_D<8>"          LOC = "R20";
  NET "DDR_D<9>"          LOC = "R19";
  NET "DDR_D<10>"         LOC = "T20";
  NET "DDR_D<11>"         LOC = "T19";
  NET "DDR_D<12>"         LOC = "U19";
  NET "DDR_D<13>"         LOC = "V20";
  NET "DDR_D<14>"         LOC = "V19";
  NET "DDR_D<15>"         LOC = "W20";
  
  NET "DDR_BS0"           LOC = "M21";
  NET "DDR_BS1"           LOC = "B19";
  
  NET "DDR_LDM"           LOC = "R21";
  NET "DDR_UDM"           LOC = "T22";
  
  NET "DDR_LDQS"          LOC = "P20";
  NET "DDR_UDQS"          LOC = "P19";
  
  NET "DDR_CSn"           LOC = "N22";
  
  NET "DDR_RASn"          LOC = "N21";
  NET "DDR_CASn"          LOC = "P21";
  
  NET "DDR_WEn"           LOC = "R22";
  
  NET "DDR_CLK"           LOC = "D12";
  NET "DDR_CLKn"          LOC = "E12";
  NET "DDR_CLKE"          LOC = "N19";