View source for TMS570LS3137 HalCoGen Bugs

Bugs, artifacts and mismatches in TexasInstruments HalCoGen tool.

* Ti HalCoGen version 3.01.01

== Incorrect DMM GIO Pins Mapping ==

All operations to select pin as GIO, select pin direction etc.
are buggy. All registers start by  DMM SYNC (0), DMM CLK (1)
and then follows DATA[0], but HalCoGen has different idea
about pin mapping: 

<code><pre>
    dmmREG->PC1 =  1           /* DATA[0] */  /*!!! should be 1 << 2 !!!*/ 
                | (1 << 1)     /* DATA[1] */  /*!!! should be 1 << 3 !!!*/
                | (1 << 2)     /* DATA[2] */  /*!!! etc !!!*/
                | (1 << 3)     /* DATA[3] */
                | (1 << 4)     /* DATA[4] */
                | (1 << 5)     /* DATA[5] */
                | (1 << 6)     /* DATA[6] */
                | (0 << 7)     /* DATA[7] */
                | (0 << 8)     /* DATA[8] */
                | (0 << 9)     /* DATA[9] */
                | (0 << 10)    /* DATA[10] */
                | (1 << 11)    /* DATA[11] */
                | (0 << 12)    /* DATA[12] */
                | (1 << 13)    /* DATA[13] */
                | (1 << 14)    /* DATA[14] */
                | (0 << 15)    /* DATA[15] */
                | (0 << 16)    /* DMM SYNC */
                | (1 << 17)    /* DMM CLK */
                | (1 << 18);   /* DMM ENA */
</pre></code>

== PINMUX Does not Know Balls  A3 (N2HET1[29]), J17 (N2HET1[31]) ==

These pins do not have alternative functions, but corresponding PINMUX26 register
bits has to be set to connect N2HET1 function signals to the pins.

<code><pre>
--- a/source/pinmux.c
+++ b/source/pinmux.c
@@ -93,8 +93,9 @@ void muxInit(void){
 	pinMuxReg->PINMUX24 = 0x01010101;
 	pinMuxReg->PINMUX25 = 0x01010101;
-	
-	pinMuxReg->PINMUX26 = PINMUX_BALL_W6_DMM_DATA_2 | PINMUX_BALL_T12_DMM_DATA_3;
+
+	/* Halcogen fix enabling N2HET1[29], N2HET1[31] */
+	pinMuxReg->PINMUX26 = 0x0101 | PINMUX_BALL_W6_DMM_DATA_2 | PINMUX_BALL_T12_DMM_DATA_3;
 	

 	pinMuxReg->PINMUX27 = PINMUX_BALL_E19_DMM_DATA_5 | PINMUX_BALL_B6_DMM_DATA_6 | PINMUX_BALL_E16_DMM_DATA_9 | PINMUX_BALL_H17_DMM_DATA_10;
</pre></code>

== Use of the EMIF module (SDRAM controller) requires GPREG1[31] to be set ==

From UM 4.3.3 Control of Special Multiplexed Options

Any application that requires the EMIF functionality
must set GPREG1[31]. This allows these 8 EMIF module
outputs to be driven on to the assigned balls.

<code><pre>
   systemREG1->GPREG1 |= 0x80000000;
</pre></code>