From e72372984d3f740bd4546ac8e352787f81edc608 Mon Sep 17 00:00:00 2001 From: David Cater Date: Tue, 15 May 2018 17:36:52 -0400 Subject: [PATCH] dt-bindings: Add binding for IDT 8T49N24x UFT IDT8T49N241 has 4 outputs; 1 integral divider and 3 fractional dividers. The 8T49N241 accepts up to two differential or single-ended input clocks and a fundamental-mode crystal input. The internal PLL can lock to either of the input reference clocks or just to the crystal to behave as a frequency synthesizer. Signed-off-by: David Cater Signed-off-by: Michal Simek --- .../bindings/clock/idt,idt8t49n24x.txt | 156 ++++++++++++++++++ 1 file changed, 156 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt diff --git a/Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt b/Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt new file mode 100644 index 000000000000..8b52017cf1c3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt @@ -0,0 +1,156 @@ +Binding for IDT 8T49N24x Universal Frequency Translator + +The 8T49N241 has one fractional-feedback PLL that can be used as a +jitter attenuator and frequency translator. It is equipped with one +integer and three fractional output dividers, allowing the generation +of up to four different output frequencies, ranging from 8kHz to 1GHz. +These frequencies are completely independent of each other, the input +reference frequencies and the crystal reference frequency. The device +places virtually no constraints on input to output frequency conversion, +supporting all FEC rates, including the new revision of ITU-T +Recommendation G.709 (2009), most with 0ppm conversion error. +The outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels. + +The driver can read a full register map from the DT, and will use that +register map to initialize the attached part (via I2C) when the system +boots. Any configuration not supported by the common clock framework +must be done via the full register map, including optimized settings. + +The 8T49N241 accepts up to two differential or single-ended input clocks +and a fundamental-mode crystal input. The internal PLL can lock to either +of the input reference clocks or just to the crystal to behave as a +frequency synthesizer. The PLL can use the second input for redundant +backup of the primary input reference, but in this case, both input clock +references must be related in frequency. + +All outputs are currently assumed to be LVDS, unless overridden in the +full register map in the DT. + +==I2C device node== + +Required properties: +- compatible: shall be one of "idt,idt8t49n241" +- reg: i2c device address, shall be one of 0x7C, 0x6C, 0x7D, 0x6D, + 0x7E, 0x6E, 0x7F, 0x6F. +- #clock-cells: From common clock bindings: Shall be 1. + +- clocks: from common clock binding; input clock handle. Required. +- clock-names: from common clock binding; clock input names, shall be + one of "input-clk0", "input-clk1", "input-xtal". Required. + +==Mapping between clock specifier and physical pins== + +When referencing the provided clock in the DT using phandle and +clock specifier, the following mapping applies: + +8T49N241: + 0 -- Q0 + 1 -- Q1 + 2 -- Q2 + 3 -- Q3 + +==Example== + +/* Example1: 25MHz input clock (via CLK0) */ + +ref25: ref25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; +}; + +i2c-master-node { + + /* IDT 8T49N241 i2c universal frequency translator */ + i2c241: clock-generator@6a { + compatible = "idt,idt8t49n241"; + reg = <0x6c>; + #clock-cells = <1>; + + /* Connect input-clk0 to 25MHz reference */ + clocks = <&ref25m>; + clock-names = "input-clk0"; + }; +}; + +/* Consumer referencing the 8T49N241 pin Q1 */ +consumer { + ... + clocks = <&i2c241 1>; + ... +} + +/* Example2: 40MHz xtal frequency, specify all settings */ + +ref40: ref40m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; +}; + +i2c-master-node { + + /* IDT 8T49N241 i2c universal frequency translator */ + i2c241: clock-generator@6a { + compatible = "idt,idt8t49n241"; + reg = <0x6c>; + #clock-cells = <1>; + + /* Connect input-xtal to 40MHz reference */ + clocks = <&ref40m>; + clock-names = "input-xtal"; + + settings=[ +09 50 00 60 67 C5 6C FF 03 00 30 00 00 01 00 00 +01 07 00 00 07 00 00 77 6D 06 00 00 00 00 00 FF +FF FF FF 00 3F 00 2A 00 16 33 33 00 01 00 00 D0 +00 00 00 00 00 00 00 00 00 04 00 00 00 02 00 00 +00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 D7 0A 2B 20 00 00 00 0B +00 00 00 00 00 00 00 00 00 00 27 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +C3 00 08 01 00 00 00 00 00 00 00 00 00 30 00 00 +00 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 85 00 00 9C 01 D4 02 71 07 00 00 00 +00 83 00 10 02 08 8C +]; + }; +}; -- 2.39.2