From b84c2bd18930196d739a5237823a3dd3a5df8cad Mon Sep 17 00:00:00 2001 From: Radhey Shyam Pandey Date: Wed, 17 Apr 2019 20:46:58 +0530 Subject: [PATCH] Revert "net: xilinx: axiethernet: Increase TX and RX BD count" This reverts commit ce37bfc2d48a94c5938838f5befbb48336f556e6. In 10G + mcdma(32-bit) zcu102 design we are seeing swiotlb buffer full error when MTU is set to 9000. The reason is default software IO TLB 64MB size is not sufficient. Hence in order to make all configurations work with the default kernel parameters, reverting BD count increase. Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek --- drivers/net/ethernet/xilinx/xilinx_axienet.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h index 0652bab6af15..de3f1f3097fa 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -28,8 +28,8 @@ #define XAE_MAX_JUMBO_FRAME_SIZE (XAE_JUMBO_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE) /* Descriptors defines for Tx and Rx DMA - 2^n for the best performance */ -#define TX_BD_NUM 512 -#define RX_BD_NUM 512 +#define TX_BD_NUM 64 +#define RX_BD_NUM 128 /* DMA address width min and max range */ #define XAE_DMA_MASK_MIN 32 @@ -487,7 +487,7 @@ #define XXV_TX_PTP_LEN 12 /* Macros used when AXI DMA h/w is configured without DRE */ -#define XAE_TX_BUFFERS TX_BD_NUM +#define XAE_TX_BUFFERS 64 #define XAE_MAX_PKT_LEN 8192 /** -- 2.39.2