Michael Gill [Tue, 10 Jan 2017 23:08:07 +0000 (15:08 -0800)]
staging: apf: Increase buffer cap for SDSoC
Currently there is a hard limit on the number of buffers
available. This patch increases that limit, with the expectation
that the limit will be removed entirely in the 2017.1 timeframe.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Moritz Fischer [Thu, 22 Dec 2016 17:19:25 +0000 (09:19 -0800)]
ARM64: zynqmp: Fix i2c node's compatible string
The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core
which fixes some silicon bugs that needed software workarounds
in Version 1.0 that was used on Zynq systems.
Signed-off-by: Moritz Fischer <mdf@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> Cc: Rob Herring <robh+dt@kernel.org> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Yasir-Khan [Fri, 30 Dec 2016 17:35:57 +0000 (22:35 +0500)]
serial: xuartps: Enable uart loopback mode
This patch adds xilinx uart loopback support by modifying the
cdns_uart_set_mctrl function to handle the switch to loopback mode.
After this patch, the loopback mode can be enabled/disabled by
setting/clearing the TIOCM_LOOP modem bit via TIOCMBIS/TIOCMBIC
ioctls respectively.
Signed-off-by: Yasir-Khan <yasir_khan@mentor.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ARM64: zynqmp: Remove rollback in pm domain power off in case of error
Removed reversing the power off operation in the case of an error.
An error could appear only if something is wrong with the communication
to the PFW and in that case, reversing the operation makes no sense
because it relies on the same communication channel. Added print for an
error case.
ARM64: zynqmp: Block on set requirement when powering on a domain
If the zynqmp_pm_set_requirement call is non-blocking, the return value
represents only the status of sending IPI message to PMU (status 0 means
that the message arguments and the IPI are sent to the PMU). Consequently,
when the zynqmp_pm_set_requirement call returns the PMU may not have
completed the processing of the call. In that case, if the device driver
attempts to access a domain which is still off it would crash. Moreover,
the result of actual processing of the call is not returned, so a power
on failure cannot be captured.
Make the call blocking, so the returned value represents the status
of processing the zynqmp_pm_set_requirement call.
Yasir-Khan [Thu, 1 Dec 2016 23:19:52 +0000 (04:19 +0500)]
arm64: zynqmp: macb: release spinlock before calling ptp_clock_unregister
macb_ptp_close calls ptp_clock_unregister with spinlock locked which
further calls device_destroy which might block on mutex required for
deleting the device node and sleep. This sleeping while holding the
spinlock triggers the below kernel panic.
Michael Gill [Mon, 19 Dec 2016 21:06:13 +0000 (13:06 -0800)]
staging: apf: Changing dma-buf attachment
The method used for attaching to buffers through the dma-buf
API resulted in loss of buffers when buffers originated from
paged v4l2 devices. This patch resolves that.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Wed, 9 Nov 2016 18:37:07 +0000 (10:37 -0800)]
drm: xilinx: dp_sub: Store drm formats
Store all supported formats for each layer. Stored formats are returned
to support dynamic format switching. With this, it's not required to
specify the layer format in DT. Thus, the layer pixel format is optional,
and it falls back to the format format. Still user can specify the layer
to be specific format, for example for fbdev emulation.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Added the idle-states node to describe zynqmp idle states. Only cpu-sleep-0
idle state is added in this patch. References to the idle-states node are
added in all CPU nodes. Time values: entry/exit latencies and min-residency,
needs to be tuned. arm,psci-suspend-param is selected to comply with PSCIv1.0
and Extended StateID format.
Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com> Acked-by: Will Wong <willw@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 25 Oct 2016 06:40:18 +0000 (08:40 +0200)]
ARM64: zynqmp: Fix tap_delay conditional build
tap_delays.c depends on CONFIG_SOC_XILINX_ZYNQMP
not on ARCH_ZYNQMP directly.
There is compilation error when CONFIG_SOC_XILINX_ZYNQMP is
disabled and ARCH_ZYNQMP is enabled.
Error log:
drivers/soc/xilinx/zynqmp/tap_delays.c:244:6: error: redefinition of
'arasan_zynqmp_set_tap_delay'
void arasan_zynqmp_set_tap_delay(u8 deviceid, u8 timing, u8 bank)
^
In file included from drivers/soc/xilinx/zynqmp/tap_delays.c:22:0:
include/linux/soc/xilinx/zynqmp/tap_delays.h:29:13: note: previous
definition of 'arasan_zynqmp_set_tap_delay' was here
inline void arasan_zynqmp_set_tap_delay(u8 deviceid, u8 timing, u8
bank) {}
^
drivers/soc/xilinx/zynqmp/tap_delays.c:284:6: error: redefinition of
'zynqmp_dll_reset'
void zynqmp_dll_reset(u8 deviceid)
^
In file included from drivers/soc/xilinx/zynqmp/tap_delays.c:22:0:
include/linux/soc/xilinx/zynqmp/tap_delays.h:30:13: note: previous
definition of 'zynqmp_dll_reset' was here
inline void zynqmp_dll_reset(u8 deviceid) {}
^
Reported-by: Cyril Chemparathy <cyrilc@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 14 Sep 2016 11:33:13 +0000 (13:33 +0200)]
ARM64: zynqmp: Add and enable dcc for zcu100 and zcu102
Add debug console to dtsi and enable it for zcu100 and zcu102.
Keep in your mind that every core has separate dcc port in case you want
to run SMP kernel.
DCC is very helpful communication channel for debugging.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Sat, 15 Oct 2016 00:53:16 +0000 (17:53 -0700)]
drm: xilinx: drv: Set all clients as master
With this change, any client with root privilege will be master.
This means that all applications that run on the Xilinx DRM driver
as root get full control of the driver. It is hacky, but easy way
to enable multiple clients, for example including X11 and
other KMS applications to control of the pipeline.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Thu, 13 Oct 2016 00:32:41 +0000 (17:32 -0700)]
drm: xilinx: dp_sub: Support color component swap
Using the color space conversion coefficients, the driver can
support more formats by swapping color components. For example,
with this change, the driver supports ARGB format with the hadrware
ABGR format by swapping R and B in the coefficient matrix.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Zynqmp DMA driver expects two clocks (main clock and apb clock)
For LPDDMA channels the two clocks are missing in the
Dma node resulting probe failure.
xilinx-zynqmp-dma ffa80000.dma: main clock not found.
xilinx-zynqmp-dma ffa80000.dma: Probing channel failed
xilinx-zynqmp-dma: probe of ffa80000.dma failed with error -2
This patch fixes this issue.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
sound: soc: xilinx: Add 256 bytes for period bytes constraint
The DPDMA has the constraint that each buffer size should be aligned
with 256 bytes. Enforce this limitation by adding a step size
constraint for period bytes.
Michael Gill [Wed, 28 Sep 2016 23:53:46 +0000 (16:53 -0700)]
staging: apf: Eliminate unnecessary flushing on SG-DMA transfers
There was a bug introduced when introducing threading that may
cause transfers that do not require cache flushing to trigger
flushing unnecessarily. This does not impact correctness,
but will improve performance.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Revert "drm: xilinx: dp: Set maximum swing / preemphsis level to 2 for ZynqMP"
This reverts commit 7b8840fd1150 ("drm: xilinx: dp: Set maximum
swing / preemphsis level to 2 for ZynqMP")
The voltage swing level 3 is optional per DP 1.2 spec
(Section 3.1.5.2 & page 220). But some monitor fails with sepcific
link configuration, so revert this change and set maximum voltage
swing back to level 3.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When validating data integrity using jffs2 file system, if we
do write and erase in multiple iterations, we are getting SPI
timed out error. this patch fixes that.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When the kernel is compiled in Thumb mode (CONFIG_THUMB2_KERNEL)
copying and jumping/returning to/from the suspend code in OCM failed due
to misinterpreting or ignoring bit 0 of function addresses - which
indicates the execution state at the jump destination - , resulting
with the kernel crashing on an undefined instruction.
In detail, the suspend code was copied with an erroneous, additional
offset of 1 due to the LSB in the address of zynq_sys_suspend being set.
And jumping to the code failed as
1. the additional offset wasn't taken into account when jumping
2. the jump switched to ARM state even though the destination contains
Thumb code
Fixed by using the 'fncpy' macro to do the copying and obtaining the
function pointer to call.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Mathias Nyman [Wed, 1 Jun 2016 15:09:10 +0000 (18:09 +0300)]
xhci: fix platform quirks overwrite regression in 4.7-rc1
commit b1c127ae990b ("usb: host: xhci: plat: make use of new methods in
xhci_plat_priv") sets xhci->quirks before calling xhci_gen_setup(), which
will overwrite them.
Don't overwite the quirks, just add the new ones
Fixes: b1c127ae990b ("usb: host: xhci: plat: make use of new methods in xhci_plat_priv") Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Michael Gill [Tue, 20 Sep 2016 17:34:57 +0000 (10:34 -0700)]
staging: apf: Make xlnk driver thread-safe
This patch enables the first stage of enabling threading in SDSoC.
Accelerators cannot be shared among threads, but concurrent
use of disjoint accelerators is now supported.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dma: zynqmp: Add description for LPDDMA channel usage
LPDDMA default allows only secured access.
inorder to enable these dma channels,
one should ensure that it allows non secure access.
This patch updates the same.
Reported-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
RPMSG always dump received messages to kernel
log buffer. It impacts rpmsg performance, and if
there are rpmsg keeps running, it quickly fills up
the log buffer, you will only see rpmsg when you run
dmesg.
This patch is to only dump messages if you define DEBUG.
Signed-off-by: Wendy Liang <jliang@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mmc: arasan: Add ADMA broken quirk based on DT parameter
This patch adds 'SDHCI_QUIRK_BROKEN_ADMA' quirk to the
sdhci arasan controller based on the DT property.
With 4.6 kernel, ADMA2 is broken. So added this quirk as
a workaround and can be reverted once kernel is upgraded
or actual solution is found.
Issue with ADMA2 can be seen with the following three steps
done in regression.
1. mount SD card.
2. Read and write some random data ~1MB.
3. reboot the board.
Issue is visible after running 15 to 20mins with 4.6 kernel
and there might be a chance that issue might occur very
frequently depending on the application.
So, using the above workaround to force the controller to
use SDMA.
The performance difference between SDMA and ADMA2 is around
10-15%.
ADMA2 can be used by removing the 'broken-adma2' property
from devicetree.
Signed-off-by: Sai Krishna Potthuri <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds 'broken-adma2' property to SD node.
By adding this property controller will use SDMA
by default. This property can be removed to use ADMA2.
Signed-off-by: Sai Krishna Potthuri <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds mask for the Control register
10Mbps speed.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Documentation states that the "default-input" property should reside
directly in the node of the device. This adjusts the parsing to make the
implementation consistent with the documentation.
Based on patch by William Towle <william.towle@codethink.co.uk>.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Tested-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
phy: zynqmp: Change serdes calibraton logic to ICM_CFG1
Because of functional issues in Silicon 1.0 (XCZU9EG) which doesn't
do PMOS calibration properly, software needs to implement work around.
As a software sequence of work around, need to programe any lane to a
valid protocol. Currently serdes driver configures lane 0 (ICM_CFG0) to
PCIe for fixing the above said calibration logic issue.
Currently PCIe doesn't use serdes driver, instead it depends on fsbl for
GT lane initialization. Since serdes driver is reintializing ICM_CFG0,
PCIe is facing link down issues once linux boots.
This patch fixes the above said issue by using ICM_CFG1 instead of ICM_CFG0
for fixing the PMOS calibration issue
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: of-simple: Fix kernel hang during unbind
In dwc3_of_simple_remove() we call of_platform_depopulate() after
disabling the clocks. Since of_platform_depopulate() calls xhci_stop()
which internally stop the controller by programming the USB registers.
Since we already disabled the USB clock, kernel hangs when try to unbind.
This patch corrects the above said issue by calling of_platform_depopulate
before clock disabling.
In dwc3_of_simple_remove() we are using clk_unprepare() before
doing any clk_disable(). Because of this we see kernel warning
during unbind if we enable Common CLK framework(CCF).
This patch fixes this kernel warning by using clk_disable_unprepare
instead of clk_unprepare().
This patch adds support for gmiitorgmii converter.
The GMII to RGMII IP core provides the Reduced Gigabit Media
Independent Interface (RGMII) between Ethernet physical media
Devices and the Gigabit Ethernet controller. This core can
Switch dynamically between the three different speed modes of
Operation by configuring the converter register through mdio write.
MDIO interface is used to set operating speed of Ethernet MAC.
This converter sits between the MAC and the external phy
MAC <==> GMII2RGMII <==> RGMII_PHY
With this patch the macb driver first tries to find
the mdio node.
If it is available will create the phy/mdio devices for the
phy/mdio nodes available in the mdio.
If the mdio node is not available it will try to probe the phy nodes
available in the mac nodes as the driver does earlier.
net: ethernet: xilinx: Fix kernel crash on 64-bit platform
In the driver ptp_tx_skb variable stores the skb address
This variable is of type u32. On 64-bit platform it is causing a kernel
crash when trying to access this variable.
projects / zynq / linux.git / log