Xilinx: ARM: SLCR: updated reset logic and unlock

Xilinx: ARM: SLCR: updated reset logic and unlock

The driver was not allowing the resets in the FPGA reset
register to be cleared or more than one at a time set.
This is needed to allow bitstreams to be downloaded
by holding the FPGA in reset, then clearing the resets
after the bitstream is loaded.

The driver was also not unlocking the SLCR so that
the register could not be written.