ARM: zynq: Turn on PL310 L2 cache prefetching

ARM: zynq: Turn on PL310 L2 cache prefetching

This patch was originally authored by John Linn on 22-Sep-2011 for
linux-xlnx.git, but got lost somehow. It turns on L2 cache prefetching
when XILINX_PREFETCH (formerly XILINX_L2_PREFETCH) is enabled.

The original patch also set the Auxiliary Control Register bit "Early
BRESP enable" (in addition to "Instruction prefetch enable" and "Data
prefetch enable"), but for Cortex-A9, this bit is now set automatically
by l2c310_enable().

Suggested-by: John Linn <john.linn@xilinx.com>
Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>