]> rtime.felk.cvut.cz Git - zynq/linux.git/commit
arm64: zynqmp: Label whole PL part as fpga_full region
authorNava kishore Manne <nava.manne@xilinx.com>
Mon, 22 May 2017 06:35:17 +0000 (12:05 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 20 Jun 2017 12:13:39 +0000 (14:13 +0200)
commitd55789a028966a1d815ab5a3dcbd031de788745e
treef7ff831ad29e4f6d3d41c7fde920534b5b5419af
parent96e6444432afd0074d69aa71e9c9b6f499a14444
arm64: zynqmp: Label whole PL part as fpga_full region

This will simplify dt overlay structure for the whole PL.

Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm64/boot/dts/xilinx/zynqmp.dtsi