]> rtime.felk.cvut.cz Git - zynq/linux.git/commit
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
authorDhaval Shah <dhaval.shah@xilinx.com>
Thu, 21 Dec 2017 18:33:06 +0000 (10:33 -0800)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 8 Jan 2018 12:42:47 +0000 (13:42 +0100)
commitcee8113a295acfc4cd25728d7c3d44e6bc3bbff9
tree9f5bf6d034f9120fb26e46593fbab85dbf4cc8d0
parentb7511552f920c8c273912353a8c8bf65e8f84fdc
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

Xilinx ZYNQMP logicoreIP Init driver is based on the new
LogiCoreIP design created. This driver provides the processing system
and programmable logic isolation. Set the frequency based on the clock
information get from the logicoreIP register set.

Signed-off-by: Dhaval Shah <dshah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/soc/xilinx/Kconfig
drivers/soc/xilinx/Makefile
drivers/soc/xilinx/xlnx_vcu.c [new file with mode: 0644]