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dt-bindings: net: xilinx_axienet: Align clock-names with IP naming
authorRadhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Wed, 6 Mar 2019 15:10:11 +0000 (20:40 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 12 Mar 2019 10:05:57 +0000 (11:05 +0100)
commitab7ad83c7b4b904451609f9ea4e8581f2081912f
treebe793c18c88f657c168f90c98dbc8994c70b9c68tree | snapshot
parent24bfbbd7c927e91811032f27145ecca3970d34decommit | diff
dt-bindings: net: xilinx_axienet: Align clock-names with IP naming

Extend clocking support by deriving clock names from IP signal names.
Update clock binding information for each supported ethernet and DMA
configuration.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Reviewed-by: Harini Katakam <harini.katakam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Documentation/devicetree/bindings/net/xilinx_axienet.txt diff | blob | history
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