]> rtime.felk.cvut.cz Git - zynq/linux.git/commit
tty: uartlite: Enable clocks at probe
authorShubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Fri, 20 Apr 2018 11:20:52 +0000 (16:50 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 23 Apr 2018 09:54:22 +0000 (11:54 +0200)
commit98ce4fa38072db5c42951b69e7d26653d5299a1e
treec438eb3f25e048d7e2e6ad8395acbc4751aec90b
parent8069fd375542abf5fb321ff8d55c5cd4c77909f8
tty: uartlite: Enable clocks at probe

At probe the uartlite is getting configured.
Enable the clocks before assiging uart and
disable after probe is done.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/tty/serial/uartlite.c