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ARM: zynq: Fix coding style violation in L2 setup
authorMichal Simek <michal.simek@xilinx.com>
Thu, 14 May 2015 07:02:38 +0000 (09:02 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Thu, 14 May 2015 07:04:31 +0000 (09:04 +0200)
commit623f642217f4f3f8110133ff612cda809556844e
tree4c6d7cf885e5b0be07ed95b9ce271b5f7f853b72tree | snapshot
parentd859d34577c393c8905f2f1e08816f02fd518120commit | diff
ARM: zynq: Fix coding style violation in L2 setup

Fix coding style introduced by:
"ARM: zynq: Set bit 22 in PL310 AuxCtrl register"
(sha1: 39371574f8efa8474fde29bdeb3b54c8242b04aa)
and
"ARM: zynq: Turn on PL310 L2 cache prefetching"
(sha1: dda52ddca3e375d949a669177d6f5063cdcf713e)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/mach-zynq/common.c diff | blob | history
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