]> rtime.felk.cvut.cz Git - zynq/linux.git/commit
clk: zynqmp: clkc: Enable CLK_SET_RATE_PARENT for more clocks
authorHyun Kwon <hyun.kwon@xilinx.com>
Fri, 24 Feb 2017 02:14:34 +0000 (18:14 -0800)
committerMichal Simek <michal.simek@xilinx.com>
Fri, 24 Feb 2017 07:13:23 +0000 (08:13 +0100)
commit0934f2c0e06d320fb9a43f3f7e1818baae3805a2
tree529db8eb9ec9fa02dc90197bfa41ce16072c7045
parentd41696969cb3eb5be69777c0a8cf2a5cc8dae03b
clk: zynqmp: clkc: Enable CLK_SET_RATE_PARENT for more clocks

This enable the CLK_SET_RATE_PARENT flags for DP audio clock and
RPLL_TO_FPD. In this way, request for audio clock frequency will
propagate to the parent PLL clock.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Acked-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/clk/zynqmp/clkc.c