clk: zynqmp: clkc: Enable CLK_SET_RATE_PARENT for more clocks

clk: zynqmp: clkc: Enable CLK_SET_RATE_PARENT for more clocks

This enable the CLK_SET_RATE_PARENT flags for DP audio clock and
RPLL_TO_FPD. In this way, request for audio clock frequency will
propagate to the parent PLL clock.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Acked-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>