xilinx_axienet: Handle 0 packet receive gracefully

xilinx_axienet: Handle 0 packet receive gracefully

The AXI-DMA rx-delay interrupt can sometimes be triggered when there are 0
outstanding packets received. This is due to the fact that the receive function
will greedily consume as many packets as possible on interrupt. So if two
packets (with a very particular timing) arrive in succession they will each
cause the rx-delay interrupt, but the first interrupt will consume both packets.
This means the second interrupt is a 0 packet receive.

This is mostly OK, except that the tail pointer register is updated
unconditionally on receive. Currently the tail pointer is always set to the
current bd-ring descriptor under the assumption that the hardware has moved onto
the next descriptor. What this means for length 0 recv is the current descriptor
that the hardware is potentially yet to use will be marked as the tail. This
causes the hardware to think its run out of descriptors deadlocking the whole rx
path.

Fixed by updating the tail pointer to the most recent successfully consumed
descriptor.

Reported-by: Wendy Liang <wendy.liang@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Tested-by: Jason Wu <huanyu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>