Merge branch 'master' of http://www.kernel.org/pub/scm/linux/kernel/git/torvalds...

[zynq/linux.git] / arch / powerpc / platforms / 44x / Kconfig

diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 6abe91357eee742afbeb5efc32472064339c7aff..f10aa1f3c40e87e73ad8afd7a081301a048699d0 100644 (file)
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -102,6 +102,58 @@ config YOSEMITE
 #      help
 #        This option enables support for the IBM PPC440GX evaluation board.
 
+config XILINX_ML507
+       bool "Xilinx ML507 Reference System"
+       depends on 44x
+       default n
+       select XILINX_ML5XX
+       select WANT_DEVICE_TREE
+       help
+         This option enables support for the Xilinx ML507 board.
+
+config XILINX_DISABLE_44x_CACHE
+       bool "Disable PPC440 caches"
+       depends on XILINX_ML507
+       help
+         This option allows to disable the caches on the PPC440. Some early
+         PPC440 soft-cores do not work with caches enabled. Also, some early
+         ML507 boards do have a non-functioning cache. If you have any
+         problems running the ML5, try using this option.
+
+config PPC_FPU
+       depends on XILINX_VIRTEX_5_FXT
+       bool "Enable Xilinx Soft FPU"
+       help
+         This option enables the Xilinx Soft FPU attached to the APU
+         interface of the PPC440 (requires DP_FULL FPU pcore).
+
+config XILINX_ERRONEOUS_EXCEPTIONS_WORKAROUND
+       depends on XILINX_VIRTEX_5_FXT && PPC_FPU
+       bool "Enable Spurious Program Exceptions Workaround"
+       default y
+       help
+         This option enables a workaround for a bug in the APU controller of
+         the PPC440 processor block in Virtex-5 FXT. See the answer record 
+         at http://www.xilinx.com/support/answers/30579.htm for more details.
+
+config XILINX_FPU_LOAD_CORRUPTION_WORKAROUND
+       depends on XILINX_VIRTEX_5_FXT && PPC_FPU
+       bool "Enable Xilinx FPU prefetch workaround"
+       default y
+       help
+         This option enables a workaround for a bug in the APU controller of
+         the PPC440 processor block in Virtex-5 FXT. See the answer record at
+         http://www.xilinx.com/support/answers/30529.htm for more details.
+
+config XILINX_FPU_ITLB_EXCEPTION_WORKAROUND
+       depends on XILINX_VIRTEX_5_FXT && PPC_FPU
+       bool "Enable Xilinx FPU TLB instruction miss workaround"
+       default y
+       help
+         This option enables a workaround for a bug in the APU controller of
+         the PPC440 processor block in Virtex-5 FXT. See the answer record at
+         http://www.xilinx.com/support/answers/30570.htm for more details.
+
 # 44x specific CPU modules, selected based on the board above.
 config 440EP
        bool
@@ -152,3 +204,15 @@ config 460EX
 # 44x errata/workaround config symbols, selected by the CPU models above
 config IBM440EP_ERR42
        bool
+
+
+# Xilinx specific config options.
+config XILINX_ML5XX
+       bool
+       select XILINX_VIRTEX
+
+config XILINX_VIRTEX_5_FXT
+       bool
+       depends on XILINX_ML507
+       default y
+