PCI: XDMA PL PCIe: Add documentation for MSI DECODE mode.

[zynq/linux.git] / Documentation / devicetree / bindings / pci / xilinx-xdma-pl-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/xilinx-xdma-pl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-xdma-pl-pcie.txt
index 29440feefc769300528aa614764224b3f17782e8..92b7194a2f7fb4995568e280e6ce5baf64192922 100644 (file)
--- a/Documentation/devicetree/bindings/pci/xilinx-xdma-pl-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-xdma-pl-pcie.txt
@@ -17,6 +17,11 @@ Required properties:
        Please refer to the standard PCI bus binding document for a more
        detailed explanation
 
+For MSI DECODE mode:
+- interrupt-names: Must include the following entries:
+       "misc": interrupt asserted when legacy or error interrupt is received
+       "msi1, msi0": interrupt asserted when an MSI is received
+
 Interrupt controller child node
 +++++++++++++++++++++++++++++++
 Required properties:
@@ -35,6 +40,7 @@ the four INTx interrupts in ISR and route them to this domain.
 
 Example:
 ++++++++
+MSI FIFO mode:
        xdma_0: axi-pcie@a0000000 {
                #address-cells = <3>;
                #interrupt-cells = <1>;
@@ -57,3 +63,25 @@ Example:
                        interrupt-controller ;
                };
        };
+
+MSI DECODE mode:
+       xdma_0: axi-pcie@a0000000 {
+               #address-cells = <3>;
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               compatible = "xlnx,xdma-host-3.00";
+               device_type = "pci";
+               interrupt-map = <0 0 0 1 &pcie_intc_0 1>, <0 0 0 2 &pcie_intc_0 2>, <0 0 0 3 &pcie_intc_0 3>, <0 0 0 4 &pcie_intc_0 4>;
+               interrupt-map-mask = <0 0 0 7>;
+               interrupt-parent = <&gic>;
+               interrupt-names = "misc", "msi0", "msi1";
+               interrupts = <0 89 4>, <0 90 4>, <0 91 4>;
+               ranges = <0x02000000 0x00000000 0xB0000000 0x0 0xB0000000 0x00000000 0x01000000>,
+                       <0x43000000 0x00000005 0x00000000 0x00000005 0x00000000 0x00000000 0x01000000>;
+               reg = <0x0 0xA0000000 0x0 0x10000000>;
+               pcie_intc_0: interrupt-controller {
+                       #address-cells = <0>;
+                       #interrupt-cells = <1>;
+                       interrupt-controller ;
+               };
+       };