Merge tag 'v4.0.8' into xlnx_4.0.8-rt6

[zynq/linux.git] / arch / mips / mm / tlbex.c

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index d75ff73a20120bf28d919b7b6b5bf30a22b5088f..a79fd0af0224c1a10fcbbd61422dacca21f14ec5 100644 (file)
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -501,26 +501,9 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
        case tlb_indexed: tlbw = uasm_i_tlbwi; break;
        }
 
-       if (cpu_has_mips_r2_exec_hazard) {
-               /*
-                * The architecture spec says an ehb is required here,
-                * but a number of cores do not have the hazard and
-                * using an ehb causes an expensive pipeline stall.
-                */
-               switch (current_cpu_type()) {
-               case CPU_M14KC:
-               case CPU_74K:
-               case CPU_1074K:
-               case CPU_PROAPTIV:
-               case CPU_P5600:
-               case CPU_M5150:
-               case CPU_QEMU_GENERIC:
-                       break;
-
-               default:
+       if (cpu_has_mips_r2_r6) {
+               if (cpu_has_mips_r2_exec_hazard)
                        uasm_i_ehb(p);
-                       break;
-               }
                tlbw(p);
                return;
        }