Merge tag 'v4.0.8' into xlnx_4.0.8-rt6

[zynq/linux.git] / arch / arm / mach-tegra / reset-handler.S

diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 71be4af5e975bec078508d1ea920568edf11b289..e3070fdab80b8b7481c0527e2d649ae7d664dc58 100644 (file)
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -169,10 +169,10 @@ after_errata:
        cmp     r6, #TEGRA20
        bne     1f
        /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
-       mov32   r5, TEGRA_PMC_BASE
-       mov     r0, #0
+       mov32   r5, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
+       mov     r0, #CPU_NOT_RESETTABLE
        cmp     r10, #0
-       strne   r0, [r5, #PMC_SCRATCH41]
+       strneb  r0, [r5, #__tegra20_cpu1_resettable_status_offset]
 1:
 #endif
 
@@ -281,6 +281,10 @@ __tegra_cpu_reset_handler_data:
        .rept   TEGRA_RESET_DATA_SIZE
        .long   0
        .endr
+       .globl  __tegra20_cpu1_resettable_status_offset
+       .equ    __tegra20_cpu1_resettable_status_offset, \
+                                       . - __tegra_cpu_reset_handler_start
+       .byte   0
        .align L1_CACHE_SHIFT
 
 ENTRY(__tegra_cpu_reset_handler_end)