1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU111
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 #include <dt-bindings/phy/phy.h>
19 model = "ZynqMP ZCU111 RevA";
20 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
43 /* Another 4GB connected to PL */
47 compatible = "gpio-keys";
53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54 linux,code = <108>; /* down */
61 compatible = "gpio-leds";
64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "heartbeat";
74 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
109 phy-handle = <&phy0>;
110 phy-mode = "rgmii-id";
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_gem3_default>;
115 ti,rx-internal-delay = <0x8>;
116 ti,tx-internal-delay = <0xa>;
117 ti,fifo-depth = <0x1>;
118 ti,rxctrl-strap-worka;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_gpio_default>;
134 clock-frequency = <400000>;
135 pinctrl-names = "default", "gpio";
136 pinctrl-0 = <&pinctrl_i2c0_default>;
137 pinctrl-1 = <&pinctrl_i2c0_gpio>;
138 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
139 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
141 tca6416_u22: gpio@20 {
142 compatible = "ti,tca6416";
144 gpio-controller; /* interrupt not connected */
150 * 1 - MAX6643_FANFAIL_B
151 * 2 - MIO26_PMU_INPUT_LS
152 * 4 - SFP_SI5382_INT_ALM
153 * 5 - IIC_MUX_RESET_B
154 * 6 - GEM3_EXP_RESET_B
155 * 10 - FMCP_HSPC_PRSNT_M2C_B
156 * 11 - CLK_SPI_MUX_SEL0
157 * 12 - CLK_SPI_MUX_SEL1
158 * 16 - IRPS5401_ALERT_B
159 * 17 - INA226_PMBUS_ALERT
160 * 3, 7, 13-15 - not connected
164 i2cswitch@75 { /* u23 */
165 compatible = "nxp,pca9544";
166 #address-cells = <1>;
169 i2c@0 { /* i2c mw 75 0 1 */
170 #address-cells = <1>;
174 /* PMBUS_ALERT done via pca9544 */
175 ina226@40 { /* u67 */
176 compatible = "ti,ina226";
178 shunt-resistor = <2000>;
180 ina226@41 { /* u59 */
181 compatible = "ti,ina226";
183 shunt-resistor = <5000>;
185 ina226@42 { /* u61 */
186 compatible = "ti,ina226";
188 shunt-resistor = <5000>;
190 ina226@43 { /* u60 */
191 compatible = "ti,ina226";
193 shunt-resistor = <5000>;
195 ina226@45 { /* u64 */
196 compatible = "ti,ina226";
198 shunt-resistor = <5000>;
200 ina226@46 { /* u69 */
201 compatible = "ti,ina226";
203 shunt-resistor = <2000>;
205 ina226@47 { /* u66 */
206 compatible = "ti,ina226";
208 shunt-resistor = <5000>;
210 ina226@48 { /* u65 */
211 compatible = "ti,ina226";
213 shunt-resistor = <5000>;
215 ina226@49 { /* u63 */
216 compatible = "ti,ina226";
218 shunt-resistor = <5000>;
221 compatible = "ti,ina226";
223 shunt-resistor = <5000>;
225 ina226@4b { /* u71 */
226 compatible = "ti,ina226";
228 shunt-resistor = <5000>;
230 ina226@4c { /* u77 */
231 compatible = "ti,ina226";
233 shunt-resistor = <5000>;
235 ina226@4d { /* u73 */
236 compatible = "ti,ina226";
238 shunt-resistor = <5000>;
240 ina226@4e { /* u79 */
241 compatible = "ti,ina226";
243 shunt-resistor = <5000>;
247 #address-cells = <1>;
252 i2c@2 { /* i2c mw 75 0 4 */
253 #address-cells = <1>;
256 irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
258 compatible = "infineon,irps5401";
261 irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
263 compatible = "infineon,irps5401";
266 irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
268 compatible = "infineon,irps5401";
278 i2c@3 { /* i2c mw 75 0 8 */
279 #address-cells = <1>;
289 clock-frequency = <400000>;
290 pinctrl-names = "default", "gpio";
291 pinctrl-0 = <&pinctrl_i2c1_default>;
292 pinctrl-1 = <&pinctrl_i2c1_gpio>;
293 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
294 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
296 i2cswitch@74 { /* u26 */
297 compatible = "nxp,pca9548";
298 #address-cells = <1>;
301 i2c@0 { /* i2c mw 74 0 1 */
302 #address-cells = <1>;
306 * IIC_EEPROM 1kB memory which uses 256B blocks
307 * where every block has different address.
308 * 0 - 256B address 0x54
309 * 256B - 512B address 0x55
310 * 512B - 768B address 0x56
311 * 768B - 1024B address 0x57
313 eeprom: eeprom@54 { /* u88 */
314 compatible = "at,24c08";
318 i2c@1 { /* i2c mw 74 0 2 */
319 #address-cells = <1>;
322 si5341: clock-generator1@36 { /* SI5341 - u46 */
323 compatible = "si5341";
328 i2c@2 { /* i2c mw 74 0 4 */
329 #address-cells = <1>;
332 si570_1: clock-generator2@5d { /* USER SI570 - u47 */
334 compatible = "silabs,si570";
336 temperature-stability = <50>;
337 factory-fout = <300000000>;
338 clock-frequency = <300000000>;
341 i2c@3 { /* i2c mw 74 0 8 */
342 #address-cells = <1>;
345 si570_2: clock-generator3@5d { /* USER MGT SI570 - u49 */
347 compatible = "silabs,si570";
349 temperature-stability = <50>;
350 factory-fout = <156250000>;
351 clock-frequency = <148500000>;
354 i2c@4 { /* i2c mw 74 0 10 */
355 #address-cells = <1>;
358 si5328: clock-generator4@69 { /* SI5328 - u48 */
359 compatible = "silabs,si5328";
363 i2c@5 { /* i2c mw 74 0 11 */
364 #address-cells = <1>;
367 sc18is603@2f { /* sc18is602 - u93 */
368 compatible = "nxp,sc18is603";
370 /* 4 gpios for CS not handled by driver */
380 i2c@6 { /* i2c mw 74 0 11 */
381 #address-cells = <1>;
390 compatible = "nxp,pca9548"; /* u27 */
391 #address-cells = <1>;
396 #address-cells = <1>;
402 #address-cells = <1>;
408 #address-cells = <1>;
413 i2c@3 { /* i2c mw 75 0 8 */
414 #address-cells = <1>;
418 dev@19 { /* u-boot detection FIXME */
422 dev@30 { /* u-boot detection */
426 dev@35 { /* u-boot detection */
430 dev@36 { /* u-boot detection */
434 dev@51 { /* u-boot detection - maybe SPD */
440 #address-cells = <1>;
446 #address-cells = <1>;
452 #address-cells = <1>;
458 #address-cells = <1>;
468 pinctrl_i2c0_default: i2c0-default {
470 groups = "i2c0_3_grp";
475 groups = "i2c0_3_grp";
477 slew-rate = <SLEW_RATE_SLOW>;
478 io-standard = <IO_STANDARD_LVCMOS18>;
482 pinctrl_i2c0_gpio: i2c0-gpio {
484 groups = "gpio0_14_grp", "gpio0_15_grp";
489 groups = "gpio0_14_grp", "gpio0_15_grp";
490 slew-rate = <SLEW_RATE_SLOW>;
491 io-standard = <IO_STANDARD_LVCMOS18>;
495 pinctrl_i2c1_default: i2c1-default {
497 groups = "i2c1_4_grp";
502 groups = "i2c1_4_grp";
504 slew-rate = <SLEW_RATE_SLOW>;
505 io-standard = <IO_STANDARD_LVCMOS18>;
509 pinctrl_i2c1_gpio: i2c1-gpio {
511 groups = "gpio0_16_grp", "gpio0_17_grp";
516 groups = "gpio0_16_grp", "gpio0_17_grp";
517 slew-rate = <SLEW_RATE_SLOW>;
518 io-standard = <IO_STANDARD_LVCMOS18>;
522 pinctrl_uart0_default: uart0-default {
524 groups = "uart0_4_grp";
529 groups = "uart0_4_grp";
530 slew-rate = <SLEW_RATE_SLOW>;
531 io-standard = <IO_STANDARD_LVCMOS18>;
545 pinctrl_usb0_default: usb0-default {
547 groups = "usb0_0_grp";
552 groups = "usb0_0_grp";
553 slew-rate = <SLEW_RATE_SLOW>;
554 io-standard = <IO_STANDARD_LVCMOS18>;
558 pins = "MIO52", "MIO53", "MIO55";
563 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
564 "MIO60", "MIO61", "MIO62", "MIO63";
569 pinctrl_gem3_default: gem3-default {
571 function = "ethernet3";
572 groups = "ethernet3_0_grp";
576 groups = "ethernet3_0_grp";
577 slew-rate = <SLEW_RATE_SLOW>;
578 io-standard = <IO_STANDARD_LVCMOS18>;
582 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
589 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
597 groups = "mdio3_0_grp";
601 groups = "mdio3_0_grp";
602 slew-rate = <SLEW_RATE_SLOW>;
603 io-standard = <IO_STANDARD_LVCMOS18>;
608 pinctrl_sdhci1_default: sdhci1-default {
610 groups = "sdio1_0_grp";
615 groups = "sdio1_0_grp";
616 slew-rate = <SLEW_RATE_SLOW>;
617 io-standard = <IO_STANDARD_LVCMOS18>;
622 groups = "sdio1_cd_0_grp";
623 function = "sdio1_cd";
627 groups = "sdio1_cd_0_grp";
630 slew-rate = <SLEW_RATE_SLOW>;
631 io-standard = <IO_STANDARD_LVCMOS18>;
635 pinctrl_gpio_default: gpio-default {
638 groups = "gpio0_22_grp", "gpio0_23_grp";
642 groups = "gpio0_22_grp", "gpio0_23_grp";
643 slew-rate = <SLEW_RATE_SLOW>;
644 io-standard = <IO_STANDARD_LVCMOS18>;
649 groups = "gpio0_13_grp", "gpio0_38_grp";
653 groups = "gpio0_13_grp", "gpio0_38_grp";
654 slew-rate = <SLEW_RATE_SLOW>;
655 io-standard = <IO_STANDARD_LVCMOS18>;
664 pins = "MIO13", "MIO23", "MIO38";
674 compatible = "m25p80"; /* 32MB */
675 #address-cells = <1>;
678 spi-tx-bus-width = <1>;
679 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
680 spi-max-frequency = <108000000>; /* Based on DC1 spec */
681 partition@qspi-fsbl-uboot { /* for testing purpose */
682 label = "qspi-fsbl-uboot";
683 reg = <0x0 0x100000>;
685 partition@qspi-linux { /* for testing purpose */
686 label = "qspi-linux";
687 reg = <0x100000 0x500000>;
689 partition@qspi-device-tree { /* for testing purpose */
690 label = "qspi-device-tree";
691 reg = <0x600000 0x20000>;
693 partition@qspi-rootfs { /* for testing purpose */
694 label = "qspi-rootfs";
695 reg = <0x620000 0x5E0000>;
706 /* SATA OOB timing settings */
707 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
708 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
709 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
710 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
711 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
712 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
713 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
714 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
715 phy-names = "sata-phy";
716 phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
719 /* SD1 with level shifter */
722 pinctrl-names = "default";
723 pinctrl-0 = <&pinctrl_sdhci1_default>;
735 pinctrl-names = "default";
736 pinctrl-0 = <&pinctrl_uart0_default>;
739 /* ULPI SMSC USB3320 */
742 pinctrl-names = "default";
743 pinctrl-0 = <&pinctrl_usb0_default>;
749 snps,usb3_lpm_capable;
750 phy-names = "usb3-phy";
751 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
756 phy-names = "dp-phy0", "dp-phy1";
757 phys = <&lane1 PHY_TYPE_DP 0 1 27000000>, <&lane0 PHY_TYPE_DP 1 1 27000000>;
760 &zynqmp_dp_snd_pcm0 {
764 &zynqmp_dp_snd_pcm1 {
768 &zynqmp_dp_snd_card0 {
772 &zynqmp_dp_snd_codec0 {