1 Xilinx Video Test Pattern Generator (TPG)
2 -----------------------------------------
6 - compatible: Must contain at least one of
8 "xlnx,v-tpg-5.0" (TPG version 5.0)
9 "xlnx,v-tpg-6.0" (TPG version 6.0)
10 "xlnx,v-tpg-7.0" (TPG version 7.0)
12 TPG versions backward-compatible with previous versions should list all
13 compatible versions in the newer to older order.
15 - reg: Physical base address and length of the registers set for the device.
17 - clocks: Reference to the video core clock.
19 - xlnx,video-format, xlnx,video-width: Video format and width, as defined in
22 - port: Video port, using the DT bindings defined in ../video-interfaces.txt.
23 The TPG has a single output port numbered 0.
27 - xlnx,vtc: A phandle referencing the Video Timing Controller that generates
28 video timings for the TPG test patterns.
30 - timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG
31 input. The GPIO active level corresponds to the selection of VTC-generated
34 - reset-gpios: Specifier for a GPIO that assert TPG (AP_RST_N) reset.
35 This property is mandatory for TPG v7.0.
37 The xlnx,vtc and timing-gpios properties are mandatory when the TPG is
38 synthesized with two ports and forbidden when synthesized with one port.
43 compatible = "xlnx,v-tpg-6.0", "xlnx,v-tpg-5.0";
44 reg = <0x40050000 0x10000>;
48 timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>;
57 xlnx,video-format = <XVIP_VF_YUV_422>;
58 xlnx,video-width = <8>;
61 remote-endpoint = <&adv7611_out>;
67 xlnx,video-format = <XVIP_VF_YUV_422>;
68 xlnx,video-width = <8>;
71 remote-endpoint = <&switch_in0>;