2 * Analog Devices AD9389B/AD9889B video encoder driver
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * References (c = chapter, p = page):
22 * REF_01 - Analog Devices, Programming Guide, AD9889B/AD9389B,
23 * HDMI Transitter, Rev. A, October 2010
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/slab.h>
29 #include <linux/i2c.h>
30 #include <linux/delay.h>
31 #include <linux/videodev2.h>
32 #include <linux/workqueue.h>
33 #include <linux/v4l2-dv-timings.h>
34 #include <media/v4l2-device.h>
35 #include <media/v4l2-common.h>
36 #include <media/v4l2-dv-timings.h>
37 #include <media/v4l2-ctrls.h>
38 #include <media/i2c/ad9389b.h>
41 module_param(debug, int, 0644);
42 MODULE_PARM_DESC(debug, "debug level (0-2)");
44 MODULE_DESCRIPTION("Analog Devices AD9389B/AD9889B video encoder driver");
45 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
46 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
47 MODULE_LICENSE("GPL");
49 #define MASK_AD9389B_EDID_RDY_INT 0x04
50 #define MASK_AD9389B_MSEN_INT 0x40
51 #define MASK_AD9389B_HPD_INT 0x80
53 #define MASK_AD9389B_HPD_DETECT 0x40
54 #define MASK_AD9389B_MSEN_DETECT 0x20
55 #define MASK_AD9389B_EDID_RDY 0x10
57 #define EDID_MAX_RETRIES (8)
58 #define EDID_DELAY 250
59 #define EDID_MAX_SEGM 8
62 **********************************************************************
64 * Arrays with configuration parameters for the AD9389B
66 **********************************************************************
69 struct i2c_reg_value {
74 struct ad9389b_state_edid {
75 /* total number of blocks */
77 /* Number of segments read */
79 u8 data[EDID_MAX_SEGM * 256];
80 /* Number of EDID read retries left */
81 unsigned read_retries;
84 struct ad9389b_state {
85 struct ad9389b_platform_data pdata;
86 struct v4l2_subdev sd;
88 struct v4l2_ctrl_handler hdl;
90 /* Is the ad9389b powered on? */
92 /* Did we receive hotplug and rx-sense signals? */
94 /* timings from s_dv_timings */
95 struct v4l2_dv_timings dv_timings;
97 struct v4l2_ctrl *hdmi_mode_ctrl;
98 struct v4l2_ctrl *hotplug_ctrl;
99 struct v4l2_ctrl *rx_sense_ctrl;
100 struct v4l2_ctrl *have_edid0_ctrl;
101 struct v4l2_ctrl *rgb_quantization_range_ctrl;
102 struct i2c_client *edid_i2c_client;
103 struct ad9389b_state_edid edid;
104 /* Running counter of the number of detected EDIDs (for debugging) */
105 unsigned edid_detect_counter;
106 struct delayed_work edid_handler; /* work entry */
109 static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd);
110 static bool ad9389b_check_edid_status(struct v4l2_subdev *sd);
111 static void ad9389b_setup(struct v4l2_subdev *sd);
112 static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
113 static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
115 static inline struct ad9389b_state *get_ad9389b_state(struct v4l2_subdev *sd)
117 return container_of(sd, struct ad9389b_state, sd);
120 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
122 return &container_of(ctrl->handler, struct ad9389b_state, hdl)->sd;
125 /* ------------------------ I2C ----------------------------------------------- */
127 static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg)
129 struct i2c_client *client = v4l2_get_subdevdata(sd);
131 return i2c_smbus_read_byte_data(client, reg);
134 static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
136 struct i2c_client *client = v4l2_get_subdevdata(sd);
140 for (i = 0; i < 3; i++) {
141 ret = i2c_smbus_write_byte_data(client, reg, val);
145 v4l2_err(sd, "I2C Write Problem\n");
149 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
150 and then the value-mask (to be OR-ed). */
151 static inline void ad9389b_wr_and_or(struct v4l2_subdev *sd, u8 reg,
152 u8 clr_mask, u8 val_mask)
154 ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask);
157 static void ad9389b_edid_rd(struct v4l2_subdev *sd, u16 len, u8 *buf)
159 struct ad9389b_state *state = get_ad9389b_state(sd);
162 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
164 for (i = 0; i < len; i++)
165 buf[i] = i2c_smbus_read_byte_data(state->edid_i2c_client, i);
168 static inline bool ad9389b_have_hotplug(struct v4l2_subdev *sd)
170 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT;
173 static inline bool ad9389b_have_rx_sense(struct v4l2_subdev *sd)
175 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT;
178 static void ad9389b_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
180 ad9389b_wr_and_or(sd, 0x17, 0xe7, (mode & 0x3)<<3);
181 ad9389b_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
184 static void ad9389b_csc_coeff(struct v4l2_subdev *sd,
185 u16 A1, u16 A2, u16 A3, u16 A4,
186 u16 B1, u16 B2, u16 B3, u16 B4,
187 u16 C1, u16 C2, u16 C3, u16 C4)
190 ad9389b_wr_and_or(sd, 0x18, 0xe0, A1>>8);
191 ad9389b_wr(sd, 0x19, A1);
192 ad9389b_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
193 ad9389b_wr(sd, 0x1B, A2);
194 ad9389b_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
195 ad9389b_wr(sd, 0x1d, A3);
196 ad9389b_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
197 ad9389b_wr(sd, 0x1f, A4);
200 ad9389b_wr_and_or(sd, 0x20, 0xe0, B1>>8);
201 ad9389b_wr(sd, 0x21, B1);
202 ad9389b_wr_and_or(sd, 0x22, 0xe0, B2>>8);
203 ad9389b_wr(sd, 0x23, B2);
204 ad9389b_wr_and_or(sd, 0x24, 0xe0, B3>>8);
205 ad9389b_wr(sd, 0x25, B3);
206 ad9389b_wr_and_or(sd, 0x26, 0xe0, B4>>8);
207 ad9389b_wr(sd, 0x27, B4);
210 ad9389b_wr_and_or(sd, 0x28, 0xe0, C1>>8);
211 ad9389b_wr(sd, 0x29, C1);
212 ad9389b_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
213 ad9389b_wr(sd, 0x2B, C2);
214 ad9389b_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
215 ad9389b_wr(sd, 0x2D, C3);
216 ad9389b_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
217 ad9389b_wr(sd, 0x2F, C4);
220 static void ad9389b_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
225 ad9389b_csc_conversion_mode(sd, csc_mode);
226 ad9389b_csc_coeff(sd,
229 0, 0, 4096-564, 256);
231 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x1);
232 /* AVI infoframe: Limited range RGB (16-235) */
233 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x02);
236 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x0);
237 /* AVI infoframe: Full range RGB (0-255) */
238 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x04);
242 static void ad9389b_set_IT_content_AVI_InfoFrame(struct v4l2_subdev *sd)
244 struct ad9389b_state *state = get_ad9389b_state(sd);
246 if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
247 /* CE format, not IT */
248 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x00);
251 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x40);
255 static int ad9389b_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
257 struct ad9389b_state *state = get_ad9389b_state(sd);
260 case V4L2_DV_RGB_RANGE_AUTO:
262 if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
263 /* CE format, RGB limited range (16-235) */
264 ad9389b_csc_rgb_full2limit(sd, true);
266 /* not CE format, RGB full range (0-255) */
267 ad9389b_csc_rgb_full2limit(sd, false);
270 case V4L2_DV_RGB_RANGE_LIMITED:
271 /* RGB limited range (16-235) */
272 ad9389b_csc_rgb_full2limit(sd, true);
274 case V4L2_DV_RGB_RANGE_FULL:
275 /* RGB full range (0-255) */
276 ad9389b_csc_rgb_full2limit(sd, false);
284 static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)
288 /* Workaround for TMDS PLL problem
289 * The TMDS PLL in AD9389b change gear when the chip is heated above a
290 * certain temperature. The output is disabled when the PLL change gear
291 * so the monitor has to lock on the signal again. A workaround for
292 * this is to use the manual PLL gears. This is a solution from Analog
293 * Devices that is not documented in the datasheets.
294 * 0x98 [7] = enable manual gearing. 0x98 [6:4] = gear
296 * The pixel frequency ranges are based on readout of the gear the
297 * automatic gearing selects for different pixel clocks
298 * (read from 0x9e [3:1]).
301 if (pixelclock > 140000000)
302 gear = 0xc0; /* 4th gear */
303 else if (pixelclock > 117000000)
304 gear = 0xb0; /* 3rd gear */
305 else if (pixelclock > 87000000)
306 gear = 0xa0; /* 2nd gear */
307 else if (pixelclock > 60000000)
308 gear = 0x90; /* 1st gear */
310 gear = 0x80; /* 0th gear */
312 ad9389b_wr_and_or(sd, 0x98, 0x0f, gear);
315 /* ------------------------------ CTRL OPS ------------------------------ */
317 static int ad9389b_s_ctrl(struct v4l2_ctrl *ctrl)
319 struct v4l2_subdev *sd = to_sd(ctrl);
320 struct ad9389b_state *state = get_ad9389b_state(sd);
322 v4l2_dbg(1, debug, sd,
323 "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
325 if (state->hdmi_mode_ctrl == ctrl) {
326 /* Set HDMI or DVI-D */
327 ad9389b_wr_and_or(sd, 0xaf, 0xfd,
328 ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
331 if (state->rgb_quantization_range_ctrl == ctrl)
332 return ad9389b_set_rgb_quantization_mode(sd, ctrl);
336 static const struct v4l2_ctrl_ops ad9389b_ctrl_ops = {
337 .s_ctrl = ad9389b_s_ctrl,
340 /* ---------------------------- CORE OPS ------------------------------------------- */
342 #ifdef CONFIG_VIDEO_ADV_DEBUG
343 static int ad9389b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
345 reg->val = ad9389b_rd(sd, reg->reg & 0xff);
350 static int ad9389b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
352 ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff);
357 static int ad9389b_log_status(struct v4l2_subdev *sd)
359 struct ad9389b_state *state = get_ad9389b_state(sd);
360 struct ad9389b_state_edid *edid = &state->edid;
362 static const char * const states[] = {
368 "initializing HDCP repeater",
369 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
371 static const char * const errors[] = {
378 "max repeater cascade exceeded",
381 "9", "A", "B", "C", "D", "E", "F"
386 v4l2_info(sd, "chip revision %d\n", state->chip_revision);
387 v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
388 v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
389 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT) ?
391 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT) ?
393 edid->segments ? "found" : "no", edid->blocks);
394 if (state->have_monitor) {
395 v4l2_info(sd, "%s output %s\n",
396 (ad9389b_rd(sd, 0xaf) & 0x02) ?
398 (ad9389b_rd(sd, 0xa1) & 0x3c) ?
399 "disabled" : "enabled");
401 v4l2_info(sd, "ad9389b: %s\n", (ad9389b_rd(sd, 0xb8) & 0x40) ?
402 "encrypted" : "no encryption");
403 v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
404 states[ad9389b_rd(sd, 0xc8) & 0xf],
405 errors[ad9389b_rd(sd, 0xc8) >> 4],
406 state->edid_detect_counter,
407 ad9389b_rd(sd, 0x94), ad9389b_rd(sd, 0x96));
408 manual_gear = ad9389b_rd(sd, 0x98) & 0x80;
409 v4l2_info(sd, "ad9389b: RGB quantization: %s range\n",
410 ad9389b_rd(sd, 0x3b) & 0x01 ? "limited" : "full");
411 v4l2_info(sd, "ad9389b: %s gear %d\n",
412 manual_gear ? "manual" : "automatic",
413 manual_gear ? ((ad9389b_rd(sd, 0x98) & 0x70) >> 4) :
414 ((ad9389b_rd(sd, 0x9e) & 0x0e) >> 1));
415 if (state->have_monitor) {
416 if (ad9389b_rd(sd, 0xaf) & 0x02) {
418 u8 manual_cts = ad9389b_rd(sd, 0x0a) & 0x80;
419 u32 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
420 ad9389b_rd(sd, 0x02) << 8 |
421 ad9389b_rd(sd, 0x03);
422 u8 vic_detect = ad9389b_rd(sd, 0x3e) >> 2;
423 u8 vic_sent = ad9389b_rd(sd, 0x3d) & 0x3f;
427 CTS = (ad9389b_rd(sd, 0x07) & 0xf) << 16 |
428 ad9389b_rd(sd, 0x08) << 8 |
429 ad9389b_rd(sd, 0x09);
431 CTS = (ad9389b_rd(sd, 0x04) & 0xf) << 16 |
432 ad9389b_rd(sd, 0x05) << 8 |
433 ad9389b_rd(sd, 0x06);
434 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
435 ad9389b_rd(sd, 0x02) << 8 |
436 ad9389b_rd(sd, 0x03);
438 v4l2_info(sd, "ad9389b: CTS %s mode: N %d, CTS %d\n",
439 manual_cts ? "manual" : "automatic", N, CTS);
441 v4l2_info(sd, "ad9389b: VIC: detected %d, sent %d\n",
442 vic_detect, vic_sent);
445 if (state->dv_timings.type == V4L2_DV_BT_656_1120)
446 v4l2_print_dv_timings(sd->name, "timings: ",
447 &state->dv_timings, false);
449 v4l2_info(sd, "no timings set\n");
453 /* Power up/down ad9389b */
454 static int ad9389b_s_power(struct v4l2_subdev *sd, int on)
456 struct ad9389b_state *state = get_ad9389b_state(sd);
457 struct ad9389b_platform_data *pdata = &state->pdata;
458 const int retries = 20;
461 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
463 state->power_on = on;
467 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
472 /* The ad9389b does not always come up immediately.
473 Retry multiple times. */
474 for (i = 0; i < retries; i++) {
475 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x0);
476 if ((ad9389b_rd(sd, 0x41) & 0x40) == 0)
478 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
482 v4l2_dbg(1, debug, sd, "failed to powerup the ad9389b\n");
483 ad9389b_s_power(sd, 0);
487 v4l2_dbg(1, debug, sd,
488 "needed %d retries to powerup the ad9389b\n", i);
490 /* Select chip: AD9389B */
491 ad9389b_wr_and_or(sd, 0xba, 0xef, 0x10);
493 /* Reserved registers that must be set according to REF_01 p. 11*/
494 ad9389b_wr_and_or(sd, 0x98, 0xf0, 0x07);
495 ad9389b_wr(sd, 0x9c, 0x38);
496 ad9389b_wr_and_or(sd, 0x9d, 0xfc, 0x01);
498 /* Differential output drive strength */
499 if (pdata->diff_data_drive_strength > 0)
500 ad9389b_wr(sd, 0xa2, pdata->diff_data_drive_strength);
502 ad9389b_wr(sd, 0xa2, 0x87);
504 if (pdata->diff_clk_drive_strength > 0)
505 ad9389b_wr(sd, 0xa3, pdata->diff_clk_drive_strength);
507 ad9389b_wr(sd, 0xa3, 0x87);
509 ad9389b_wr(sd, 0x0a, 0x01);
510 ad9389b_wr(sd, 0xbb, 0xff);
512 /* Set number of attempts to read the EDID */
513 ad9389b_wr(sd, 0xc9, 0xf);
517 /* Enable interrupts */
518 static void ad9389b_set_isr(struct v4l2_subdev *sd, bool enable)
520 u8 irqs = MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT;
524 /* The datasheet says that the EDID ready interrupt should be
525 disabled if there is no hotplug. */
528 else if (ad9389b_have_hotplug(sd))
529 irqs |= MASK_AD9389B_EDID_RDY_INT;
532 * This i2c write can fail (approx. 1 in 1000 writes). But it
533 * is essential that this register is correct, so retry it
536 * Note that the i2c write does not report an error, but the readback
537 * clearly shows the wrong value.
540 ad9389b_wr(sd, 0x94, irqs);
541 irqs_rd = ad9389b_rd(sd, 0x94);
542 } while (retries-- && irqs_rd != irqs);
545 v4l2_err(sd, "Could not set interrupts: hw failure?\n");
548 /* Interrupt handler */
549 static int ad9389b_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
553 /* disable interrupts to prevent a race condition */
554 ad9389b_set_isr(sd, false);
555 irq_status = ad9389b_rd(sd, 0x96);
556 /* clear detected interrupts */
557 ad9389b_wr(sd, 0x96, irq_status);
559 if (irq_status & (MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT))
560 ad9389b_check_monitor_present_status(sd);
561 if (irq_status & MASK_AD9389B_EDID_RDY_INT)
562 ad9389b_check_edid_status(sd);
564 /* enable interrupts */
565 ad9389b_set_isr(sd, true);
570 static const struct v4l2_subdev_core_ops ad9389b_core_ops = {
571 .log_status = ad9389b_log_status,
572 #ifdef CONFIG_VIDEO_ADV_DEBUG
573 .g_register = ad9389b_g_register,
574 .s_register = ad9389b_s_register,
576 .s_power = ad9389b_s_power,
577 .interrupt_service_routine = ad9389b_isr,
580 /* ------------------------------ VIDEO OPS ------------------------------ */
582 /* Enable/disable ad9389b output */
583 static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
585 struct ad9389b_state *state = get_ad9389b_state(sd);
587 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
589 ad9389b_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
591 ad9389b_check_monitor_present_status(sd);
593 ad9389b_s_power(sd, 0);
594 state->have_monitor = false;
599 static const struct v4l2_dv_timings_cap ad9389b_timings_cap = {
600 .type = V4L2_DV_BT_656_1120,
601 /* keep this initialization for compatibility with GCC < 4.4.6 */
603 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
604 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
605 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
606 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
607 V4L2_DV_BT_CAP_CUSTOM)
610 static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
611 struct v4l2_dv_timings *timings)
613 struct ad9389b_state *state = get_ad9389b_state(sd);
615 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
617 /* quick sanity check */
618 if (!v4l2_valid_dv_timings(timings, &ad9389b_timings_cap, NULL, NULL))
621 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
622 if the format is one of the CEA or DMT timings. */
623 v4l2_find_dv_timings_cap(timings, &ad9389b_timings_cap, 0, NULL, NULL);
625 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
628 state->dv_timings = *timings;
630 /* update quantization range based on new dv_timings */
631 ad9389b_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
633 /* update PLL gear based on new dv_timings */
634 if (state->pdata.tmds_pll_gear == AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC)
635 ad9389b_set_manual_pll_gear(sd, (u32)timings->bt.pixelclock);
637 /* update AVI infoframe */
638 ad9389b_set_IT_content_AVI_InfoFrame(sd);
643 static int ad9389b_g_dv_timings(struct v4l2_subdev *sd,
644 struct v4l2_dv_timings *timings)
646 struct ad9389b_state *state = get_ad9389b_state(sd);
648 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
653 *timings = state->dv_timings;
658 static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd,
659 struct v4l2_enum_dv_timings *timings)
661 if (timings->pad != 0)
664 return v4l2_enum_dv_timings_cap(timings, &ad9389b_timings_cap,
668 static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd,
669 struct v4l2_dv_timings_cap *cap)
674 *cap = ad9389b_timings_cap;
678 static const struct v4l2_subdev_video_ops ad9389b_video_ops = {
679 .s_stream = ad9389b_s_stream,
680 .s_dv_timings = ad9389b_s_dv_timings,
681 .g_dv_timings = ad9389b_g_dv_timings,
684 /* ------------------------------ PAD OPS ------------------------------ */
686 static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
688 struct ad9389b_state *state = get_ad9389b_state(sd);
692 if (edid->blocks == 0 || edid->blocks > 256)
694 if (!state->edid.segments) {
695 v4l2_dbg(1, debug, sd, "EDID segment 0 not found\n");
698 if (edid->start_block >= state->edid.segments * 2)
700 if (edid->blocks + edid->start_block >= state->edid.segments * 2)
701 edid->blocks = state->edid.segments * 2 - edid->start_block;
702 memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
707 static const struct v4l2_subdev_pad_ops ad9389b_pad_ops = {
708 .get_edid = ad9389b_get_edid,
709 .enum_dv_timings = ad9389b_enum_dv_timings,
710 .dv_timings_cap = ad9389b_dv_timings_cap,
713 /* ------------------------------ AUDIO OPS ------------------------------ */
715 static int ad9389b_s_audio_stream(struct v4l2_subdev *sd, int enable)
717 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
720 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x80);
722 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x40);
727 static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
732 case 32000: N = 4096; break;
733 case 44100: N = 6272; break;
734 case 48000: N = 6144; break;
735 case 88200: N = 12544; break;
736 case 96000: N = 12288; break;
737 case 176400: N = 25088; break;
738 case 192000: N = 24576; break;
743 /* Set N (used with CTS to regenerate the audio clock) */
744 ad9389b_wr(sd, 0x01, (N >> 16) & 0xf);
745 ad9389b_wr(sd, 0x02, (N >> 8) & 0xff);
746 ad9389b_wr(sd, 0x03, N & 0xff);
751 static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
756 case 32000: i2s_sf = 0x30; break;
757 case 44100: i2s_sf = 0x00; break;
758 case 48000: i2s_sf = 0x20; break;
759 case 88200: i2s_sf = 0x80; break;
760 case 96000: i2s_sf = 0xa0; break;
761 case 176400: i2s_sf = 0xc0; break;
762 case 192000: i2s_sf = 0xe0; break;
767 /* Set sampling frequency for I2S audio to 48 kHz */
768 ad9389b_wr_and_or(sd, 0x15, 0xf, i2s_sf);
773 static int ad9389b_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
775 /* TODO based on input/output/config */
776 /* TODO See datasheet "Programmers guide" p. 39-40 */
778 /* Only 2 channels in use for application */
779 ad9389b_wr_and_or(sd, 0x50, 0x1f, 0x20);
780 /* Speaker mapping */
781 ad9389b_wr(sd, 0x51, 0x00);
783 /* TODO Where should this be placed? */
784 /* 16 bit audio word length */
785 ad9389b_wr_and_or(sd, 0x14, 0xf0, 0x02);
790 static const struct v4l2_subdev_audio_ops ad9389b_audio_ops = {
791 .s_stream = ad9389b_s_audio_stream,
792 .s_clock_freq = ad9389b_s_clock_freq,
793 .s_i2s_clock_freq = ad9389b_s_i2s_clock_freq,
794 .s_routing = ad9389b_s_routing,
797 /* --------------------- SUBDEV OPS --------------------------------------- */
799 static const struct v4l2_subdev_ops ad9389b_ops = {
800 .core = &ad9389b_core_ops,
801 .video = &ad9389b_video_ops,
802 .audio = &ad9389b_audio_ops,
803 .pad = &ad9389b_pad_ops,
806 /* ----------------------------------------------------------------------- */
807 static void ad9389b_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd,
808 int segment, u8 *buf)
815 v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
816 for (i = 0; i < 256; i += 16) {
821 v4l2_dbg(lvl, debug, sd, "\n");
822 for (j = i; j < i + 16; j++) {
823 sprintf(bp, "0x%02x, ", buf[j]);
827 v4l2_dbg(lvl, debug, sd, "%s\n", b);
831 static void ad9389b_edid_handler(struct work_struct *work)
833 struct delayed_work *dwork = to_delayed_work(work);
834 struct ad9389b_state *state =
835 container_of(dwork, struct ad9389b_state, edid_handler);
836 struct v4l2_subdev *sd = &state->sd;
837 struct ad9389b_edid_detect ed;
839 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
841 if (ad9389b_check_edid_status(sd)) {
842 /* Return if we received the EDID. */
846 if (ad9389b_have_hotplug(sd)) {
847 /* We must retry reading the EDID several times, it is possible
848 * that initially the EDID couldn't be read due to i2c errors
849 * (DVI connectors are particularly prone to this problem). */
850 if (state->edid.read_retries) {
851 state->edid.read_retries--;
852 v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__);
853 state->have_monitor = false;
854 ad9389b_s_power(sd, false);
855 ad9389b_s_power(sd, true);
856 schedule_delayed_work(&state->edid_handler, EDID_DELAY);
861 /* We failed to read the EDID, so send an event for this. */
863 ed.segment = ad9389b_rd(sd, 0xc4);
864 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
865 v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
868 static void ad9389b_audio_setup(struct v4l2_subdev *sd)
870 v4l2_dbg(1, debug, sd, "%s\n", __func__);
872 ad9389b_s_i2s_clock_freq(sd, 48000);
873 ad9389b_s_clock_freq(sd, 48000);
874 ad9389b_s_routing(sd, 0, 0, 0);
877 /* Initial setup of AD9389b */
879 /* Configure hdmi transmitter. */
880 static void ad9389b_setup(struct v4l2_subdev *sd)
882 struct ad9389b_state *state = get_ad9389b_state(sd);
884 v4l2_dbg(1, debug, sd, "%s\n", __func__);
886 /* Input format: RGB 4:4:4 */
887 ad9389b_wr_and_or(sd, 0x15, 0xf1, 0x0);
888 /* Output format: RGB 4:4:4 */
889 ad9389b_wr_and_or(sd, 0x16, 0x3f, 0x0);
890 /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion,
891 Aspect ratio: 16:9 */
892 ad9389b_wr_and_or(sd, 0x17, 0xf9, 0x06);
893 /* Output format: RGB 4:4:4, Active Format Information is valid. */
894 ad9389b_wr_and_or(sd, 0x45, 0xc7, 0x08);
896 ad9389b_wr_and_or(sd, 0x46, 0x3f, 0x80);
897 /* Setup video format */
898 ad9389b_wr(sd, 0x3c, 0x0);
899 /* Active format aspect ratio: same as picure. */
900 ad9389b_wr(sd, 0x47, 0x80);
902 ad9389b_wr_and_or(sd, 0xaf, 0xef, 0x0);
903 /* Positive clk edge capture for input video clock */
904 ad9389b_wr_and_or(sd, 0xba, 0x1f, 0x60);
906 ad9389b_audio_setup(sd);
908 v4l2_ctrl_handler_setup(&state->hdl);
910 ad9389b_set_IT_content_AVI_InfoFrame(sd);
913 static void ad9389b_notify_monitor_detect(struct v4l2_subdev *sd)
915 struct ad9389b_monitor_detect mdt;
916 struct ad9389b_state *state = get_ad9389b_state(sd);
918 mdt.present = state->have_monitor;
919 v4l2_subdev_notify(sd, AD9389B_MONITOR_DETECT, (void *)&mdt);
922 static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd)
924 struct ad9389b_state *state = get_ad9389b_state(sd);
925 /* read hotplug and rx-sense state */
926 u8 status = ad9389b_rd(sd, 0x42);
928 v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
931 status & MASK_AD9389B_HPD_DETECT ? ", hotplug" : "",
932 status & MASK_AD9389B_MSEN_DETECT ? ", rx-sense" : "");
934 if ((status & MASK_AD9389B_HPD_DETECT) &&
935 ((status & MASK_AD9389B_MSEN_DETECT) || state->edid.segments)) {
936 v4l2_dbg(1, debug, sd,
937 "%s: hotplug and (rx-sense or edid)\n", __func__);
938 if (!state->have_monitor) {
939 v4l2_dbg(1, debug, sd, "%s: monitor detected\n", __func__);
940 state->have_monitor = true;
941 ad9389b_set_isr(sd, true);
942 if (!ad9389b_s_power(sd, true)) {
943 v4l2_dbg(1, debug, sd,
944 "%s: monitor detected, powerup failed\n", __func__);
948 ad9389b_notify_monitor_detect(sd);
949 state->edid.read_retries = EDID_MAX_RETRIES;
950 queue_delayed_work(state->work_queue,
951 &state->edid_handler, EDID_DELAY);
953 } else if (status & MASK_AD9389B_HPD_DETECT) {
954 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
955 state->edid.read_retries = EDID_MAX_RETRIES;
956 schedule_delayed_work(&state->edid_handler, EDID_DELAY);
957 } else if (!(status & MASK_AD9389B_HPD_DETECT)) {
958 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
959 if (state->have_monitor) {
960 v4l2_dbg(1, debug, sd, "%s: monitor not detected\n", __func__);
961 state->have_monitor = false;
962 ad9389b_notify_monitor_detect(sd);
964 ad9389b_s_power(sd, false);
965 memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
968 /* update read only ctrls */
969 v4l2_ctrl_s_ctrl(state->hotplug_ctrl, ad9389b_have_hotplug(sd) ? 0x1 : 0x0);
970 v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, ad9389b_have_rx_sense(sd) ? 0x1 : 0x0);
971 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
974 static bool edid_block_verify_crc(u8 *edid_block)
979 for (i = 0; i < 128; i++)
980 sum += edid_block[i];
984 static bool edid_segment_verify_crc(struct v4l2_subdev *sd, u32 segment)
986 struct ad9389b_state *state = get_ad9389b_state(sd);
987 u32 blocks = state->edid.blocks;
988 u8 *data = state->edid.data;
990 if (edid_block_verify_crc(&data[segment * 256])) {
991 if ((segment + 1) * 2 <= blocks)
992 return edid_block_verify_crc(&data[segment * 256 + 128]);
998 static bool ad9389b_check_edid_status(struct v4l2_subdev *sd)
1000 struct ad9389b_state *state = get_ad9389b_state(sd);
1001 struct ad9389b_edid_detect ed;
1003 u8 edidRdy = ad9389b_rd(sd, 0xc5);
1005 v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
1006 __func__, EDID_MAX_RETRIES - state->edid.read_retries);
1008 if (!(edidRdy & MASK_AD9389B_EDID_RDY))
1011 segment = ad9389b_rd(sd, 0xc4);
1012 if (segment >= EDID_MAX_SEGM) {
1013 v4l2_err(sd, "edid segment number too big\n");
1016 v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1017 ad9389b_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1018 ad9389b_dbg_dump_edid(2, debug, sd, segment,
1019 &state->edid.data[segment * 256]);
1021 state->edid.blocks = state->edid.data[0x7e] + 1;
1022 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
1023 __func__, state->edid.blocks);
1025 if (!edid_segment_verify_crc(sd, segment)) {
1026 /* edid crc error, force reread of edid segment */
1027 v4l2_err(sd, "%s: edid crc error\n", __func__);
1028 state->have_monitor = false;
1029 ad9389b_s_power(sd, false);
1030 ad9389b_s_power(sd, true);
1033 /* one more segment read ok */
1034 state->edid.segments = segment + 1;
1035 if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1036 /* Request next EDID segment */
1037 v4l2_dbg(1, debug, sd, "%s: request segment %d\n",
1038 __func__, state->edid.segments);
1039 ad9389b_wr(sd, 0xc9, 0xf);
1040 ad9389b_wr(sd, 0xc4, state->edid.segments);
1041 state->edid.read_retries = EDID_MAX_RETRIES;
1042 schedule_delayed_work(&state->edid_handler, EDID_DELAY);
1046 /* report when we have all segments but report only for segment 0 */
1049 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
1050 state->edid_detect_counter++;
1051 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1055 /* ----------------------------------------------------------------------- */
1057 static void ad9389b_init_setup(struct v4l2_subdev *sd)
1059 struct ad9389b_state *state = get_ad9389b_state(sd);
1060 struct ad9389b_state_edid *edid = &state->edid;
1062 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1064 /* clear all interrupts */
1065 ad9389b_wr(sd, 0x96, 0xff);
1067 memset(edid, 0, sizeof(struct ad9389b_state_edid));
1068 state->have_monitor = false;
1069 ad9389b_set_isr(sd, false);
1072 static int ad9389b_probe(struct i2c_client *client, const struct i2c_device_id *id)
1074 const struct v4l2_dv_timings dv1080p60 = V4L2_DV_BT_CEA_1920X1080P60;
1075 struct ad9389b_state *state;
1076 struct ad9389b_platform_data *pdata = client->dev.platform_data;
1077 struct v4l2_ctrl_handler *hdl;
1078 struct v4l2_subdev *sd;
1081 /* Check if the adapter supports the needed features */
1082 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1085 v4l_dbg(1, debug, client, "detecting ad9389b client on address 0x%x\n",
1088 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1093 if (pdata == NULL) {
1094 v4l_err(client, "No platform data!\n");
1097 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1100 v4l2_i2c_subdev_init(sd, client, &ad9389b_ops);
1101 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1104 v4l2_ctrl_handler_init(hdl, 5);
1106 state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1107 V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1108 0, V4L2_DV_TX_MODE_DVI_D);
1109 state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1110 V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
1111 state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1112 V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
1113 state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1114 V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
1115 state->rgb_quantization_range_ctrl =
1116 v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1117 V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1118 0, V4L2_DV_RGB_RANGE_AUTO);
1119 sd->ctrl_handler = hdl;
1125 state->pad.flags = MEDIA_PAD_FL_SINK;
1126 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
1130 state->chip_revision = ad9389b_rd(sd, 0x0);
1131 if (state->chip_revision != 2) {
1132 v4l2_err(sd, "chip_revision %d != 2\n", state->chip_revision);
1136 v4l2_dbg(1, debug, sd, "reg 0x41 0x%x, chip version (reg 0x00) 0x%x\n",
1137 ad9389b_rd(sd, 0x41), state->chip_revision);
1139 state->edid_i2c_client = i2c_new_dummy(client->adapter, (0x7e>>1));
1140 if (state->edid_i2c_client == NULL) {
1141 v4l2_err(sd, "failed to register edid i2c client\n");
1146 INIT_DELAYED_WORK(&state->edid_handler, ad9389b_edid_handler);
1147 state->dv_timings = dv1080p60;
1149 ad9389b_init_setup(sd);
1150 ad9389b_set_isr(sd, true);
1152 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1153 client->addr << 1, client->adapter->name);
1157 media_entity_cleanup(&sd->entity);
1159 v4l2_ctrl_handler_free(&state->hdl);
1163 /* ----------------------------------------------------------------------- */
1165 static int ad9389b_remove(struct i2c_client *client)
1167 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1168 struct ad9389b_state *state = get_ad9389b_state(sd);
1170 state->chip_revision = -1;
1172 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1173 client->addr << 1, client->adapter->name);
1175 ad9389b_s_stream(sd, false);
1176 ad9389b_s_audio_stream(sd, false);
1177 ad9389b_init_setup(sd);
1178 cancel_delayed_work_sync(&state->edid_handler);
1179 i2c_unregister_device(state->edid_i2c_client);
1180 v4l2_device_unregister_subdev(sd);
1181 media_entity_cleanup(&sd->entity);
1182 v4l2_ctrl_handler_free(sd->ctrl_handler);
1186 /* ----------------------------------------------------------------------- */
1188 static struct i2c_device_id ad9389b_id[] = {
1193 MODULE_DEVICE_TABLE(i2c, ad9389b_id);
1195 static struct i2c_driver ad9389b_driver = {
1199 .probe = ad9389b_probe,
1200 .remove = ad9389b_remove,
1201 .id_table = ad9389b_id,
1204 module_i2c_driver(ad9389b_driver);