2 * Xilinx gpio driver for xps/axi_gpio IP.
4 * Copyright 2008 - 2013 Xilinx, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
10 * You should have received a copy of the GNU General Public License
11 * along with this program; if not, write to the Free Software
12 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15 #include <linux/bitops.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/of_gpio.h>
23 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/irqdomain.h>
28 #include <linux/gpio.h>
29 #include <linux/slab.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/clk.h>
33 /* Register Offset Definitions */
34 #define XGPIO_DATA_OFFSET 0x0 /* Data register */
35 #define XGPIO_TRI_OFFSET 0x4 /* I/O direction register */
36 #define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */
37 #define XGPIO_GIER_IE BIT(31)
39 #define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */
40 #define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */
42 #define XGPIO_CHANNEL_OFFSET 0x8
44 /* Read/Write access to the GPIO registers */
45 #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARM64)
46 # define xgpio_readreg(offset) readl(offset)
47 # define xgpio_writereg(offset, val) writel(val, offset)
49 # define xgpio_readreg(offset) __raw_readl(offset)
50 # define xgpio_writereg(offset, val) __raw_writel(val, offset)
54 * struct xgpio_instance - Stores information about GPIO device
55 * @mmchip: OF GPIO chip for memory mapped banks
56 * @gpio_state: GPIO state shadow register
57 * @gpio_dir: GPIO direction shadow register
58 * @offset: GPIO channel offset
59 * @irq_base: GPIO channel irq base address
60 * @irq_enable: GPIO irq enable/disable bitfield
61 * @no_init: No intitialisation at probe
62 * @gpio_lock: Lock used for synchronization
63 * @irq_domain: irq_domain of the controller
64 * @clk: clock resource for this driver
66 struct xgpio_instance {
67 struct of_mm_gpio_chip mmchip;
75 struct irq_domain *irq_domain;
80 * xgpio_get - Read the specified signal of the GPIO device.
81 * @gc: Pointer to gpio_chip device structure.
82 * @gpio: GPIO signal number.
84 * This function reads the specified signal of the GPIO device.
87 * 0 if direction of GPIO signals is set as input otherwise it
88 * returns negative error value.
90 static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
92 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
93 struct xgpio_instance *chip =
94 container_of(mm_gc, struct xgpio_instance, mmchip);
96 void __iomem *regs = mm_gc->regs + chip->offset;
98 return !!(xgpio_readreg(regs + XGPIO_DATA_OFFSET) & BIT(gpio));
102 * xgpio_set - Write the specified signal of the GPIO device.
103 * @gc: Pointer to gpio_chip device structure.
104 * @gpio: GPIO signal number.
105 * @val: Value to be written to specified signal.
107 * This function writes the specified value in to the specified signal of the
110 static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
113 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
114 struct xgpio_instance *chip =
115 container_of(mm_gc, struct xgpio_instance, mmchip);
116 void __iomem *regs = mm_gc->regs;
118 spin_lock_irqsave(&chip->gpio_lock, flags);
120 /* Write to GPIO signal and set its direction to output */
122 chip->gpio_state |= BIT(gpio);
124 chip->gpio_state &= ~BIT(gpio);
126 xgpio_writereg(regs + chip->offset + XGPIO_DATA_OFFSET,
129 spin_unlock_irqrestore(&chip->gpio_lock, flags);
133 * xgpio_set_multiple - Write the specified signals of the GPIO device.
134 * @gc: Pointer to gpio_chip device structure.
135 * @mask: Mask of the GPIOS to modify.
136 * @bits: Value to be wrote on each GPIO
138 * This function writes the specified values into the specified signals of the
141 static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
145 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
146 struct xgpio_instance *chip =
147 container_of(mm_gc, struct xgpio_instance, mmchip);
148 void __iomem *regs = mm_gc->regs;
151 spin_lock_irqsave(&chip->gpio_lock, flags);
153 /* Write to GPIO signals */
154 for (i = 0; i < gc->ngpio; i++) {
157 if (__test_and_clear_bit(i, mask)) {
158 if (test_bit(i, bits))
159 chip->gpio_state |= BIT(i);
161 chip->gpio_state &= ~BIT(i);
165 xgpio_writereg(regs + chip->offset + XGPIO_DATA_OFFSET,
168 spin_unlock_irqrestore(&chip->gpio_lock, flags);
172 * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
173 * @gc: Pointer to gpio_chip device structure.
174 * @gpio: GPIO signal number.
176 * This function sets the direction of specified GPIO signal as input.
179 * 0 - if direction of GPIO signals is set as input
180 * otherwise it returns negative error value.
182 static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
185 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
186 struct xgpio_instance *chip =
187 container_of(mm_gc, struct xgpio_instance, mmchip);
188 void __iomem *regs = mm_gc->regs;
190 spin_lock_irqsave(&chip->gpio_lock, flags);
192 /* Set the GPIO bit in shadow register and set direction as input */
193 chip->gpio_dir |= BIT(gpio);
194 xgpio_writereg(regs + chip->offset + XGPIO_TRI_OFFSET, chip->gpio_dir);
196 spin_unlock_irqrestore(&chip->gpio_lock, flags);
202 * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
203 * @gc: Pointer to gpio_chip device structure.
204 * @gpio: GPIO signal number.
205 * @val: Value to be written to specified signal.
207 * This function sets the direction of specified GPIO signal as output.
210 * If all GPIO signals of GPIO chip is configured as input then it returns
211 * error otherwise it returns 0.
213 static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
216 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
217 struct xgpio_instance *chip =
218 container_of(mm_gc, struct xgpio_instance, mmchip);
219 void __iomem *regs = mm_gc->regs;
221 spin_lock_irqsave(&chip->gpio_lock, flags);
223 /* Write state of GPIO signal */
225 chip->gpio_state |= BIT(gpio);
227 chip->gpio_state &= ~BIT(gpio);
228 xgpio_writereg(regs + chip->offset + XGPIO_DATA_OFFSET,
231 /* Clear the GPIO bit in shadow register and set direction as output */
232 chip->gpio_dir &= ~BIT(gpio);
233 xgpio_writereg(regs + chip->offset + XGPIO_TRI_OFFSET, chip->gpio_dir);
235 spin_unlock_irqrestore(&chip->gpio_lock, flags);
241 * xgpio_save_regs - Set initial values of GPIO pins
242 * @mm_gc: Pointer to memory mapped GPIO chip structure
244 static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc)
246 struct xgpio_instance *chip =
247 container_of(mm_gc, struct xgpio_instance, mmchip);
249 chip->gpio_state = xgpio_readreg(mm_gc->regs +
251 chip->gpio_dir = xgpio_readreg(mm_gc->regs + XGPIO_TRI_OFFSET);
253 xgpio_writereg(mm_gc->regs + chip->offset + XGPIO_DATA_OFFSET,
255 xgpio_writereg(mm_gc->regs + chip->offset + XGPIO_TRI_OFFSET,
261 * xgpio_xlate - Translate gpio_spec to the GPIO number and flags
262 * @gc: Pointer to gpio_chip device structure.
263 * @gpiospec: gpio specifier as found in the device tree
264 * @flags: A flags pointer based on binding
267 * irq number otherwise -EINVAL
269 static int xgpio_xlate(struct gpio_chip *gc,
270 const struct of_phandle_args *gpiospec, u32 *flags)
272 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
273 struct xgpio_instance *chip = container_of(mm_gc, struct xgpio_instance,
275 if (gc->of_gpio_n_cells == 3 && flags)
276 *flags = gpiospec->args[2];
278 if (gpiospec->args[1] == chip->offset)
279 return gpiospec->args[0];
285 * xgpio_irq_mask - Write the specified signal of the GPIO device.
286 * @irq_data: per irq and chip data passed down to chip functions
288 static void xgpio_irq_mask(struct irq_data *irq_data)
291 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
292 struct of_mm_gpio_chip *mm_gc = &chip->mmchip;
293 u32 offset = irq_data->irq - chip->irq_base;
296 pr_debug("%s: Disable %d irq, irq_enable_mask 0x%x\n",
297 __func__, offset, chip->irq_enable);
299 spin_lock_irqsave(&chip->gpio_lock, flags);
301 chip->irq_enable &= ~BIT(offset);
303 if (!chip->irq_enable) {
304 /* Enable per channel interrupt */
305 temp = xgpio_readreg(mm_gc->regs + XGPIO_IPIER_OFFSET);
306 temp &= chip->offset / XGPIO_CHANNEL_OFFSET + 1;
307 xgpio_writereg(mm_gc->regs + XGPIO_IPIER_OFFSET, temp);
309 /* Disable global interrupt if channel interrupts are unused */
310 temp = xgpio_readreg(mm_gc->regs + XGPIO_IPIER_OFFSET);
312 xgpio_writereg(mm_gc->regs + XGPIO_GIER_OFFSET,
316 spin_unlock_irqrestore(&chip->gpio_lock, flags);
320 * xgpio_irq_unmask - Write the specified signal of the GPIO device.
321 * @irq_data: per irq and chip data passed down to chip functions
323 static void xgpio_irq_unmask(struct irq_data *irq_data)
326 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
327 struct of_mm_gpio_chip *mm_gc = &chip->mmchip;
328 u32 offset = irq_data->irq - chip->irq_base;
331 pr_debug("%s: Enable %d irq, irq_enable_mask 0x%x\n",
332 __func__, offset, chip->irq_enable);
334 /* Setup pin as input */
335 xgpio_dir_in(&mm_gc->gc, offset);
337 spin_lock_irqsave(&chip->gpio_lock, flags);
339 chip->irq_enable |= BIT(offset);
341 if (chip->irq_enable) {
343 /* Enable per channel interrupt */
344 temp = xgpio_readreg(mm_gc->regs + XGPIO_IPIER_OFFSET);
345 temp |= chip->offset / XGPIO_CHANNEL_OFFSET + 1;
346 xgpio_writereg(mm_gc->regs + XGPIO_IPIER_OFFSET, temp);
348 /* Enable global interrupts */
349 xgpio_writereg(mm_gc->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);
352 spin_unlock_irqrestore(&chip->gpio_lock, flags);
356 * xgpio_set_irq_type - Write the specified signal of the GPIO device.
357 * @irq_data: Per irq and chip data passed down to chip functions
358 * @type: Interrupt type that is to be set for the gpio pin
361 * 0 if interrupt type is supported otherwise otherwise -EINVAL
363 static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
365 /* Only rising edge case is supported now */
366 if (type & IRQ_TYPE_EDGE_RISING)
372 /* irq chip descriptor */
373 static struct irq_chip xgpio_irqchip = {
375 .irq_mask = xgpio_irq_mask,
376 .irq_unmask = xgpio_irq_unmask,
377 .irq_set_type = xgpio_set_irq_type,
381 * xgpio_to_irq - Find out gpio to Linux irq mapping
382 * @gc: Pointer to gpio_chip device structure.
383 * @offset: Gpio pin offset
386 * irq number otherwise -EINVAL
388 static int xgpio_to_irq(struct gpio_chip *gc, unsigned int offset)
390 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
391 struct xgpio_instance *chip = container_of(mm_gc, struct xgpio_instance,
394 return irq_find_mapping(chip->irq_domain, offset);
398 * xgpio_irqhandler - Gpio interrupt service routine
399 * @desc: Pointer to interrupt description
401 static void xgpio_irqhandler(struct irq_desc *desc)
403 unsigned int irq = irq_desc_get_irq(desc);
405 struct xgpio_instance *chip = (struct xgpio_instance *)
406 irq_get_handler_data(irq);
407 struct of_mm_gpio_chip *mm_gc = &chip->mmchip;
408 struct irq_chip *irqchip = irq_desc_get_chip(desc);
412 chained_irq_enter(irqchip, desc);
414 val = xgpio_readreg(mm_gc->regs + chip->offset);
415 /* Only rising edge is supported */
416 val &= chip->irq_enable;
418 for_each_set_bit(offset, &val, chip->mmchip.gc.ngpio) {
419 generic_handle_irq(chip->irq_base + offset);
422 xgpio_writereg(mm_gc->regs + XGPIO_IPISR_OFFSET,
423 chip->offset / XGPIO_CHANNEL_OFFSET + 1);
425 chained_irq_exit(irqchip, desc);
428 static struct lock_class_key gpio_lock_class;
431 * xgpio_irq_setup - Allocate irq for gpio and setup appropriate functions
432 * @np: Device node of the GPIO chip
433 * @chip: Pointer to private gpio channel structure
436 * 0 if success, otherwise -1
438 static int xgpio_irq_setup(struct device_node *np, struct xgpio_instance *chip)
443 int ret = of_irq_to_resource(np, 0, &res);
446 pr_info("GPIO IRQ not connected\n");
450 chip->mmchip.gc.to_irq = xgpio_to_irq;
452 chip->irq_base = irq_alloc_descs(-1, 0, chip->mmchip.gc.ngpio, 0);
453 if (chip->irq_base < 0) {
454 pr_err("Couldn't allocate IRQ numbers\n");
457 chip->irq_domain = irq_domain_add_legacy(np, chip->mmchip.gc.ngpio,
459 &irq_domain_simple_ops, NULL);
462 * set the irq chip, handler and irq chip data for callbacks for
465 for (pin_num = 0; pin_num < chip->mmchip.gc.ngpio; pin_num++) {
466 u32 gpio_irq = irq_find_mapping(chip->irq_domain, pin_num);
468 irq_set_lockdep_class(gpio_irq, &gpio_lock_class);
469 pr_debug("IRQ Base: %d, Pin %d = IRQ %d\n",
470 chip->irq_base, pin_num, gpio_irq);
471 irq_set_chip_and_handler(gpio_irq, &xgpio_irqchip,
473 irq_set_chip_data(gpio_irq, (void *)chip);
475 irq_set_handler_data(res.start, (void *)chip);
476 irq_set_chained_handler(res.start, xgpio_irqhandler);
481 static int xgpio_request(struct gpio_chip *chip, unsigned int offset)
483 int ret = pm_runtime_get_sync(chip->parent);
486 * If the device is already active pm_runtime_get() will return 1 on
487 * success, but gpio_request still needs to return 0.
489 return ret < 0 ? ret : 0;
492 static void xgpio_free(struct gpio_chip *chip, unsigned int offset)
494 pm_runtime_put(chip->parent);
497 static int __maybe_unused xgpio_suspend(struct device *dev)
499 struct platform_device *pdev = to_platform_device(dev);
501 struct irq_data *data;
503 irq = platform_get_irq(pdev, 0);
505 dev_dbg(dev, "failed to get IRQ\n");
509 data = irq_get_irq_data(irq);
510 if (!irqd_is_wakeup_set(data))
511 return pm_runtime_force_suspend(dev);
516 static int __maybe_unused xgpio_resume(struct device *dev)
518 struct platform_device *pdev = to_platform_device(dev);
520 struct irq_data *data;
523 irq = platform_get_irq(pdev, 0);
525 dev_dbg(dev, "failed to get IRQ\n");
529 data = irq_get_irq_data(irq);
530 if (!irqd_is_wakeup_set(data))
531 return pm_runtime_force_resume(dev);
536 static int __maybe_unused xgpio_runtime_suspend(struct device *dev)
538 struct platform_device *pdev = to_platform_device(dev);
539 struct xgpio_instance *gpio = platform_get_drvdata(pdev);
541 clk_disable(gpio->clk);
546 static int __maybe_unused xgpio_runtime_resume(struct device *dev)
548 struct platform_device *pdev = to_platform_device(dev);
549 struct xgpio_instance *gpio = platform_get_drvdata(pdev);
551 return clk_enable(gpio->clk);
554 static const struct dev_pm_ops xgpio_dev_pm_ops = {
555 SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume)
556 SET_RUNTIME_PM_OPS(xgpio_runtime_suspend,
557 xgpio_runtime_resume, NULL)
561 * xgpio_remove - Remove method for the GPIO device.
562 * @pdev: pointer to the platform device
564 * This function remove gpiochips and frees all the allocated resources.
568 static int xgpio_remove(struct platform_device *pdev)
570 struct xgpio_instance *chip = platform_get_drvdata(pdev);
572 of_mm_gpiochip_remove(&chip->mmchip);
573 clk_disable_unprepare(chip->clk);
574 pm_runtime_disable(&pdev->dev);
580 * xgpio_of_probe - Probe method for the GPIO device.
581 * @pdev: platform device instance
583 * This function probes the GPIO device in the device tree. It initializes the
584 * driver data structure.
587 * It returns 0, if the driver is bound to the GPIO device, or
588 * a negative value if there is an error.
590 static int xgpio_of_probe(struct platform_device *pdev)
592 struct device_node *np = pdev->dev.of_node;
593 struct xgpio_instance *chip;
595 const u32 *tree_info;
599 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
603 /* Update GPIO state shadow register with default value */
604 of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state);
606 /* By default, all pins are inputs */
607 chip->gpio_dir = 0xFFFFFFFF;
609 /* Update GPIO direction shadow register with default value */
610 of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir);
612 chip->no_init = of_property_read_bool(np, "xlnx,no-init");
614 /* Update cells with gpio-cells value */
615 of_property_read_u32(np, "#gpio-cells", &cells);
618 * Check device node and parent device node for device width
619 * and assume default width of 32
621 if (of_property_read_u32(np, "xlnx,gpio-width", &ngpio))
623 chip->mmchip.gc.ngpio = (u16)ngpio;
625 spin_lock_init(&chip->gpio_lock);
627 chip->mmchip.gc.parent = &pdev->dev;
628 chip->mmchip.gc.owner = THIS_MODULE;
629 chip->mmchip.gc.of_xlate = xgpio_xlate;
630 chip->mmchip.gc.of_gpio_n_cells = cells;
631 chip->mmchip.gc.direction_input = xgpio_dir_in;
632 chip->mmchip.gc.direction_output = xgpio_dir_out;
633 chip->mmchip.gc.get = xgpio_get;
634 chip->mmchip.gc.set = xgpio_set;
635 chip->mmchip.gc.request = xgpio_request;
636 chip->mmchip.gc.free = xgpio_free;
637 chip->mmchip.gc.set_multiple = xgpio_set_multiple;
639 chip->mmchip.save_regs = xgpio_save_regs;
641 platform_set_drvdata(pdev, chip);
643 chip->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
644 if (IS_ERR(chip->clk)) {
645 if ((PTR_ERR(chip->clk) != -ENOENT) ||
646 (PTR_ERR(chip->clk) != -EPROBE_DEFER)) {
647 dev_err(&pdev->dev, "Input clock not found\n");
648 return PTR_ERR(chip->clk);
652 * Clock framework support is optional, continue on
653 * anyways if we don't find a matching clock.
658 status = clk_prepare_enable(chip->clk);
660 dev_err(&pdev->dev, "Failed to prepare clk\n");
664 pm_runtime_enable(&pdev->dev);
665 status = pm_runtime_get_sync(&pdev->dev);
667 goto err_unprepare_clk;
669 /* Call the OF gpio helper to setup and register the GPIO device */
670 status = of_mm_gpiochip_add(np, &chip->mmchip);
672 pr_err("%pOF: error in probe function with status %d\n",
677 status = xgpio_irq_setup(np, chip);
679 pr_err("%s: GPIO IRQ initialization failed %d\n",
680 np->full_name, status);
684 pr_info("XGpio: %s: registered, base is %d\n", np->full_name,
685 chip->mmchip.gc.base);
687 tree_info = of_get_property(np, "xlnx,is-dual", NULL);
688 if (tree_info && be32_to_cpup(tree_info)) {
689 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
693 /* Add dual channel offset */
694 chip->offset = XGPIO_CHANNEL_OFFSET;
696 /* Update GPIO state shadow register with default value */
697 of_property_read_u32(np, "xlnx,dout-default-2",
700 /* By default, all pins are inputs */
701 chip->gpio_dir = 0xFFFFFFFF;
703 /* Update GPIO direction shadow register with default value */
704 of_property_read_u32(np, "xlnx,tri-default-2", &chip->gpio_dir);
707 * Check device node and parent device node for device width
708 * and assume default width of 32
710 if (of_property_read_u32(np, "xlnx,gpio2-width", &ngpio))
712 chip->mmchip.gc.ngpio = (u16)ngpio;
714 spin_lock_init(&chip->gpio_lock);
716 chip->mmchip.gc.parent = &pdev->dev;
717 chip->mmchip.gc.owner = THIS_MODULE;
718 chip->mmchip.gc.of_xlate = xgpio_xlate;
719 chip->mmchip.gc.of_gpio_n_cells = cells;
720 chip->mmchip.gc.direction_input = xgpio_dir_in;
721 chip->mmchip.gc.direction_output = xgpio_dir_out;
722 chip->mmchip.gc.get = xgpio_get;
723 chip->mmchip.gc.set = xgpio_set;
724 chip->mmchip.gc.request = xgpio_request;
725 chip->mmchip.gc.free = xgpio_free;
726 chip->mmchip.gc.set_multiple = xgpio_set_multiple;
728 chip->mmchip.save_regs = xgpio_save_regs;
730 status = xgpio_irq_setup(np, chip);
732 pr_err("%s: GPIO IRQ initialization failed %d\n",
733 np->full_name, status);
737 /* Call the OF gpio helper to setup and register the GPIO dev */
738 status = of_mm_gpiochip_add(np, &chip->mmchip);
740 pr_err("%s: error in probe function with status %d\n",
741 np->full_name, status);
744 pr_info("XGpio: %s: dual channel registered, base is %d\n",
745 np->full_name, chip->mmchip.gc.base);
748 pm_runtime_put(&pdev->dev);
752 pm_runtime_put(&pdev->dev);
754 pm_runtime_disable(&pdev->dev);
755 clk_disable_unprepare(chip->clk);
759 static const struct of_device_id xgpio_of_match[] = {
760 { .compatible = "xlnx,xps-gpio-1.00.a", },
761 { /* end of list */ },
763 MODULE_DEVICE_TABLE(of, xgpio_of_match);
765 static struct platform_driver xilinx_gpio_driver = {
766 .probe = xgpio_of_probe,
767 .remove = xgpio_remove,
769 .name = "xilinx-gpio",
770 .of_match_table = xgpio_of_match,
771 .pm = &xgpio_dev_pm_ops,
775 static int __init xgpio_init(void)
777 return platform_driver_register(&xilinx_gpio_driver);
780 /* Make sure we get initialized before anyone else tries to use us */
781 subsys_initcall(xgpio_init);
783 static void __exit xgpio_exit(void)
785 platform_driver_unregister(&xilinx_gpio_driver);
787 module_exit(xgpio_exit);
789 MODULE_AUTHOR("Xilinx, Inc.");
790 MODULE_DESCRIPTION("Xilinx GPIO driver");
791 MODULE_LICENSE("GPL");