arch/arm64/boot/dts/xilinx/zynqmp.dtsi

   1 /*
   2  * dts file for Xilinx ZynqMP
   3  *
   4  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 / {
  12         compatible = "xlnx,zynqmp";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu0: cpu@0 {
  21                         compatible = "arm,cortex-a53", "arm,armv8";
  22                         device_type = "cpu";
  23                         enable-method = "psci";
  24                         operating-points-v2 = <&cpu_opp_table>;
  25                         reg = <0x0>;
  26                         cpu-idle-states = <&CPU_SLEEP_0>;
  27                 };
  28
  29                 cpu1: cpu@1 {
  30                         compatible = "arm,cortex-a53", "arm,armv8";
  31                         device_type = "cpu";
  32                         enable-method = "psci";
  33                         reg = <0x1>;
  34                         operating-points-v2 = <&cpu_opp_table>;
  35                         cpu-idle-states = <&CPU_SLEEP_0>;
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         compatible = "arm,cortex-a53", "arm,armv8";
  40                         device_type = "cpu";
  41                         enable-method = "psci";
  42                         reg = <0x2>;
  43                         operating-points-v2 = <&cpu_opp_table>;
  44                         cpu-idle-states = <&CPU_SLEEP_0>;
  45                 };
  46
  47                 cpu3: cpu@3 {
  48                         compatible = "arm,cortex-a53", "arm,armv8";
  49                         device_type = "cpu";
  50                         enable-method = "psci";
  51                         reg = <0x3>;
  52                         operating-points-v2 = <&cpu_opp_table>;
  53                         cpu-idle-states = <&CPU_SLEEP_0>;
  54                 };
  55
  56                 idle-states {
  57                         entry-method = "arm,psci";
  58
  59                         CPU_SLEEP_0: cpu-sleep-0 {
  60                                 compatible = "arm,idle-state";
  61                                 arm,psci-suspend-param = <0x40000000>;
  62                                 local-timer-stop;
  63                                 entry-latency-us = <300>;
  64                                 exit-latency-us = <600>;
  65                                 min-residency-us = <10000>;
  66                         };
  67                 };
  68         };
  69
  70         cpu_opp_table: cpu_opp_table {
  71                 compatible = "operating-points-v2";
  72                 opp-shared;
  73                 opp00 {
  74                         opp-hz = /bits/ 64 <1199999988>;
  75                         opp-microvolt = <1000000>;
  76                         clock-latency-ns = <500000>;
  77                 };
  78                 opp01 {
  79                         opp-hz = /bits/ 64 <599999994>;
  80                         opp-microvolt = <1000000>;
  81                         clock-latency-ns = <500000>;
  82                 };
  83                 opp02 {
  84                         opp-hz = /bits/ 64 <399999996>;
  85                         opp-microvolt = <1000000>;
  86                         clock-latency-ns = <500000>;
  87                 };
  88                 opp03 {
  89                         opp-hz = /bits/ 64 <299999997>;
  90                         opp-microvolt = <1000000>;
  91                         clock-latency-ns = <500000>;
  92                 };
  93         };
  94
  95         dcc: dcc {
  96                 compatible = "arm,dcc";
  97                 status = "disabled";
  98                 u-boot,dm-pre-reloc;
  99         };
 100
 101         pinctrl0: pinctrl {
 102                 compatible = "xlnx,zynqmp-pinctrl";
 103                 status = "disabled";
 104         };
 105
 106         power-domains {
 107                 compatible = "xlnx,zynqmp-genpd";
 108
 109                 pd_usb0: pd-usb0 {
 110                         #power-domain-cells = <0x0>;
 111                         pd-id = <0x16>;
 112                 };
 113
 114                 pd_usb1: pd-usb1 {
 115                         #power-domain-cells = <0x0>;
 116                         pd-id = <0x17>;
 117                 };
 118
 119                 pd_sata: pd-sata {
 120                         #power-domain-cells = <0x0>;
 121                         pd-id = <0x1c>;
 122                 };
 123
 124                 pd_spi0: pd-spi0 {
 125                         #power-domain-cells = <0x0>;
 126                         pd-id = <0x23>;
 127                 };
 128
 129                 pd_spi1: pd-spi1 {
 130                         #power-domain-cells = <0x0>;
 131                         pd-id = <0x24>;
 132                 };
 133
 134                 pd_uart0: pd-uart0 {
 135                         #power-domain-cells = <0x0>;
 136                         pd-id = <0x21>;
 137                 };
 138
 139                 pd_uart1: pd-uart1 {
 140                         #power-domain-cells = <0x0>;
 141                         pd-id = <0x22>;
 142                 };
 143
 144                 pd_eth0: pd-eth0 {
 145                         #power-domain-cells = <0x0>;
 146                         pd-id = <0x1d>;
 147                 };
 148
 149                 pd_eth1: pd-eth1 {
 150                         #power-domain-cells = <0x0>;
 151                         pd-id = <0x1e>;
 152                 };
 153
 154                 pd_eth2: pd-eth2 {
 155                         #power-domain-cells = <0x0>;
 156                         pd-id = <0x1f>;
 157                 };
 158
 159                 pd_eth3: pd-eth3 {
 160                         #power-domain-cells = <0x0>;
 161                         pd-id = <0x20>;
 162                 };
 163
 164                 pd_i2c0: pd-i2c0 {
 165                         #power-domain-cells = <0x0>;
 166                         pd-id = <0x25>;
 167                 };
 168
 169                 pd_i2c1: pd-i2c1 {
 170                         #power-domain-cells = <0x0>;
 171                         pd-id = <0x26>;
 172                 };
 173
 174                 pd_dp: pd-dp {
 175                         #power-domain-cells = <0x0>;
 176                         pd-id = <0x29>;
 177                 };
 178
 179                 pd_gdma: pd-gdma {
 180                         #power-domain-cells = <0x0>;
 181                         pd-id = <0x2a>;
 182                 };
 183
 184                 pd_adma: pd-adma {
 185                         #power-domain-cells = <0x0>;
 186                         pd-id = <0x2b>;
 187                 };
 188
 189                 pd_ttc0: pd-ttc0 {
 190                         #power-domain-cells = <0x0>;
 191                         pd-id = <0x18>;
 192                 };
 193
 194                 pd_ttc1: pd-ttc1 {
 195                         #power-domain-cells = <0x0>;
 196                         pd-id = <0x19>;
 197                 };
 198
 199                 pd_ttc2: pd-ttc2 {
 200                         #power-domain-cells = <0x0>;
 201                         pd-id = <0x1a>;
 202                 };
 203
 204                 pd_ttc3: pd-ttc3 {
 205                         #power-domain-cells = <0x0>;
 206                         pd-id = <0x1b>;
 207                 };
 208
 209                 pd_sd0: pd-sd0 {
 210                         #power-domain-cells = <0x0>;
 211                         pd-id = <0x27>;
 212                 };
 213
 214                 pd_sd1: pd-sd1 {
 215                         #power-domain-cells = <0x0>;
 216                         pd-id = <0x28>;
 217                 };
 218
 219                 pd_nand: pd-nand {
 220                         #power-domain-cells = <0x0>;
 221                         pd-id = <0x2c>;
 222                 };
 223
 224                 pd_qspi: pd-qspi {
 225                         #power-domain-cells = <0x0>;
 226                         pd-id = <0x2d>;
 227                 };
 228
 229                 pd_gpio: pd-gpio {
 230                         #power-domain-cells = <0x0>;
 231                         pd-id = <0x2e>;
 232                 };
 233
 234                 pd_can0: pd-can0 {
 235                         #power-domain-cells = <0x0>;
 236                         pd-id = <0x2f>;
 237                 };
 238
 239                 pd_can1: pd-can1 {
 240                         #power-domain-cells = <0x0>;
 241                         pd-id = <0x30>;
 242                 };
 243
 244                 pd_pcie: pd-pcie {
 245                         #power-domain-cells = <0x0>;
 246                         pd-id = <0x3b>;
 247                 };
 248
 249                 pd_gpu: pd-gpu {
 250                         #power-domain-cells = <0x0>;
 251                         pd-id = <0x3a 0x14 0x15>;
 252                 };
 253         };
 254
 255         /* PMU1<->APU IPI mailbox controller */
 256         ipi_mailbox_pmu1: mailbox@ff990400 {
 257                 compatible = "xlnx,zynqmp-ipi-mailbox";
 258                 reg = <0x0 0xff9905c0 0x0 0x20>,
 259                       <0x0 0xff9905e0 0x0 0x20>,
 260                       <0x0 0xff990e80 0x0 0x20>,
 261                       <0x0 0xff990ea0 0x0 0x20>;
 262                 reg-names = "local_request_region", "local_response_region",
 263                             "remote_request_region", "remote_response_region";
 264                 #mbox-cells = <1>;
 265                 xlnx,ipi-ids = <0 4>;
 266                 interrupt-parent = <&gic>;
 267                 interrupts = <0 35 4>;
 268         };
 269
 270         pmu {
 271                 compatible = "arm,armv8-pmuv3";
 272                 interrupt-parent = <&gic>;
 273                 interrupts = <0 143 4>,
 274                              <0 144 4>,
 275                              <0 145 4>,
 276                              <0 146 4>;
 277         };
 278
 279         psci {
 280                 compatible = "arm,psci-0.2";
 281                 method = "smc";
 282         };
 283
 284         firmware {
 285                 zynqmp_firmware: zynqmp-firmware {
 286                         compatible = "xlnx,zynqmp-firmware";
 287                         method = "smc";
 288                 };
 289         };
 290
 291         zynqmp_power: zynqmp-power {
 292                 compatible = "xlnx,zynqmp-power";
 293                 mboxes = <&ipi_mailbox_pmu1 0>,
 294                          <&ipi_mailbox_pmu1 1>;
 295                 mbox-names = "tx", "rx";
 296         };
 297
 298         timer {
 299                 compatible = "arm,armv8-timer";
 300                 interrupt-parent = <&gic>;
 301                 interrupts = <1 13 0xf08>,
 302                              <1 14 0xf08>,
 303                              <1 11 0xf08>,
 304                              <1 10 0xf08>;
 305         };
 306
 307         edac {
 308                 compatible = "arm,cortex-a53-edac";
 309         };
 310
 311         fpga_full: fpga-full {
 312                 compatible = "fpga-region";
 313                 fpga-mgr = <&pcap>;
 314                 #address-cells = <2>;
 315                 #size-cells = <2>;
 316         };
 317
 318         nvmem_firmware {
 319                 compatible = "xlnx,zynqmp-nvmem-fw";
 320                 #address-cells = <1>;
 321                 #size-cells = <1>;
 322
 323                 soc_revision: soc_revision@0 {
 324                         reg = <0x0 0x4>;
 325                 };
 326         };
 327
 328         pcap: pcap {
 329                 compatible = "xlnx,zynqmp-pcap-fpga";
 330         };
 331
 332         rst: reset-controller {
 333                 compatible = "xlnx,zynqmp-reset";
 334                 #reset-cells = <1>;
 335         };
 336
 337         xlnx_rsa: zynqmp_rsa {
 338                 compatible = "xlnx,zynqmp-rsa";
 339         };
 340
 341         xlnx_keccak_384: sha384 {
 342                 compatible = "xlnx,zynqmp-keccak-384";
 343         };
 344
 345         xlnx_dp_snd_card: dp_snd_card {
 346                 compatible = "xlnx,dp-snd-card";
 347                 status = "disabled";
 348                 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
 349                 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
 350         };
 351
 352         xlnx_dp_snd_codec0: dp_snd_codec0 {
 353                 compatible = "xlnx,dp-snd-codec";
 354                 status = "disabled";
 355                 clock-names = "aud_clk";
 356         };
 357
 358         xlnx_dp_snd_pcm0: dp_snd_pcm0 {
 359                 compatible = "xlnx,dp-snd-pcm";
 360                 status = "disabled";
 361                 dmas = <&xlnx_dpdma 4>;
 362                 dma-names = "tx";
 363         };
 364
 365         xlnx_dp_snd_pcm1: dp_snd_pcm1 {
 366                 compatible = "xlnx,dp-snd-pcm";
 367                 status = "disabled";
 368                 dmas = <&xlnx_dpdma 5>;
 369                 dma-names = "tx";
 370         };
 371
 372         xilinx_drm: xilinx_drm {
 373                 compatible = "xlnx,drm";
 374                 status = "disabled";
 375                 xlnx,encoder-slave = <&xlnx_dp>;
 376                 xlnx,connector-type = "DisplayPort";
 377                 xlnx,dp-sub = <&xlnx_dp_sub>;
 378                 planes {
 379                         xlnx,pixel-format = "rgb565";
 380                         plane0 {
 381                                 dmas = <&xlnx_dpdma 3>;
 382                                 dma-names = "dma0";
 383                         };
 384                         plane1 {
 385                                 dmas = <&xlnx_dpdma 0>,
 386                                         <&xlnx_dpdma 1>,
 387                                         <&xlnx_dpdma 2>;
 388                                 dma-names = "dma0", "dma1", "dma2";
 389                         };
 390                 };
 391         };
 392
 393         amba_apu: amba_apu@0 {
 394                 compatible = "simple-bus";
 395                 #address-cells = <2>;
 396                 #size-cells = <1>;
 397                 ranges = <0 0 0 0 0xffffffff>;
 398
 399                 gic: interrupt-controller@f9010000 {
 400                         compatible = "arm,gic-400", "arm,cortex-a15-gic";
 401                         #interrupt-cells = <3>;
 402                         reg = <0x0 0xf9010000 0x10000>,
 403                               <0x0 0xf9020000 0x20000>,
 404                               <0x0 0xf9040000 0x20000>,
 405                               <0x0 0xf9060000 0x20000>;
 406                         interrupt-controller;
 407                         interrupt-parent = <&gic>;
 408                         interrupts = <1 9 0xf04>;
 409                 };
 410         };
 411
 412         amba: amba {
 413                 compatible = "simple-bus";
 414                 u-boot,dm-pre-reloc;
 415                 #address-cells = <2>;
 416                 #size-cells = <2>;
 417                 ranges;
 418
 419                 can0: can@ff060000 {
 420                         compatible = "xlnx,zynq-can-1.0";
 421                         status = "disabled";
 422                         clock-names = "can_clk", "pclk";
 423                         reg = <0x0 0xff060000 0x0 0x1000>;
 424                         interrupts = <0 23 4>;
 425                         interrupt-parent = <&gic>;
 426                         tx-fifo-depth = <0x40>;
 427                         rx-fifo-depth = <0x40>;
 428                         power-domains = <&pd_can0>;
 429                 };
 430
 431                 can1: can@ff070000 {
 432                         compatible = "xlnx,zynq-can-1.0";
 433                         status = "disabled";
 434                         clock-names = "can_clk", "pclk";
 435                         reg = <0x0 0xff070000 0x0 0x1000>;
 436                         interrupts = <0 24 4>;
 437                         interrupt-parent = <&gic>;
 438                         tx-fifo-depth = <0x40>;
 439                         rx-fifo-depth = <0x40>;
 440                         power-domains = <&pd_can1>;
 441                 };
 442
 443                 cci: cci@fd6e0000 {
 444                         compatible = "arm,cci-400";
 445                         reg = <0x0 0xfd6e0000 0x0 0x9000>;
 446                         ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 447                         #address-cells = <1>;
 448                         #size-cells = <1>;
 449
 450                         pmu@9000 {
 451                                 compatible = "arm,cci-400-pmu,r1";
 452                                 reg = <0x9000 0x5000>;
 453                                 interrupt-parent = <&gic>;
 454                                 interrupts = <0 123 4>,
 455                                              <0 123 4>,
 456                                              <0 123 4>,
 457                                              <0 123 4>,
 458                                              <0 123 4>;
 459                         };
 460                 };
 461
 462                 /* GDMA */
 463                 fpd_dma_chan1: dma@fd500000 {
 464                         status = "disabled";
 465                         compatible = "xlnx,zynqmp-dma-1.0";
 466                         reg = <0x0 0xfd500000 0x0 0x1000>;
 467                         interrupt-parent = <&gic>;
 468                         interrupts = <0 124 4>;
 469                         clock-names = "clk_main", "clk_apb";
 470                         xlnx,bus-width = <128>;
 471                         #stream-id-cells = <1>;
 472                         iommus = <&smmu 0x14e8>;
 473                         power-domains = <&pd_gdma>;
 474                 };
 475
 476                 fpd_dma_chan2: dma@fd510000 {
 477                         status = "disabled";
 478                         compatible = "xlnx,zynqmp-dma-1.0";
 479                         reg = <0x0 0xfd510000 0x0 0x1000>;
 480                         interrupt-parent = <&gic>;
 481                         interrupts = <0 125 4>;
 482                         clock-names = "clk_main", "clk_apb";
 483                         xlnx,bus-width = <128>;
 484                         #stream-id-cells = <1>;
 485                         iommus = <&smmu 0x14e9>;
 486                         power-domains = <&pd_gdma>;
 487                 };
 488
 489                 fpd_dma_chan3: dma@fd520000 {
 490                         status = "disabled";
 491                         compatible = "xlnx,zynqmp-dma-1.0";
 492                         reg = <0x0 0xfd520000 0x0 0x1000>;
 493                         interrupt-parent = <&gic>;
 494                         interrupts = <0 126 4>;
 495                         clock-names = "clk_main", "clk_apb";
 496                         xlnx,bus-width = <128>;
 497                         #stream-id-cells = <1>;
 498                         iommus = <&smmu 0x14ea>;
 499                         power-domains = <&pd_gdma>;
 500                 };
 501
 502                 fpd_dma_chan4: dma@fd530000 {
 503                         status = "disabled";
 504                         compatible = "xlnx,zynqmp-dma-1.0";
 505                         reg = <0x0 0xfd530000 0x0 0x1000>;
 506                         interrupt-parent = <&gic>;
 507                         interrupts = <0 127 4>;
 508                         clock-names = "clk_main", "clk_apb";
 509                         xlnx,bus-width = <128>;
 510                         #stream-id-cells = <1>;
 511                         iommus = <&smmu 0x14eb>;
 512                         power-domains = <&pd_gdma>;
 513                 };
 514
 515                 fpd_dma_chan5: dma@fd540000 {
 516                         status = "disabled";
 517                         compatible = "xlnx,zynqmp-dma-1.0";
 518                         reg = <0x0 0xfd540000 0x0 0x1000>;
 519                         interrupt-parent = <&gic>;
 520                         interrupts = <0 128 4>;
 521                         clock-names = "clk_main", "clk_apb";
 522                         xlnx,bus-width = <128>;
 523                         #stream-id-cells = <1>;
 524                         iommus = <&smmu 0x14ec>;
 525                         power-domains = <&pd_gdma>;
 526                 };
 527
 528                 fpd_dma_chan6: dma@fd550000 {
 529                         status = "disabled";
 530                         compatible = "xlnx,zynqmp-dma-1.0";
 531                         reg = <0x0 0xfd550000 0x0 0x1000>;
 532                         interrupt-parent = <&gic>;
 533                         interrupts = <0 129 4>;
 534                         clock-names = "clk_main", "clk_apb";
 535                         xlnx,bus-width = <128>;
 536                         #stream-id-cells = <1>;
 537                         iommus = <&smmu 0x14ed>;
 538                         power-domains = <&pd_gdma>;
 539                 };
 540
 541                 fpd_dma_chan7: dma@fd560000 {
 542                         status = "disabled";
 543                         compatible = "xlnx,zynqmp-dma-1.0";
 544                         reg = <0x0 0xfd560000 0x0 0x1000>;
 545                         interrupt-parent = <&gic>;
 546                         interrupts = <0 130 4>;
 547                         clock-names = "clk_main", "clk_apb";
 548                         xlnx,bus-width = <128>;
 549                         #stream-id-cells = <1>;
 550                         iommus = <&smmu 0x14ee>;
 551                         power-domains = <&pd_gdma>;
 552                 };
 553
 554                 fpd_dma_chan8: dma@fd570000 {
 555                         status = "disabled";
 556                         compatible = "xlnx,zynqmp-dma-1.0";
 557                         reg = <0x0 0xfd570000 0x0 0x1000>;
 558                         interrupt-parent = <&gic>;
 559                         interrupts = <0 131 4>;
 560                         clock-names = "clk_main", "clk_apb";
 561                         xlnx,bus-width = <128>;
 562                         #stream-id-cells = <1>;
 563                         iommus = <&smmu 0x14ef>;
 564                         power-domains = <&pd_gdma>;
 565                 };
 566
 567                 gpu: gpu@fd4b0000 {
 568                         status = "disabled";
 569                         compatible = "arm,mali-400", "arm,mali-utgard";
 570                         reg = <0x0 0xfd4b0000 0x0 0x10000>;
 571                         interrupt-parent = <&gic>;
 572                         interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 573                         interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
 574                         clock-names = "gpu", "gpu_pp0", "gpu_pp1";
 575                         power-domains = <&pd_gpu>;
 576                 };
 577
 578                 /* LPDDMA default allows only secured access. inorder to enable
 579                  * These dma channels, Users should ensure that these dma
 580                  * Channels are allowed for non secure access.
 581                  */
 582                 lpd_dma_chan1: dma@ffa80000 {
 583                         status = "disabled";
 584                         compatible = "xlnx,zynqmp-dma-1.0";
 585                         reg = <0x0 0xffa80000 0x0 0x1000>;
 586                         interrupt-parent = <&gic>;
 587                         interrupts = <0 77 4>;
 588                         clock-names = "clk_main", "clk_apb";
 589                         xlnx,bus-width = <64>;
 590                         #stream-id-cells = <1>;
 591                         /* iommus = <&smmu 0x868>; */
 592                         power-domains = <&pd_adma>;
 593                 };
 594
 595                 lpd_dma_chan2: dma@ffa90000 {
 596                         status = "disabled";
 597                         compatible = "xlnx,zynqmp-dma-1.0";
 598                         reg = <0x0 0xffa90000 0x0 0x1000>;
 599                         interrupt-parent = <&gic>;
 600                         interrupts = <0 78 4>;
 601                         clock-names = "clk_main", "clk_apb";
 602                         xlnx,bus-width = <64>;
 603                         #stream-id-cells = <1>;
 604                         /* iommus = <&smmu 0x869>; */
 605                         power-domains = <&pd_adma>;
 606                 };
 607
 608                 lpd_dma_chan3: dma@ffaa0000 {
 609                         status = "disabled";
 610                         compatible = "xlnx,zynqmp-dma-1.0";
 611                         reg = <0x0 0xffaa0000 0x0 0x1000>;
 612                         interrupt-parent = <&gic>;
 613                         interrupts = <0 79 4>;
 614                         clock-names = "clk_main", "clk_apb";
 615                         xlnx,bus-width = <64>;
 616                         #stream-id-cells = <1>;
 617                         /* iommus = <&smmu 0x86a>; */
 618                         power-domains = <&pd_adma>;
 619                 };
 620
 621                 lpd_dma_chan4: dma@ffab0000 {
 622                         status = "disabled";
 623                         compatible = "xlnx,zynqmp-dma-1.0";
 624                         reg = <0x0 0xffab0000 0x0 0x1000>;
 625                         interrupt-parent = <&gic>;
 626                         interrupts = <0 80 4>;
 627                         clock-names = "clk_main", "clk_apb";
 628                         xlnx,bus-width = <64>;
 629                         #stream-id-cells = <1>;
 630                         /* iommus = <&smmu 0x86b>; */
 631                         power-domains = <&pd_adma>;
 632                 };
 633
 634                 lpd_dma_chan5: dma@ffac0000 {
 635                         status = "disabled";
 636                         compatible = "xlnx,zynqmp-dma-1.0";
 637                         reg = <0x0 0xffac0000 0x0 0x1000>;
 638                         interrupt-parent = <&gic>;
 639                         interrupts = <0 81 4>;
 640                         clock-names = "clk_main", "clk_apb";
 641                         xlnx,bus-width = <64>;
 642                         #stream-id-cells = <1>;
 643                         /* iommus = <&smmu 0x86c>; */
 644                         power-domains = <&pd_adma>;
 645                 };
 646
 647                 lpd_dma_chan6: dma@ffad0000 {
 648                         status = "disabled";
 649                         compatible = "xlnx,zynqmp-dma-1.0";
 650                         reg = <0x0 0xffad0000 0x0 0x1000>;
 651                         interrupt-parent = <&gic>;
 652                         interrupts = <0 82 4>;
 653                         clock-names = "clk_main", "clk_apb";
 654                         xlnx,bus-width = <64>;
 655                         #stream-id-cells = <1>;
 656                         /* iommus = <&smmu 0x86d>; */
 657                         power-domains = <&pd_adma>;
 658                 };
 659
 660                 lpd_dma_chan7: dma@ffae0000 {
 661                         status = "disabled";
 662                         compatible = "xlnx,zynqmp-dma-1.0";
 663                         reg = <0x0 0xffae0000 0x0 0x1000>;
 664                         interrupt-parent = <&gic>;
 665                         interrupts = <0 83 4>;
 666                         clock-names = "clk_main", "clk_apb";
 667                         xlnx,bus-width = <64>;
 668                         #stream-id-cells = <1>;
 669                         /* iommus = <&smmu 0x86e>; */
 670                         power-domains = <&pd_adma>;
 671                 };
 672
 673                 lpd_dma_chan8: dma@ffaf0000 {
 674                         status = "disabled";
 675                         compatible = "xlnx,zynqmp-dma-1.0";
 676                         reg = <0x0 0xffaf0000 0x0 0x1000>;
 677                         interrupt-parent = <&gic>;
 678                         interrupts = <0 84 4>;
 679                         clock-names = "clk_main", "clk_apb";
 680                         xlnx,bus-width = <64>;
 681                         #stream-id-cells = <1>;
 682                         /* iommus = <&smmu 0x86f>; */
 683                         power-domains = <&pd_adma>;
 684                 };
 685
 686                 mc: memory-controller@fd070000 {
 687                         compatible = "xlnx,zynqmp-ddrc-2.40a";
 688                         reg = <0x0 0xfd070000 0x0 0x30000>;
 689                         interrupt-parent = <&gic>;
 690                         interrupts = <0 112 4>;
 691                 };
 692
 693                 nand0: nand@ff100000 {
 694                         compatible = "arasan,nfc-v3p10";
 695                         status = "disabled";
 696                         reg = <0x0 0xff100000 0x0 0x1000>;
 697                         clock-names = "clk_sys", "clk_flash";
 698                         interrupt-parent = <&gic>;
 699                         interrupts = <0 14 4>;
 700                         #address-cells = <1>;
 701                         #size-cells = <0>;
 702                         #stream-id-cells = <1>;
 703                         iommus = <&smmu 0x872>;
 704                         power-domains = <&pd_nand>;
 705                 };
 706
 707                 gem0: ethernet@ff0b0000 {
 708                         compatible = "cdns,zynqmp-gem";
 709                         status = "disabled";
 710                         interrupt-parent = <&gic>;
 711                         interrupts = <0 57 4>, <0 57 4>;
 712                         reg = <0x0 0xff0b0000 0x0 0x1000>;
 713                         clock-names = "pclk", "hclk", "tx_clk";
 714                         #address-cells = <1>;
 715                         #size-cells = <0>;
 716                         #stream-id-cells = <1>;
 717                         iommus = <&smmu 0x874>;
 718                         power-domains = <&pd_eth0>;
 719                 };
 720
 721                 gem1: ethernet@ff0c0000 {
 722                         compatible = "cdns,zynqmp-gem";
 723                         status = "disabled";
 724                         interrupt-parent = <&gic>;
 725                         interrupts = <0 59 4>, <0 59 4>;
 726                         reg = <0x0 0xff0c0000 0x0 0x1000>;
 727                         clock-names = "pclk", "hclk", "tx_clk";
 728                         #address-cells = <1>;
 729                         #size-cells = <0>;
 730                         #stream-id-cells = <1>;
 731                         iommus = <&smmu 0x875>;
 732                         power-domains = <&pd_eth1>;
 733                 };
 734
 735                 gem2: ethernet@ff0d0000 {
 736                         compatible = "cdns,zynqmp-gem";
 737                         status = "disabled";
 738                         interrupt-parent = <&gic>;
 739                         interrupts = <0 61 4>, <0 61 4>;
 740                         reg = <0x0 0xff0d0000 0x0 0x1000>;
 741                         clock-names = "pclk", "hclk", "tx_clk";
 742                         #address-cells = <1>;
 743                         #size-cells = <0>;
 744                         #stream-id-cells = <1>;
 745                         iommus = <&smmu 0x876>;
 746                         power-domains = <&pd_eth2>;
 747                 };
 748
 749                 gem3: ethernet@ff0e0000 {
 750                         compatible = "cdns,zynqmp-gem";
 751                         status = "disabled";
 752                         interrupt-parent = <&gic>;
 753                         interrupts = <0 63 4>, <0 63 4>;
 754                         reg = <0x0 0xff0e0000 0x0 0x1000>;
 755                         clock-names = "pclk", "hclk", "tx_clk";
 756                         #address-cells = <1>;
 757                         #size-cells = <0>;
 758                         #stream-id-cells = <1>;
 759                         iommus = <&smmu 0x877>;
 760                         power-domains = <&pd_eth3>;
 761                 };
 762
 763                 gpio: gpio@ff0a0000 {
 764                         compatible = "xlnx,zynqmp-gpio-1.0";
 765                         status = "disabled";
 766                         #gpio-cells = <0x2>;
 767                         interrupt-parent = <&gic>;
 768                         interrupts = <0 16 4>;
 769                         interrupt-controller;
 770                         #interrupt-cells = <2>;
 771                         reg = <0x0 0xff0a0000 0x0 0x1000>;
 772                         gpio-controller;
 773                         power-domains = <&pd_gpio>;
 774                 };
 775
 776                 i2c0: i2c@ff020000 {
 777                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 778                         status = "disabled";
 779                         interrupt-parent = <&gic>;
 780                         interrupts = <0 17 4>;
 781                         reg = <0x0 0xff020000 0x0 0x1000>;
 782                         #address-cells = <1>;
 783                         #size-cells = <0>;
 784                         power-domains = <&pd_i2c0>;
 785                 };
 786
 787                 i2c1: i2c@ff030000 {
 788                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 789                         status = "disabled";
 790                         interrupt-parent = <&gic>;
 791                         interrupts = <0 18 4>;
 792                         reg = <0x0 0xff030000 0x0 0x1000>;
 793                         #address-cells = <1>;
 794                         #size-cells = <0>;
 795                         power-domains = <&pd_i2c1>;
 796                 };
 797
 798                 ocm: memory-controller@ff960000 {
 799                         compatible = "xlnx,zynqmp-ocmc-1.0";
 800                         reg = <0x0 0xff960000 0x0 0x1000>;
 801                         interrupt-parent = <&gic>;
 802                         interrupts = <0 10 4>;
 803                 };
 804
 805                 perf_monitor_ocm: perf-monitor@ffa00000 {
 806                         compatible = "xlnx,axi-perf-monitor";
 807                         reg = <0x0 0xffa00000 0x0 0x10000>;
 808                         interrupts = <0 25 4>;
 809                         interrupt-parent = <&gic>;
 810                         xlnx,enable-profile = <0>;
 811                         xlnx,enable-trace = <0>;
 812                         xlnx,num-monitor-slots = <4>;
 813                         xlnx,enable-event-count = <1>;
 814                         xlnx,enable-event-log = <1>;
 815                         xlnx,have-sampled-metric-cnt = <1>;
 816                         xlnx,num-of-counters = <8>;
 817                         xlnx,metric-count-width = <32>;
 818                         xlnx,metrics-sample-count-width = <32>;
 819                         xlnx,global-count-width = <32>;
 820                         xlnx,metric-count-scale = <1>;
 821                 };
 822
 823                 pcie: pcie@fd0e0000 {
 824                         compatible = "xlnx,nwl-pcie-2.11";
 825                         status = "disabled";
 826                         #address-cells = <3>;
 827                         #size-cells = <2>;
 828                         #interrupt-cells = <1>;
 829                         msi-controller;
 830                         device_type = "pci";
 831                         interrupt-parent = <&gic>;
 832                         interrupts = <0 118 4>,
 833                                      <0 117 4>,
 834                                      <0 116 4>,
 835                                      <0 115 4>, /* MSI_1 [63...32] */
 836                                      <0 114 4>; /* MSI_0 [31...0] */
 837                         interrupt-names = "misc", "dummy", "intx",
 838                                           "msi1", "msi0";
 839                         msi-parent = <&pcie>;
 840                         reg = <0x0 0xfd0e0000 0x0 0x1000>,
 841                               <0x0 0xfd480000 0x0 0x1000>,
 842                               <0x80 0x00000000 0x0 0x1000000>;
 843                         reg-names = "breg", "pcireg", "cfg";
 844                         ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
 845                                   0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 846                         bus-range = <0x00 0xff>;
 847                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 848                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 849                                         <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 850                                         <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 851                                         <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 852                         power-domains = <&pd_pcie>;
 853                         pcie_intc: legacy-interrupt-controller {
 854                                 interrupt-controller;
 855                                 #address-cells = <0>;
 856                                 #interrupt-cells = <1>;
 857                         };
 858                 };
 859
 860                 qspi: spi@ff0f0000 {
 861                         u-boot,dm-pre-reloc;
 862                         compatible = "xlnx,zynqmp-qspi-1.0";
 863                         status = "disabled";
 864                         clock-names = "ref_clk", "pclk";
 865                         interrupts = <0 15 4>;
 866                         interrupt-parent = <&gic>;
 867                         num-cs = <1>;
 868                         reg = <0x0 0xff0f0000 0x0 0x1000>,
 869                               <0x0 0xc0000000 0x0 0x8000000>;
 870                         #address-cells = <1>;
 871                         #size-cells = <0>;
 872                         #stream-id-cells = <1>;
 873                         iommus = <&smmu 0x873>;
 874                         power-domains = <&pd_qspi>;
 875                 };
 876
 877                 rtc: rtc@ffa60000 {
 878                         compatible = "xlnx,zynqmp-rtc";
 879                         status = "disabled";
 880                         reg = <0x0 0xffa60000 0x0 0x100>;
 881                         interrupt-parent = <&gic>;
 882                         interrupts = <0 26 4>, <0 27 4>;
 883                         interrupt-names = "alarm", "sec";
 884                         calibration = <0x8000>;
 885                 };
 886
 887                 serdes: zynqmp_phy@fd400000 {
 888                         compatible = "xlnx,zynqmp-psgtr";
 889                         status = "disabled";
 890                         reg = <0x0 0xfd400000 0x0 0x40000>,
 891                               <0x0 0xfd3d0000 0x0 0x1000>,
 892                               <0x0 0xff5e0000 0x0 0x1000>;
 893                         reg-names = "serdes", "siou", "lpd";
 894                         nvmem-cells = <&soc_revision>;
 895                         nvmem-cell-names = "soc_revision";
 896                         resets = <&rst 16>, <&rst 59>, <&rst 60>,
 897                                  <&rst 61>, <&rst 62>, <&rst 63>,
 898                                  <&rst 64>, <&rst 3>, <&rst 29>,
 899                                  <&rst 30>, <&rst 31>, <&rst 32>;
 900                         reset-names = "sata_rst", "usb0_crst", "usb1_crst",
 901                                       "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
 902                                       "usb1_apbrst", "dp_rst", "gem0_rst",
 903                                       "gem1_rst", "gem2_rst", "gem3_rst";
 904                         lane0: lane0 {
 905                                 #phy-cells = <4>;
 906                         };
 907                         lane1: lane1 {
 908                                 #phy-cells = <4>;
 909                         };
 910                         lane2: lane2 {
 911                                 #phy-cells = <4>;
 912                         };
 913                         lane3: lane3 {
 914                                 #phy-cells = <4>;
 915                         };
 916                 };
 917
 918                 sata: ahci@fd0c0000 {
 919                         compatible = "ceva,ahci-1v84";
 920                         status = "disabled";
 921                         reg = <0x0 0xfd0c0000 0x0 0x2000>;
 922                         interrupt-parent = <&gic>;
 923                         interrupts = <0 133 4>;
 924                         power-domains = <&pd_sata>;
 925                         #stream-id-cells = <4>;
 926                         iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
 927                                  <&smmu 0x4c2>, <&smmu 0x4c3>;
 928                         /* dma-coherent; */
 929                 };
 930
 931                 sdhci0: sdhci@ff160000 {
 932                         u-boot,dm-pre-reloc;
 933                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 934                         status = "disabled";
 935                         interrupt-parent = <&gic>;
 936                         interrupts = <0 48 4>;
 937                         reg = <0x0 0xff160000 0x0 0x1000>;
 938                         clock-names = "clk_xin", "clk_ahb";
 939                         xlnx,device_id = <0>;
 940                         #stream-id-cells = <1>;
 941                         iommus = <&smmu 0x870>;
 942                         power-domains = <&pd_sd0>;
 943                         nvmem-cells = <&soc_revision>;
 944                         nvmem-cell-names = "soc_revision";
 945                 };
 946
 947                 sdhci1: sdhci@ff170000 {
 948                         u-boot,dm-pre-reloc;
 949                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 950                         status = "disabled";
 951                         interrupt-parent = <&gic>;
 952                         interrupts = <0 49 4>;
 953                         reg = <0x0 0xff170000 0x0 0x1000>;
 954                         clock-names = "clk_xin", "clk_ahb";
 955                         xlnx,device_id = <1>;
 956                         #stream-id-cells = <1>;
 957                         iommus = <&smmu 0x871>;
 958                         power-domains = <&pd_sd1>;
 959                         nvmem-cells = <&soc_revision>;
 960                         nvmem-cell-names = "soc_revision";
 961                 };
 962
 963                 smmu: smmu@fd800000 {
 964                         compatible = "arm,mmu-500";
 965                         reg = <0x0 0xfd800000 0x0 0x20000>;
 966                         #iommu-cells = <1>;
 967                         status = "disabled";
 968                         #global-interrupts = <1>;
 969                         interrupt-parent = <&gic>;
 970                         interrupts = <0 155 4>,
 971                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 972                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 973                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 974                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 975                 };
 976
 977                 spi0: spi@ff040000 {
 978                         compatible = "cdns,spi-r1p6";
 979                         status = "disabled";
 980                         interrupt-parent = <&gic>;
 981                         interrupts = <0 19 4>;
 982                         reg = <0x0 0xff040000 0x0 0x1000>;
 983                         clock-names = "ref_clk", "pclk";
 984                         #address-cells = <1>;
 985                         #size-cells = <0>;
 986                         power-domains = <&pd_spi0>;
 987                 };
 988
 989                 spi1: spi@ff050000 {
 990                         compatible = "cdns,spi-r1p6";
 991                         status = "disabled";
 992                         interrupt-parent = <&gic>;
 993                         interrupts = <0 20 4>;
 994                         reg = <0x0 0xff050000 0x0 0x1000>;
 995                         clock-names = "ref_clk", "pclk";
 996                         #address-cells = <1>;
 997                         #size-cells = <0>;
 998                         power-domains = <&pd_spi1>;
 999                 };
1000
1001                 ttc0: timer@ff110000 {
1002                         compatible = "cdns,ttc";
1003                         status = "disabled";
1004                         interrupt-parent = <&gic>;
1005                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
1006                         reg = <0x0 0xff110000 0x0 0x1000>;
1007                         timer-width = <32>;
1008                         power-domains = <&pd_ttc0>;
1009                 };
1010
1011                 ttc1: timer@ff120000 {
1012                         compatible = "cdns,ttc";
1013                         status = "disabled";
1014                         interrupt-parent = <&gic>;
1015                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
1016                         reg = <0x0 0xff120000 0x0 0x1000>;
1017                         timer-width = <32>;
1018                         power-domains = <&pd_ttc1>;
1019                 };
1020
1021                 ttc2: timer@ff130000 {
1022                         compatible = "cdns,ttc";
1023                         status = "disabled";
1024                         interrupt-parent = <&gic>;
1025                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
1026                         reg = <0x0 0xff130000 0x0 0x1000>;
1027                         timer-width = <32>;
1028                         power-domains = <&pd_ttc2>;
1029                 };
1030
1031                 ttc3: timer@ff140000 {
1032                         compatible = "cdns,ttc";
1033                         status = "disabled";
1034                         interrupt-parent = <&gic>;
1035                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
1036                         reg = <0x0 0xff140000 0x0 0x1000>;
1037                         timer-width = <32>;
1038                         power-domains = <&pd_ttc3>;
1039                 };
1040
1041                 uart0: serial@ff000000 {
1042                         u-boot,dm-pre-reloc;
1043                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
1044                         status = "disabled";
1045                         interrupt-parent = <&gic>;
1046                         interrupts = <0 21 4>;
1047                         reg = <0x0 0xff000000 0x0 0x1000>;
1048                         clock-names = "uart_clk", "pclk";
1049                         power-domains = <&pd_uart0>;
1050                 };
1051
1052                 uart1: serial@ff010000 {
1053                         u-boot,dm-pre-reloc;
1054                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
1055                         status = "disabled";
1056                         interrupt-parent = <&gic>;
1057                         interrupts = <0 22 4>;
1058                         reg = <0x0 0xff010000 0x0 0x1000>;
1059                         clock-names = "uart_clk", "pclk";
1060                         power-domains = <&pd_uart1>;
1061                 };
1062
1063                 usb0: usb0@ff9d0000 {
1064                         #address-cells = <2>;
1065                         #size-cells = <2>;
1066                         status = "disabled";
1067                         compatible = "xlnx,zynqmp-dwc3";
1068                         reg = <0x0 0xff9d0000 0x0 0x100>;
1069                         clock-names = "bus_clk", "ref_clk";
1070                         power-domains = <&pd_usb0>;
1071                         ranges;
1072                         nvmem-cells = <&soc_revision>;
1073                         nvmem-cell-names = "soc_revision";
1074
1075                         dwc3_0: dwc3@fe200000 {
1076                                 compatible = "snps,dwc3";
1077                                 status = "disabled";
1078                                 reg = <0x0 0xfe200000 0x0 0x40000>;
1079                                 interrupt-parent = <&gic>;
1080                                 interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
1081                                 #stream-id-cells = <1>;
1082                                 iommus = <&smmu 0x860>;
1083                                 snps,quirk-frame-length-adjustment = <0x20>;
1084                                 snps,refclk_fladj;
1085                                 snps,enable_guctl1_resume_quirk;
1086                                 snps,enable_guctl1_ipd_quirk;
1087                                 snps,xhci-stream-quirk;
1088                                 /* dma-coherent; */
1089                                 /* snps,enable-hibernation; */
1090                         };
1091                 };
1092
1093                 usb1: usb1@ff9e0000 {
1094                         #address-cells = <2>;
1095                         #size-cells = <2>;
1096                         status = "disabled";
1097                         compatible = "xlnx,zynqmp-dwc3";
1098                         reg = <0x0 0xff9e0000 0x0 0x100>;
1099                         clock-names = "bus_clk", "ref_clk";
1100                         power-domains = <&pd_usb1>;
1101                         ranges;
1102                         nvmem-cells = <&soc_revision>;
1103                         nvmem-cell-names = "soc_revision";
1104
1105                         dwc3_1: dwc3@fe300000 {
1106                                 compatible = "snps,dwc3";
1107                                 status = "disabled";
1108                                 reg = <0x0 0xfe300000 0x0 0x40000>;
1109                                 interrupt-parent = <&gic>;
1110                                 interrupts = <0 70 4>, <0 74 4>, <0 76 4>;
1111                                 #stream-id-cells = <1>;
1112                                 iommus = <&smmu 0x861>;
1113                                 snps,quirk-frame-length-adjustment = <0x20>;
1114                                 snps,refclk_fladj;
1115                                 snps,enable_guctl1_resume_quirk;
1116                                 snps,enable_guctl1_ipd_quirk;
1117                                 snps,xhci-stream-quirk;
1118                                 /* dma-coherent; */
1119                         };
1120                 };
1121
1122                 watchdog0: watchdog@fd4d0000 {
1123                         compatible = "cdns,wdt-r1p2";
1124                         status = "disabled";
1125                         interrupt-parent = <&gic>;
1126                         interrupts = <0 113 1>;
1127                         reg = <0x0 0xfd4d0000 0x0 0x1000>;
1128                         timeout-sec = <10>;
1129                 };
1130
1131                 xilinx_ams: ams@ffa50000 {
1132                         compatible = "xlnx,zynqmp-ams";
1133                         status = "disabled";
1134                         interrupt-parent = <&gic>;
1135                         interrupts = <0 56 4>;
1136                         interrupt-names = "ams-irq";
1137                         reg = <0x0 0xffa50000 0x0 0x800>;
1138                         reg-names = "ams-base";
1139                         #address-cells = <2>;
1140                         #size-cells = <2>;
1141                         #io-channel-cells = <1>;
1142                         ranges;
1143
1144                         ams_ps: ams_ps@ffa50800 {
1145                                 compatible = "xlnx,zynqmp-ams-ps";
1146                                 status = "disabled";
1147                                 reg = <0x0 0xffa50800 0x0 0x400>;
1148                         };
1149
1150                         ams_pl: ams_pl@ffa50c00 {
1151                                 compatible = "xlnx,zynqmp-ams-pl";
1152                                 status = "disabled";
1153                                 reg = <0x0 0xffa50c00 0x0 0x400>;
1154                         };
1155                 };
1156
1157                 xlnx_dp: dp@fd4a0000 {
1158                         compatible = "xlnx,v-dp";
1159                         status = "disabled";
1160                         reg = <0x0 0xfd4a0000 0x0 0x1000>;
1161                         interrupts = <0 119 4>;
1162                         interrupt-parent = <&gic>;
1163                         clock-names = "aclk", "aud_clk";
1164                         power-domains = <&pd_dp>;
1165                         xlnx,dp-version = "v1.2";
1166                         xlnx,max-lanes = <2>;
1167                         xlnx,max-link-rate = <540000>;
1168                         xlnx,max-bpc = <16>;
1169                         xlnx,enable-ycrcb;
1170                         xlnx,colormetry = "rgb";
1171                         xlnx,bpc = <8>;
1172                         xlnx,audio-chan = <2>;
1173                         xlnx,dp-sub = <&xlnx_dp_sub>;
1174                         xlnx,max-pclock-frequency = <300000>;
1175                 };
1176
1177                 xlnx_dp_sub: dp_sub@fd4aa000 {
1178                         compatible = "xlnx,dp-sub";
1179                         status = "disabled";
1180                         reg = <0x0 0xfd4aa000 0x0 0x1000>,
1181                               <0x0 0xfd4ab000 0x0 0x1000>,
1182                               <0x0 0xfd4ac000 0x0 0x1000>;
1183                         reg-names = "blend", "av_buf", "aud";
1184                         xlnx,output-fmt = "rgb";
1185                         xlnx,vid-fmt = "yuyv";
1186                         xlnx,gfx-fmt = "rgb565";
1187                         power-domains = <&pd_dp>;
1188                 };
1189
1190                 xlnx_dpdma: dma@fd4c0000 {
1191                         compatible = "xlnx,dpdma";
1192                         status = "disabled";
1193                         reg = <0x0 0xfd4c0000 0x0 0x1000>;
1194                         interrupts = <0 122 4>;
1195                         interrupt-parent = <&gic>;
1196                         clock-names = "axi_clk";
1197                         power-domains = <&pd_dp>;
1198                         dma-channels = <6>;
1199                         #dma-cells = <1>;
1200                         dma-video0channel {
1201                                 compatible = "xlnx,video0";
1202                         };
1203                         dma-video1channel {
1204                                 compatible = "xlnx,video1";
1205                         };
1206                         dma-video2channel {
1207                                 compatible = "xlnx,video2";
1208                         };
1209                         dma-graphicschannel {
1210                                 compatible = "xlnx,graphics";
1211                         };
1212                         dma-audio0channel {
1213                                 compatible = "xlnx,audio0";
1214                         };
1215                         dma-audio1channel {
1216                                 compatible = "xlnx,audio1";
1217                         };
1218                 };
1219         };
1220 };