2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/macb.h>
28 #include <linux/platform_device.h>
29 #include <linux/phy.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_mdio.h>
34 #include <linux/of_net.h>
36 #include <linux/udp.h>
37 #include <linux/tcp.h>
40 #define MACB_RX_BUFFER_SIZE 128
41 #define RX_BUFFER_MULTIPLE 64 /* bytes */
43 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
44 #define MIN_RX_RING_SIZE 64
45 #define MAX_RX_RING_SIZE 8192
46 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
49 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
50 #define MIN_TX_RING_SIZE 64
51 #define MAX_TX_RING_SIZE 4096
52 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
55 /* level of occupied TX descriptors under which we wake up TX process */
56 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
58 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
60 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
63 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
65 /* Max length of transmit frame must be a multiple of 8 bytes */
66 #define MACB_TX_LEN_ALIGN 8
67 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
68 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
70 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
71 #define MACB_NETIF_LSO NETIF_F_TSO
73 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
74 #define MACB_WOL_ENABLED (0x1 << 1)
76 /* Graceful stop timeouts in us. We should allow up to
77 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
79 #define MACB_HALT_TIMEOUT 1230
81 /* DMA buffer descriptor might be different size
82 * depends on hardware configuration:
84 * 1. dma address width 32 bits:
85 * word 1: 32 bit address of Data Buffer
88 * 2. dma address width 64 bits:
89 * word 1: 32 bit address of Data Buffer
91 * word 3: upper 32 bit address of Data Buffer
94 * 3. dma address width 32 bits with hardware timestamping:
95 * word 1: 32 bit address of Data Buffer
97 * word 3: timestamp word 1
98 * word 4: timestamp word 2
100 * 4. dma address width 64 bits with hardware timestamping:
101 * word 1: 32 bit address of Data Buffer
103 * word 3: upper 32 bit address of Data Buffer
105 * word 5: timestamp word 1
106 * word 6: timestamp word 2
108 static unsigned int macb_dma_desc_get_size(struct macb *bp)
111 unsigned int desc_size;
113 switch (bp->hw_dma_cap) {
115 desc_size = sizeof(struct macb_dma_desc)
116 + sizeof(struct macb_dma_desc_64);
119 desc_size = sizeof(struct macb_dma_desc)
120 + sizeof(struct macb_dma_desc_ptp);
122 case HW_DMA_CAP_64B_PTP:
123 desc_size = sizeof(struct macb_dma_desc)
124 + sizeof(struct macb_dma_desc_64)
125 + sizeof(struct macb_dma_desc_ptp);
128 desc_size = sizeof(struct macb_dma_desc);
132 return sizeof(struct macb_dma_desc);
135 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
138 switch (bp->hw_dma_cap) {
143 case HW_DMA_CAP_64B_PTP:
153 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
154 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
156 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
157 return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct macb_dma_desc));
162 /* Ring buffer accessors */
163 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
165 return index & (bp->tx_ring_size - 1);
168 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
171 index = macb_tx_ring_wrap(queue->bp, index);
172 index = macb_adj_dma_desc_idx(queue->bp, index);
173 return &queue->tx_ring[index];
176 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
179 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
182 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
186 offset = macb_tx_ring_wrap(queue->bp, index) *
187 macb_dma_desc_get_size(queue->bp);
189 return queue->tx_ring_dma + offset;
192 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
194 return index & (bp->rx_ring_size - 1);
197 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
199 index = macb_rx_ring_wrap(bp, index);
200 index = macb_adj_dma_desc_idx(bp, index);
201 return &bp->rx_ring[index];
204 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
206 return bp->rx_buffers + bp->rx_buffer_size *
207 macb_rx_ring_wrap(bp, index);
211 static u32 hw_readl_native(struct macb *bp, int offset)
213 return __raw_readl(bp->regs + offset);
216 static void hw_writel_native(struct macb *bp, int offset, u32 value)
218 __raw_writel(value, bp->regs + offset);
221 static u32 hw_readl(struct macb *bp, int offset)
223 return readl_relaxed(bp->regs + offset);
226 static void hw_writel(struct macb *bp, int offset, u32 value)
228 writel_relaxed(value, bp->regs + offset);
231 /* Find the CPU endianness by using the loopback bit of NCR register. When the
232 * CPU is in big endian we need to program swapped mode for management
235 static bool hw_is_native_io(void __iomem *addr)
237 u32 value = MACB_BIT(LLB);
239 __raw_writel(value, addr + MACB_NCR);
240 value = __raw_readl(addr + MACB_NCR);
242 /* Write 0 back to disable everything */
243 __raw_writel(0, addr + MACB_NCR);
245 return value == MACB_BIT(LLB);
248 static bool hw_is_gem(void __iomem *addr, bool native_io)
253 id = __raw_readl(addr + MACB_MID);
255 id = readl_relaxed(addr + MACB_MID);
257 return MACB_BFEXT(IDNUM, id) >= 0x2;
260 static void macb_set_hwaddr(struct macb *bp)
265 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
266 macb_or_gem_writel(bp, SA1B, bottom);
267 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
268 macb_or_gem_writel(bp, SA1T, top);
270 /* Clear unused address register sets */
271 macb_or_gem_writel(bp, SA2B, 0);
272 macb_or_gem_writel(bp, SA2T, 0);
273 macb_or_gem_writel(bp, SA3B, 0);
274 macb_or_gem_writel(bp, SA3T, 0);
275 macb_or_gem_writel(bp, SA4B, 0);
276 macb_or_gem_writel(bp, SA4T, 0);
279 static void macb_get_hwaddr(struct macb *bp)
281 struct macb_platform_data *pdata;
287 pdata = dev_get_platdata(&bp->pdev->dev);
289 /* Check all 4 address register for valid address */
290 for (i = 0; i < 4; i++) {
291 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
292 top = macb_or_gem_readl(bp, SA1T + i * 8);
294 if (pdata && pdata->rev_eth_addr) {
295 addr[5] = bottom & 0xff;
296 addr[4] = (bottom >> 8) & 0xff;
297 addr[3] = (bottom >> 16) & 0xff;
298 addr[2] = (bottom >> 24) & 0xff;
299 addr[1] = top & 0xff;
300 addr[0] = (top & 0xff00) >> 8;
302 addr[0] = bottom & 0xff;
303 addr[1] = (bottom >> 8) & 0xff;
304 addr[2] = (bottom >> 16) & 0xff;
305 addr[3] = (bottom >> 24) & 0xff;
306 addr[4] = top & 0xff;
307 addr[5] = (top >> 8) & 0xff;
310 if (is_valid_ether_addr(addr)) {
311 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
316 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
317 eth_hw_addr_random(bp->dev);
320 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
322 struct macb *bp = bus->priv;
325 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
326 | MACB_BF(RW, MACB_MAN_READ)
327 | MACB_BF(PHYA, mii_id)
328 | MACB_BF(REGA, regnum)
329 | MACB_BF(CODE, MACB_MAN_CODE)));
331 /* wait for end of transfer */
332 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
335 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
340 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
343 struct macb *bp = bus->priv;
345 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
346 | MACB_BF(RW, MACB_MAN_WRITE)
347 | MACB_BF(PHYA, mii_id)
348 | MACB_BF(REGA, regnum)
349 | MACB_BF(CODE, MACB_MAN_CODE)
350 | MACB_BF(DATA, value)));
352 /* wait for end of transfer */
353 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
360 * macb_set_tx_clk() - Set a clock to a new frequency
361 * @clk Pointer to the clock to change
362 * @rate New frequency in Hz
363 * @dev Pointer to the struct net_device
365 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
367 long ferr, rate, rate_rounded;
386 rate_rounded = clk_round_rate(clk, rate);
387 if (rate_rounded < 0)
390 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
393 ferr = abs(rate_rounded - rate);
394 ferr = DIV_ROUND_UP(ferr, rate / 100000);
396 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
399 if (clk_set_rate(clk, rate_rounded))
400 netdev_err(dev, "adjusting tx_clk failed.\n");
403 static void macb_handle_link_change(struct net_device *dev)
405 struct macb *bp = netdev_priv(dev);
406 struct phy_device *phydev = bp->phy_dev;
408 int status_change = 0;
410 spin_lock_irqsave(&bp->lock, flags);
413 if ((bp->speed != phydev->speed) ||
414 (bp->duplex != phydev->duplex)) {
417 reg = macb_readl(bp, NCFGR);
418 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
420 reg &= ~GEM_BIT(GBE);
424 if (phydev->speed == SPEED_100)
425 reg |= MACB_BIT(SPD);
426 if (phydev->speed == SPEED_1000 &&
427 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
430 macb_or_gem_writel(bp, NCFGR, reg);
432 bp->speed = phydev->speed;
433 bp->duplex = phydev->duplex;
438 if (phydev->link != bp->link) {
443 bp->link = phydev->link;
448 spin_unlock_irqrestore(&bp->lock, flags);
452 /* Update the TX clock rate if and only if the link is
453 * up and there has been a link change.
455 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
457 netif_carrier_on(dev);
458 netdev_info(dev, "link up (%d/%s)\n",
460 phydev->duplex == DUPLEX_FULL ?
463 netif_carrier_off(dev);
464 netdev_info(dev, "link down\n");
469 /* based on au1000_eth. c*/
470 static int macb_mii_probe(struct net_device *dev)
472 struct macb *bp = netdev_priv(dev);
473 struct macb_platform_data *pdata;
474 struct phy_device *phydev;
479 phydev = of_phy_connect(dev, bp->phy_node,
480 &macb_handle_link_change, 0,
485 phydev = phy_find_first(bp->mii_bus);
487 netdev_err(dev, "no PHY found\n");
491 pdata = dev_get_platdata(&bp->pdev->dev);
492 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
493 ret = devm_gpio_request(&bp->pdev->dev,
494 pdata->phy_irq_pin, "phy int");
496 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
497 phydev->irq = (phy_irq < 0) ?
502 /* attach the mac to the phy */
503 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
506 netdev_err(dev, "Could not attach to PHY\n");
511 /* mask with MAC supported features */
512 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
513 phydev->supported &= PHY_GBIT_FEATURES;
515 phydev->supported &= PHY_BASIC_FEATURES;
517 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
518 phydev->supported &= ~SUPPORTED_1000baseT_Half;
520 phydev->advertising = phydev->supported;
525 bp->phy_dev = phydev;
530 static int macb_mii_init(struct macb *bp)
532 struct macb_platform_data *pdata;
533 struct device_node *np;
536 /* Enable management port */
537 macb_writel(bp, NCR, MACB_BIT(MPE));
539 bp->mii_bus = mdiobus_alloc();
545 bp->mii_bus->name = "MACB_mii_bus";
546 bp->mii_bus->read = &macb_mdio_read;
547 bp->mii_bus->write = &macb_mdio_write;
548 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
549 bp->pdev->name, bp->pdev->id);
550 bp->mii_bus->priv = bp;
551 bp->mii_bus->parent = &bp->pdev->dev;
552 pdata = dev_get_platdata(&bp->pdev->dev);
554 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
556 np = bp->pdev->dev.of_node;
558 if (of_phy_is_fixed_link(np)) {
559 if (of_phy_register_fixed_link(np) < 0) {
560 dev_err(&bp->pdev->dev,
561 "broken fixed-link specification\n");
562 goto err_out_unregister_bus;
564 bp->phy_node = of_node_get(np);
566 err = mdiobus_register(bp->mii_bus);
568 /* try dt phy registration */
569 err = of_mdiobus_register(bp->mii_bus, np);
571 /* fallback to standard phy registration if no phy were
572 * found during dt phy registration
574 if (!err && !phy_find_first(bp->mii_bus)) {
575 for (i = 0; i < PHY_MAX_ADDR; i++) {
576 struct phy_device *phydev;
578 phydev = mdiobus_scan(bp->mii_bus, i);
579 if (IS_ERR(phydev) &&
580 PTR_ERR(phydev) != -ENODEV) {
581 err = PTR_ERR(phydev);
587 goto err_out_unregister_bus;
591 for (i = 0; i < PHY_MAX_ADDR; i++)
592 bp->mii_bus->irq[i] = PHY_POLL;
595 bp->mii_bus->phy_mask = pdata->phy_mask;
597 err = mdiobus_register(bp->mii_bus);
601 goto err_out_free_mdiobus;
603 err = macb_mii_probe(bp->dev);
605 goto err_out_unregister_bus;
609 err_out_unregister_bus:
610 mdiobus_unregister(bp->mii_bus);
611 err_out_free_mdiobus:
612 mdiobus_free(bp->mii_bus);
617 static void macb_update_stats(struct macb *bp)
619 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
620 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
621 int offset = MACB_PFR;
623 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
625 for (; p < end; p++, offset += 4)
626 *p += bp->macb_reg_readl(bp, offset);
629 static int macb_halt_tx(struct macb *bp)
631 unsigned long halt_time, timeout;
634 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
636 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
639 status = macb_readl(bp, TSR);
640 if (!(status & MACB_BIT(TGO)))
643 usleep_range(10, 250);
644 } while (time_before(halt_time, timeout));
649 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
651 if (tx_skb->mapping) {
652 if (tx_skb->mapped_as_page)
653 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
654 tx_skb->size, DMA_TO_DEVICE);
656 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
657 tx_skb->size, DMA_TO_DEVICE);
662 dev_kfree_skb_any(tx_skb->skb);
667 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
669 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
670 struct macb_dma_desc_64 *desc_64;
672 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
673 desc_64 = macb_64b_desc(bp, desc);
674 desc_64->addrh = upper_32_bits(addr);
677 desc->addr = lower_32_bits(addr);
680 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
683 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
684 struct macb_dma_desc_64 *desc_64;
686 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
687 desc_64 = macb_64b_desc(bp, desc);
688 addr = ((u64)(desc_64->addrh) << 32);
691 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
695 static void macb_tx_error_task(struct work_struct *work)
697 struct macb_queue *queue = container_of(work, struct macb_queue,
699 struct macb *bp = queue->bp;
700 struct macb_tx_skb *tx_skb;
701 struct macb_dma_desc *desc;
706 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
707 (unsigned int)(queue - bp->queues),
708 queue->tx_tail, queue->tx_head);
710 /* Prevent the queue IRQ handlers from running: each of them may call
711 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
712 * As explained below, we have to halt the transmission before updating
713 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
714 * network engine about the macb/gem being halted.
716 spin_lock_irqsave(&bp->lock, flags);
718 /* Make sure nobody is trying to queue up new packets */
719 netif_tx_stop_all_queues(bp->dev);
721 /* Stop transmission now
722 * (in case we have just queued new packets)
723 * macb/gem must be halted to write TBQP register
725 if (macb_halt_tx(bp))
726 /* Just complain for now, reinitializing TX path can be good */
727 netdev_err(bp->dev, "BUG: halt tx timed out\n");
729 /* Treat frames in TX queue including the ones that caused the error.
730 * Free transmit buffers in upper layer.
732 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
735 desc = macb_tx_desc(queue, tail);
737 tx_skb = macb_tx_skb(queue, tail);
740 if (ctrl & MACB_BIT(TX_USED)) {
741 /* skb is set for the last buffer of the frame */
743 macb_tx_unmap(bp, tx_skb);
745 tx_skb = macb_tx_skb(queue, tail);
749 /* ctrl still refers to the first buffer descriptor
750 * since it's the only one written back by the hardware
752 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
753 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
754 macb_tx_ring_wrap(bp, tail),
756 bp->dev->stats.tx_packets++;
757 bp->dev->stats.tx_bytes += skb->len;
760 /* "Buffers exhausted mid-frame" errors may only happen
761 * if the driver is buggy, so complain loudly about
762 * those. Statistics are updated by hardware.
764 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
766 "BUG: TX buffers exhausted mid-frame\n");
768 desc->ctrl = ctrl | MACB_BIT(TX_USED);
771 macb_tx_unmap(bp, tx_skb);
774 /* Set end of TX queue */
775 desc = macb_tx_desc(queue, 0);
776 macb_set_addr(bp, desc, 0);
777 desc->ctrl = MACB_BIT(TX_USED);
779 /* Make descriptor updates visible to hardware */
782 /* Reinitialize the TX desc queue */
783 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
784 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
785 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
786 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
788 /* Make TX ring reflect state of hardware */
792 /* Housework before enabling TX IRQ */
793 macb_writel(bp, TSR, macb_readl(bp, TSR));
794 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
796 /* Now we are ready to start transmission again */
797 netif_tx_start_all_queues(bp->dev);
798 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
800 spin_unlock_irqrestore(&bp->lock, flags);
803 static void macb_tx_interrupt(struct macb_queue *queue)
808 struct macb *bp = queue->bp;
809 u16 queue_index = queue - bp->queues;
811 status = macb_readl(bp, TSR);
812 macb_writel(bp, TSR, status);
814 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
815 queue_writel(queue, ISR, MACB_BIT(TCOMP));
817 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
818 (unsigned long)status);
820 head = queue->tx_head;
821 for (tail = queue->tx_tail; tail != head; tail++) {
822 struct macb_tx_skb *tx_skb;
824 struct macb_dma_desc *desc;
827 desc = macb_tx_desc(queue, tail);
829 /* Make hw descriptor updates visible to CPU */
834 /* TX_USED bit is only set by hardware on the very first buffer
835 * descriptor of the transmitted frame.
837 if (!(ctrl & MACB_BIT(TX_USED)))
840 /* Process all buffers of the current transmitted frame */
842 tx_skb = macb_tx_skb(queue, tail);
845 /* First, update TX stats if needed */
847 if (gem_ptp_do_txstamp(queue, skb, desc) == 0) {
848 /* skb now belongs to timestamp buffer
849 * and will be removed later
853 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
854 macb_tx_ring_wrap(bp, tail),
856 bp->dev->stats.tx_packets++;
857 bp->dev->stats.tx_bytes += skb->len;
860 /* Now we can safely release resources */
861 macb_tx_unmap(bp, tx_skb);
863 /* skb is set only for the last buffer of the frame.
864 * WARNING: at this point skb has been freed by
872 queue->tx_tail = tail;
873 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
874 CIRC_CNT(queue->tx_head, queue->tx_tail,
875 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
876 netif_wake_subqueue(bp->dev, queue_index);
879 static void gem_rx_refill(struct macb *bp)
884 struct macb_dma_desc *desc;
886 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail,
887 bp->rx_ring_size) > 0) {
888 entry = macb_rx_ring_wrap(bp, bp->rx_prepared_head);
890 /* Make hw descriptor updates visible to CPU */
893 bp->rx_prepared_head++;
894 desc = macb_rx_desc(bp, entry);
896 if (!bp->rx_skbuff[entry]) {
897 /* allocate sk_buff for this free entry in ring */
898 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
899 if (unlikely(!skb)) {
901 "Unable to allocate sk_buff\n");
905 /* now fill corresponding descriptor entry */
906 paddr = dma_map_single(&bp->pdev->dev, skb->data,
909 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
914 bp->rx_skbuff[entry] = skb;
916 if (entry == bp->rx_ring_size - 1)
917 paddr |= MACB_BIT(RX_WRAP);
918 macb_set_addr(bp, desc, paddr);
921 /* properly align Ethernet header */
922 skb_reserve(skb, NET_IP_ALIGN);
924 desc->addr &= ~MACB_BIT(RX_USED);
929 /* Make descriptor updates visible to hardware */
932 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
933 bp->rx_prepared_head, bp->rx_tail);
936 /* Mark DMA descriptors from begin up to and not including end as unused */
937 static void discard_partial_frame(struct macb *bp, unsigned int begin,
942 for (frag = begin; frag != end; frag++) {
943 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
945 desc->addr &= ~MACB_BIT(RX_USED);
948 /* Make descriptor updates visible to hardware */
951 /* When this happens, the hardware stats registers for
952 * whatever caused this is updated, so we don't have to record
957 static int gem_rx(struct macb *bp, int budget)
962 struct macb_dma_desc *desc;
965 while (count < budget) {
970 entry = macb_rx_ring_wrap(bp, bp->rx_tail);
971 desc = macb_rx_desc(bp, entry);
973 /* Make hw descriptor updates visible to CPU */
976 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
977 addr = macb_get_addr(bp, desc);
986 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
988 "not whole frame pointed by descriptor\n");
989 bp->dev->stats.rx_dropped++;
992 skb = bp->rx_skbuff[entry];
993 if (unlikely(!skb)) {
995 "inconsistent Rx descriptor chain\n");
996 bp->dev->stats.rx_dropped++;
999 /* now everything is ready for receiving packet */
1000 bp->rx_skbuff[entry] = NULL;
1001 len = ctrl & bp->rx_frm_len_mask;
1003 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1006 dma_unmap_single(&bp->pdev->dev, addr,
1007 bp->rx_buffer_size, DMA_FROM_DEVICE);
1009 skb->protocol = eth_type_trans(skb, bp->dev);
1010 skb_checksum_none_assert(skb);
1011 if (bp->dev->features & NETIF_F_RXCSUM &&
1012 !(bp->dev->flags & IFF_PROMISC) &&
1013 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1014 skb->ip_summed = CHECKSUM_UNNECESSARY;
1016 bp->dev->stats.rx_packets++;
1017 bp->dev->stats.rx_bytes += skb->len;
1019 gem_ptp_do_rxstamp(bp, skb, desc);
1021 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1022 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1023 skb->len, skb->csum);
1024 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1025 skb_mac_header(skb), 16, true);
1026 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1027 skb->data, 32, true);
1030 netif_receive_skb(skb);
1038 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
1039 unsigned int last_frag)
1043 unsigned int offset;
1044 struct sk_buff *skb;
1045 struct macb_dma_desc *desc;
1047 desc = macb_rx_desc(bp, last_frag);
1048 len = desc->ctrl & bp->rx_frm_len_mask;
1050 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1051 macb_rx_ring_wrap(bp, first_frag),
1052 macb_rx_ring_wrap(bp, last_frag), len);
1054 /* The ethernet header starts NET_IP_ALIGN bytes into the
1055 * first buffer. Since the header is 14 bytes, this makes the
1056 * payload word-aligned.
1058 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1059 * the two padding bytes into the skb so that we avoid hitting
1060 * the slowpath in memcpy(), and pull them off afterwards.
1062 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1064 bp->dev->stats.rx_dropped++;
1065 for (frag = first_frag; ; frag++) {
1066 desc = macb_rx_desc(bp, frag);
1067 desc->addr &= ~MACB_BIT(RX_USED);
1068 if (frag == last_frag)
1072 /* Make descriptor updates visible to hardware */
1079 len += NET_IP_ALIGN;
1080 skb_checksum_none_assert(skb);
1083 for (frag = first_frag; ; frag++) {
1084 unsigned int frag_len = bp->rx_buffer_size;
1086 if (offset + frag_len > len) {
1087 if (unlikely(frag != last_frag)) {
1088 dev_kfree_skb_any(skb);
1091 frag_len = len - offset;
1093 skb_copy_to_linear_data_offset(skb, offset,
1094 macb_rx_buffer(bp, frag),
1096 offset += bp->rx_buffer_size;
1097 desc = macb_rx_desc(bp, frag);
1098 desc->addr &= ~MACB_BIT(RX_USED);
1100 if (frag == last_frag)
1104 /* Make descriptor updates visible to hardware */
1107 __skb_pull(skb, NET_IP_ALIGN);
1108 skb->protocol = eth_type_trans(skb, bp->dev);
1110 bp->dev->stats.rx_packets++;
1111 bp->dev->stats.rx_bytes += skb->len;
1112 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1113 skb->len, skb->csum);
1114 netif_receive_skb(skb);
1119 static inline void macb_init_rx_ring(struct macb *bp)
1122 struct macb_dma_desc *desc = NULL;
1125 addr = bp->rx_buffers_dma;
1126 for (i = 0; i < bp->rx_ring_size; i++) {
1127 desc = macb_rx_desc(bp, i);
1128 macb_set_addr(bp, desc, addr);
1130 addr += bp->rx_buffer_size;
1132 desc->addr |= MACB_BIT(RX_WRAP);
1136 static int macb_rx(struct macb *bp, int budget)
1138 bool reset_rx_queue = false;
1141 int first_frag = -1;
1143 for (tail = bp->rx_tail; budget > 0; tail++) {
1144 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
1147 /* Make hw descriptor updates visible to CPU */
1152 if (!(desc->addr & MACB_BIT(RX_USED)))
1155 if (ctrl & MACB_BIT(RX_SOF)) {
1156 if (first_frag != -1)
1157 discard_partial_frame(bp, first_frag, tail);
1161 if (ctrl & MACB_BIT(RX_EOF)) {
1164 if (unlikely(first_frag == -1)) {
1165 reset_rx_queue = true;
1169 dropped = macb_rx_frame(bp, first_frag, tail);
1171 if (unlikely(dropped < 0)) {
1172 reset_rx_queue = true;
1182 if (unlikely(reset_rx_queue)) {
1183 unsigned long flags;
1186 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1188 spin_lock_irqsave(&bp->lock, flags);
1190 ctrl = macb_readl(bp, NCR);
1191 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1193 macb_init_rx_ring(bp);
1194 macb_writel(bp, RBQP, bp->rx_ring_dma);
1196 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1198 spin_unlock_irqrestore(&bp->lock, flags);
1202 if (first_frag != -1)
1203 bp->rx_tail = first_frag;
1210 static int macb_poll(struct napi_struct *napi, int budget)
1212 struct macb *bp = container_of(napi, struct macb, napi);
1216 status = macb_readl(bp, RSR);
1217 macb_writel(bp, RSR, status);
1221 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1222 (unsigned long)status, budget);
1224 work_done = bp->macbgem_ops.mog_rx(bp, budget);
1225 if (work_done < budget) {
1226 napi_complete_done(napi, work_done);
1228 /* Packets received while interrupts were disabled */
1229 status = macb_readl(bp, RSR);
1231 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1232 macb_writel(bp, ISR, MACB_BIT(RCOMP));
1233 napi_reschedule(napi);
1235 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
1239 /* TODO: Handle errors */
1244 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1246 struct macb_queue *queue = dev_id;
1247 struct macb *bp = queue->bp;
1248 struct net_device *dev = bp->dev;
1251 status = queue_readl(queue, ISR);
1253 if (unlikely(!status))
1256 spin_lock(&bp->lock);
1259 /* close possible race with dev_close */
1260 if (unlikely(!netif_running(dev))) {
1261 queue_writel(queue, IDR, -1);
1262 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1263 queue_writel(queue, ISR, -1);
1267 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1268 (unsigned int)(queue - bp->queues),
1269 (unsigned long)status);
1271 if (status & MACB_RX_INT_FLAGS) {
1272 /* There's no point taking any more interrupts
1273 * until we have processed the buffers. The
1274 * scheduling call may fail if the poll routine
1275 * is already scheduled, so disable interrupts
1278 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1279 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1280 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1282 if (napi_schedule_prep(&bp->napi)) {
1283 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1284 __napi_schedule(&bp->napi);
1288 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1289 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1290 schedule_work(&queue->tx_error_task);
1292 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1293 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1298 if (status & MACB_BIT(TCOMP))
1299 macb_tx_interrupt(queue);
1301 /* Link change detection isn't possible with RMII, so we'll
1302 * add that if/when we get our hands on a full-blown MII PHY.
1305 /* There is a hardware issue under heavy load where DMA can
1306 * stop, this causes endless "used buffer descriptor read"
1307 * interrupts but it can be cleared by re-enabling RX. See
1308 * the at91 manual, section 41.3.1 or the Zynq manual
1309 * section 16.7.4 for details.
1311 if (status & MACB_BIT(RXUBR)) {
1312 ctrl = macb_readl(bp, NCR);
1313 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1315 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1317 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1318 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1321 if (status & MACB_BIT(ISR_ROVR)) {
1322 /* We missed at least one packet */
1323 if (macb_is_gem(bp))
1324 bp->hw_stats.gem.rx_overruns++;
1326 bp->hw_stats.macb.rx_overruns++;
1328 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1329 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1332 if (status & MACB_BIT(HRESP)) {
1333 /* TODO: Reset the hardware, and maybe move the
1334 * netdev_err to a lower-priority context as well
1337 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1339 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1340 queue_writel(queue, ISR, MACB_BIT(HRESP));
1342 status = queue_readl(queue, ISR);
1345 spin_unlock(&bp->lock);
1350 #ifdef CONFIG_NET_POLL_CONTROLLER
1351 /* Polling receive - used by netconsole and other diagnostic tools
1352 * to allow network i/o with interrupts disabled.
1354 static void macb_poll_controller(struct net_device *dev)
1356 struct macb *bp = netdev_priv(dev);
1357 struct macb_queue *queue;
1358 unsigned long flags;
1361 local_irq_save(flags);
1362 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1363 macb_interrupt(dev->irq, queue);
1364 local_irq_restore(flags);
1368 static unsigned int macb_tx_map(struct macb *bp,
1369 struct macb_queue *queue,
1370 struct sk_buff *skb,
1371 unsigned int hdrlen)
1374 unsigned int len, entry, i, tx_head = queue->tx_head;
1375 struct macb_tx_skb *tx_skb = NULL;
1376 struct macb_dma_desc *desc;
1377 unsigned int offset, size, count = 0;
1378 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1379 unsigned int eof = 1, mss_mfs = 0;
1380 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1383 if (skb_shinfo(skb)->gso_size != 0) {
1384 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1386 lso_ctrl = MACB_LSO_UFO_ENABLE;
1389 lso_ctrl = MACB_LSO_TSO_ENABLE;
1392 /* First, map non-paged data */
1393 len = skb_headlen(skb);
1395 /* first buffer length */
1400 entry = macb_tx_ring_wrap(bp, tx_head);
1401 tx_skb = &queue->tx_skb[entry];
1403 mapping = dma_map_single(&bp->pdev->dev,
1405 size, DMA_TO_DEVICE);
1406 if (dma_mapping_error(&bp->pdev->dev, mapping))
1409 /* Save info to properly release resources */
1411 tx_skb->mapping = mapping;
1412 tx_skb->size = size;
1413 tx_skb->mapped_as_page = false;
1420 size = min(len, bp->max_tx_length);
1423 /* Then, map paged data from fragments */
1424 for (f = 0; f < nr_frags; f++) {
1425 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1427 len = skb_frag_size(frag);
1430 size = min(len, bp->max_tx_length);
1431 entry = macb_tx_ring_wrap(bp, tx_head);
1432 tx_skb = &queue->tx_skb[entry];
1434 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1435 offset, size, DMA_TO_DEVICE);
1436 if (dma_mapping_error(&bp->pdev->dev, mapping))
1439 /* Save info to properly release resources */
1441 tx_skb->mapping = mapping;
1442 tx_skb->size = size;
1443 tx_skb->mapped_as_page = true;
1452 /* Should never happen */
1453 if (unlikely(!tx_skb)) {
1454 netdev_err(bp->dev, "BUG! empty skb!\n");
1458 /* This is the last buffer of the frame: save socket buffer */
1461 /* Update TX ring: update buffer descriptors in reverse order
1462 * to avoid race condition
1465 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1466 * to set the end of TX queue
1469 entry = macb_tx_ring_wrap(bp, i);
1470 ctrl = MACB_BIT(TX_USED);
1471 desc = macb_tx_desc(queue, entry);
1475 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1476 /* include header and FCS in value given to h/w */
1477 mss_mfs = skb_shinfo(skb)->gso_size +
1478 skb_transport_offset(skb) +
1481 mss_mfs = skb_shinfo(skb)->gso_size;
1482 /* TCP Sequence Number Source Select
1483 * can be set only for TSO
1491 entry = macb_tx_ring_wrap(bp, i);
1492 tx_skb = &queue->tx_skb[entry];
1493 desc = macb_tx_desc(queue, entry);
1495 ctrl = (u32)tx_skb->size;
1497 ctrl |= MACB_BIT(TX_LAST);
1500 if (unlikely(entry == (bp->tx_ring_size - 1)))
1501 ctrl |= MACB_BIT(TX_WRAP);
1503 /* First descriptor is header descriptor */
1504 if (i == queue->tx_head) {
1505 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1506 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1508 /* Only set MSS/MFS on payload descriptors
1509 * (second or later descriptor)
1511 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1513 /* Set TX buffer descriptor */
1514 macb_set_addr(bp, desc, tx_skb->mapping);
1515 /* desc->addr must be visible to hardware before clearing
1516 * 'TX_USED' bit in desc->ctrl.
1520 } while (i != queue->tx_head);
1522 queue->tx_head = tx_head;
1527 netdev_err(bp->dev, "TX DMA map failed\n");
1529 for (i = queue->tx_head; i != tx_head; i++) {
1530 tx_skb = macb_tx_skb(queue, i);
1532 macb_tx_unmap(bp, tx_skb);
1538 static netdev_features_t macb_features_check(struct sk_buff *skb,
1539 struct net_device *dev,
1540 netdev_features_t features)
1542 unsigned int nr_frags, f;
1543 unsigned int hdrlen;
1545 /* Validate LSO compatibility */
1547 /* there is only one buffer */
1548 if (!skb_is_nonlinear(skb))
1551 /* length of header */
1552 hdrlen = skb_transport_offset(skb);
1553 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
1554 hdrlen += tcp_hdrlen(skb);
1557 * When software supplies two or more payload buffers all payload buffers
1558 * apart from the last must be a multiple of 8 bytes in size.
1560 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1561 return features & ~MACB_NETIF_LSO;
1563 nr_frags = skb_shinfo(skb)->nr_frags;
1564 /* No need to check last fragment */
1566 for (f = 0; f < nr_frags; f++) {
1567 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1569 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1570 return features & ~MACB_NETIF_LSO;
1575 static inline int macb_clear_csum(struct sk_buff *skb)
1577 /* no change for packets without checksum offloading */
1578 if (skb->ip_summed != CHECKSUM_PARTIAL)
1581 /* make sure we can modify the header */
1582 if (unlikely(skb_cow_head(skb, 0)))
1585 /* initialize checksum field
1586 * This is required - at least for Zynq, which otherwise calculates
1587 * wrong UDP header checksums for UDP packets with UDP data len <=2
1589 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1593 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1595 u16 queue_index = skb_get_queue_mapping(skb);
1596 struct macb *bp = netdev_priv(dev);
1597 struct macb_queue *queue = &bp->queues[queue_index];
1598 unsigned long flags;
1599 unsigned int desc_cnt, nr_frags, frag_size, f;
1600 unsigned int hdrlen;
1601 bool is_lso, is_udp = 0;
1603 is_lso = (skb_shinfo(skb)->gso_size != 0);
1606 is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP);
1608 /* length of headers */
1610 /* only queue eth + ip headers separately for UDP */
1611 hdrlen = skb_transport_offset(skb);
1613 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
1614 if (skb_headlen(skb) < hdrlen) {
1615 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
1616 /* if this is required, would need to copy to single buffer */
1617 return NETDEV_TX_BUSY;
1620 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
1622 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1623 netdev_vdbg(bp->dev,
1624 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1625 queue_index, skb->len, skb->head, skb->data,
1626 skb_tail_pointer(skb), skb_end_pointer(skb));
1627 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1628 skb->data, 16, true);
1631 /* Count how many TX buffer descriptors are needed to send this
1632 * socket buffer: skb fragments of jumbo frames may need to be
1633 * split into many buffer descriptors.
1635 if (is_lso && (skb_headlen(skb) > hdrlen))
1636 /* extra header descriptor if also payload in first buffer */
1637 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
1639 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1640 nr_frags = skb_shinfo(skb)->nr_frags;
1641 for (f = 0; f < nr_frags; f++) {
1642 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1643 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1646 spin_lock_irqsave(&bp->lock, flags);
1648 /* This is a hard error, log it. */
1649 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1650 bp->tx_ring_size) < desc_cnt) {
1651 netif_stop_subqueue(dev, queue_index);
1652 spin_unlock_irqrestore(&bp->lock, flags);
1653 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1654 queue->tx_head, queue->tx_tail);
1655 return NETDEV_TX_BUSY;
1658 if (macb_clear_csum(skb)) {
1659 dev_kfree_skb_any(skb);
1663 /* Map socket buffer for DMA transfer */
1664 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
1665 dev_kfree_skb_any(skb);
1669 /* Make newly initialized descriptor visible to hardware */
1671 skb_tx_timestamp(skb);
1673 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1675 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
1676 netif_stop_subqueue(dev, queue_index);
1679 spin_unlock_irqrestore(&bp->lock, flags);
1681 return NETDEV_TX_OK;
1684 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1686 if (!macb_is_gem(bp)) {
1687 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1689 bp->rx_buffer_size = size;
1691 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1693 "RX buffer must be multiple of %d bytes, expanding\n",
1694 RX_BUFFER_MULTIPLE);
1695 bp->rx_buffer_size =
1696 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1700 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
1701 bp->dev->mtu, bp->rx_buffer_size);
1704 static void gem_free_rx_buffers(struct macb *bp)
1706 struct sk_buff *skb;
1707 struct macb_dma_desc *desc;
1714 for (i = 0; i < bp->rx_ring_size; i++) {
1715 skb = bp->rx_skbuff[i];
1720 desc = macb_rx_desc(bp, i);
1721 addr = macb_get_addr(bp, desc);
1723 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1725 dev_kfree_skb_any(skb);
1729 kfree(bp->rx_skbuff);
1730 bp->rx_skbuff = NULL;
1733 static void macb_free_rx_buffers(struct macb *bp)
1735 if (bp->rx_buffers) {
1736 dma_free_coherent(&bp->pdev->dev,
1737 bp->rx_ring_size * bp->rx_buffer_size,
1738 bp->rx_buffers, bp->rx_buffers_dma);
1739 bp->rx_buffers = NULL;
1743 static void macb_free_consistent(struct macb *bp)
1745 struct macb_queue *queue;
1748 bp->macbgem_ops.mog_free_rx_buffers(bp);
1750 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES(bp),
1751 bp->rx_ring, bp->rx_ring_dma);
1755 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1756 kfree(queue->tx_skb);
1757 queue->tx_skb = NULL;
1758 if (queue->tx_ring) {
1759 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES(bp),
1760 queue->tx_ring, queue->tx_ring_dma);
1761 queue->tx_ring = NULL;
1766 static int gem_alloc_rx_buffers(struct macb *bp)
1770 size = bp->rx_ring_size * sizeof(struct sk_buff *);
1771 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1776 "Allocated %d RX struct sk_buff entries at %p\n",
1777 bp->rx_ring_size, bp->rx_skbuff);
1781 static int macb_alloc_rx_buffers(struct macb *bp)
1785 size = bp->rx_ring_size * bp->rx_buffer_size;
1786 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1787 &bp->rx_buffers_dma, GFP_KERNEL);
1788 if (!bp->rx_buffers)
1792 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1793 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1797 static int macb_alloc_consistent(struct macb *bp)
1799 struct macb_queue *queue;
1803 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1804 size = TX_RING_BYTES(bp);
1805 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1806 &queue->tx_ring_dma,
1808 if (!queue->tx_ring)
1811 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1812 q, size, (unsigned long)queue->tx_ring_dma,
1815 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
1816 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1821 size = RX_RING_BYTES(bp);
1822 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1823 &bp->rx_ring_dma, GFP_KERNEL);
1827 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1828 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1830 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1836 macb_free_consistent(bp);
1840 static void gem_init_rings(struct macb *bp)
1842 struct macb_queue *queue;
1843 struct macb_dma_desc *desc = NULL;
1847 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1848 for (i = 0; i < bp->tx_ring_size; i++) {
1849 desc = macb_tx_desc(queue, i);
1850 macb_set_addr(bp, desc, 0);
1851 desc->ctrl = MACB_BIT(TX_USED);
1853 desc->ctrl |= MACB_BIT(TX_WRAP);
1859 bp->rx_prepared_head = 0;
1864 static void macb_init_rings(struct macb *bp)
1867 struct macb_dma_desc *desc = NULL;
1869 macb_init_rx_ring(bp);
1871 for (i = 0; i < bp->tx_ring_size; i++) {
1872 desc = macb_tx_desc(&bp->queues[0], i);
1873 macb_set_addr(bp, desc, 0);
1874 desc->ctrl = MACB_BIT(TX_USED);
1876 bp->queues[0].tx_head = 0;
1877 bp->queues[0].tx_tail = 0;
1878 desc->ctrl |= MACB_BIT(TX_WRAP);
1881 static void macb_reset_hw(struct macb *bp)
1883 struct macb_queue *queue;
1886 /* Disable RX and TX (XXX: Should we halt the transmission
1889 macb_writel(bp, NCR, 0);
1891 /* Clear the stats registers (XXX: Update stats first?) */
1892 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1894 /* Clear all status flags */
1895 macb_writel(bp, TSR, -1);
1896 macb_writel(bp, RSR, -1);
1898 /* Disable all interrupts */
1899 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1900 queue_writel(queue, IDR, -1);
1901 queue_readl(queue, ISR);
1902 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1903 queue_writel(queue, ISR, -1);
1907 static u32 gem_mdc_clk_div(struct macb *bp)
1910 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1912 if (pclk_hz <= 20000000)
1913 config = GEM_BF(CLK, GEM_CLK_DIV8);
1914 else if (pclk_hz <= 40000000)
1915 config = GEM_BF(CLK, GEM_CLK_DIV16);
1916 else if (pclk_hz <= 80000000)
1917 config = GEM_BF(CLK, GEM_CLK_DIV32);
1918 else if (pclk_hz <= 120000000)
1919 config = GEM_BF(CLK, GEM_CLK_DIV48);
1920 else if (pclk_hz <= 160000000)
1921 config = GEM_BF(CLK, GEM_CLK_DIV64);
1923 config = GEM_BF(CLK, GEM_CLK_DIV96);
1928 static u32 macb_mdc_clk_div(struct macb *bp)
1931 unsigned long pclk_hz;
1933 if (macb_is_gem(bp))
1934 return gem_mdc_clk_div(bp);
1936 pclk_hz = clk_get_rate(bp->pclk);
1937 if (pclk_hz <= 20000000)
1938 config = MACB_BF(CLK, MACB_CLK_DIV8);
1939 else if (pclk_hz <= 40000000)
1940 config = MACB_BF(CLK, MACB_CLK_DIV16);
1941 else if (pclk_hz <= 80000000)
1942 config = MACB_BF(CLK, MACB_CLK_DIV32);
1944 config = MACB_BF(CLK, MACB_CLK_DIV64);
1949 /* Get the DMA bus width field of the network configuration register that we
1950 * should program. We find the width from decoding the design configuration
1951 * register to find the maximum supported data bus width.
1953 static u32 macb_dbw(struct macb *bp)
1955 if (!macb_is_gem(bp))
1958 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1960 return GEM_BF(DBW, GEM_DBW128);
1962 return GEM_BF(DBW, GEM_DBW64);
1965 return GEM_BF(DBW, GEM_DBW32);
1969 /* Configure the receive DMA engine
1970 * - use the correct receive buffer size
1971 * - set best burst length for DMA operations
1972 * (if not supported by FIFO, it will fallback to default)
1973 * - set both rx/tx packet buffers to full memory size
1974 * These are configurable parameters for GEM.
1976 static void macb_configure_dma(struct macb *bp)
1980 if (macb_is_gem(bp)) {
1981 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1982 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1983 if (bp->dma_burst_length)
1984 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
1985 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1986 dmacfg &= ~GEM_BIT(ENDIA_PKT);
1989 dmacfg &= ~GEM_BIT(ENDIA_DESC);
1991 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
1993 if (bp->dev->features & NETIF_F_HW_CSUM)
1994 dmacfg |= GEM_BIT(TXCOEN);
1996 dmacfg &= ~GEM_BIT(TXCOEN);
1998 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1999 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2000 dmacfg |= GEM_BIT(ADDR64);
2002 #ifdef CONFIG_MACB_USE_HWSTAMP
2003 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2004 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2006 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2008 gem_writel(bp, DMACFG, dmacfg);
2012 static void macb_init_hw(struct macb *bp)
2014 struct macb_queue *queue;
2020 macb_set_hwaddr(bp);
2022 config = macb_mdc_clk_div(bp);
2023 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2024 config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
2025 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2026 config |= MACB_BIT(PAE); /* PAuse Enable */
2027 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2028 if (bp->caps & MACB_CAPS_JUMBO)
2029 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2031 config |= MACB_BIT(BIG); /* Receive oversized frames */
2032 if (bp->dev->flags & IFF_PROMISC)
2033 config |= MACB_BIT(CAF); /* Copy All Frames */
2034 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2035 config |= GEM_BIT(RXCOEN);
2036 if (!(bp->dev->flags & IFF_BROADCAST))
2037 config |= MACB_BIT(NBC); /* No BroadCast */
2038 config |= macb_dbw(bp);
2039 macb_writel(bp, NCFGR, config);
2040 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2041 gem_writel(bp, JML, bp->jumbo_max_len);
2042 bp->speed = SPEED_10;
2043 bp->duplex = DUPLEX_HALF;
2044 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2045 if (bp->caps & MACB_CAPS_JUMBO)
2046 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2048 macb_configure_dma(bp);
2050 /* Initialize TX and RX buffers */
2051 macb_writel(bp, RBQP, lower_32_bits(bp->rx_ring_dma));
2052 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2053 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2054 macb_writel(bp, RBQPH, upper_32_bits(bp->rx_ring_dma));
2056 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2057 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
2058 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2059 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2060 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
2063 /* Enable interrupts */
2064 queue_writel(queue, IER,
2070 if ((bp->phy_interface == PHY_INTERFACE_MODE_SGMII) &&
2071 (bp->caps & MACB_CAPS_PCS))
2072 gem_writel(bp, PCSCNTRL,
2073 gem_readl(bp, PCSCNTRL) | GEM_BIT(PCSAUTONEG));
2075 /* Enable TX and RX */
2076 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
2079 /* The hash address register is 64 bits long and takes up two
2080 * locations in the memory map. The least significant bits are stored
2081 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2083 * The unicast hash enable and the multicast hash enable bits in the
2084 * network configuration register enable the reception of hash matched
2085 * frames. The destination address is reduced to a 6 bit index into
2086 * the 64 bit hash register using the following hash function. The
2087 * hash function is an exclusive or of every sixth bit of the
2088 * destination address.
2090 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2091 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2092 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2093 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2094 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2095 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2097 * da[0] represents the least significant bit of the first byte
2098 * received, that is, the multicast/unicast indicator, and da[47]
2099 * represents the most significant bit of the last byte received. If
2100 * the hash index, hi[n], points to a bit that is set in the hash
2101 * register then the frame will be matched according to whether the
2102 * frame is multicast or unicast. A multicast match will be signalled
2103 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2104 * index points to a bit set in the hash register. A unicast match
2105 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2106 * and the hash index points to a bit set in the hash register. To
2107 * receive all multicast frames, the hash register should be set with
2108 * all ones and the multicast hash enable bit should be set in the
2109 * network configuration register.
2112 static inline int hash_bit_value(int bitnr, __u8 *addr)
2114 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2119 /* Return the hash index value for the specified address. */
2120 static int hash_get_index(__u8 *addr)
2125 for (j = 0; j < 6; j++) {
2126 for (i = 0, bitval = 0; i < 8; i++)
2127 bitval ^= hash_bit_value(i * 6 + j, addr);
2129 hash_index |= (bitval << j);
2135 /* Add multicast addresses to the internal multicast-hash table. */
2136 static void macb_sethashtable(struct net_device *dev)
2138 struct netdev_hw_addr *ha;
2139 unsigned long mc_filter[2];
2141 struct macb *bp = netdev_priv(dev);
2146 netdev_for_each_mc_addr(ha, dev) {
2147 bitnr = hash_get_index(ha->addr);
2148 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2151 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2152 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2155 /* Enable/Disable promiscuous and multicast modes. */
2156 static void macb_set_rx_mode(struct net_device *dev)
2159 struct macb *bp = netdev_priv(dev);
2161 cfg = macb_readl(bp, NCFGR);
2163 if (dev->flags & IFF_PROMISC) {
2164 /* Enable promiscuous mode */
2165 cfg |= MACB_BIT(CAF);
2167 /* Disable RX checksum offload */
2168 if (macb_is_gem(bp))
2169 cfg &= ~GEM_BIT(RXCOEN);
2171 /* Disable promiscuous mode */
2172 cfg &= ~MACB_BIT(CAF);
2174 /* Enable RX checksum offload only if requested */
2175 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2176 cfg |= GEM_BIT(RXCOEN);
2179 if (dev->flags & IFF_ALLMULTI) {
2180 /* Enable all multicast mode */
2181 macb_or_gem_writel(bp, HRB, -1);
2182 macb_or_gem_writel(bp, HRT, -1);
2183 cfg |= MACB_BIT(NCFGR_MTI);
2184 } else if (!netdev_mc_empty(dev)) {
2185 /* Enable specific multicasts */
2186 macb_sethashtable(dev);
2187 cfg |= MACB_BIT(NCFGR_MTI);
2188 } else if (dev->flags & (~IFF_ALLMULTI)) {
2189 /* Disable all multicast mode */
2190 macb_or_gem_writel(bp, HRB, 0);
2191 macb_or_gem_writel(bp, HRT, 0);
2192 cfg &= ~MACB_BIT(NCFGR_MTI);
2195 macb_writel(bp, NCFGR, cfg);
2198 static int macb_open(struct net_device *dev)
2200 struct macb *bp = netdev_priv(dev);
2201 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2204 netdev_dbg(bp->dev, "open\n");
2206 /* carrier starts down */
2207 netif_carrier_off(dev);
2209 /* if the phy is not yet register, retry later*/
2213 /* RX buffers initialization */
2214 macb_init_rx_buffer_size(bp, bufsz);
2216 err = macb_alloc_consistent(bp);
2218 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2223 napi_enable(&bp->napi);
2225 bp->macbgem_ops.mog_init_rings(bp);
2228 /* schedule a link state check */
2229 phy_start(bp->phy_dev);
2231 netif_tx_start_all_queues(dev);
2234 bp->ptp_info->ptp_init(dev);
2239 static int macb_close(struct net_device *dev)
2241 struct macb *bp = netdev_priv(dev);
2242 unsigned long flags;
2244 netif_tx_stop_all_queues(dev);
2245 napi_disable(&bp->napi);
2248 phy_stop(bp->phy_dev);
2250 spin_lock_irqsave(&bp->lock, flags);
2252 netif_carrier_off(dev);
2253 spin_unlock_irqrestore(&bp->lock, flags);
2255 macb_free_consistent(bp);
2258 bp->ptp_info->ptp_remove(dev);
2263 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2265 if (netif_running(dev))
2273 static void gem_update_stats(struct macb *bp)
2276 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2278 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2279 u32 offset = gem_statistics[i].offset;
2280 u64 val = bp->macb_reg_readl(bp, offset);
2282 bp->ethtool_stats[i] += val;
2285 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2286 /* Add GEM_OCTTXH, GEM_OCTRXH */
2287 val = bp->macb_reg_readl(bp, offset + 4);
2288 bp->ethtool_stats[i] += ((u64)val) << 32;
2294 static struct net_device_stats *gem_get_stats(struct macb *bp)
2296 struct gem_stats *hwstat = &bp->hw_stats.gem;
2297 struct net_device_stats *nstat = &bp->dev->stats;
2299 gem_update_stats(bp);
2301 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2302 hwstat->rx_alignment_errors +
2303 hwstat->rx_resource_errors +
2304 hwstat->rx_overruns +
2305 hwstat->rx_oversize_frames +
2306 hwstat->rx_jabbers +
2307 hwstat->rx_undersized_frames +
2308 hwstat->rx_length_field_frame_errors);
2309 nstat->tx_errors = (hwstat->tx_late_collisions +
2310 hwstat->tx_excessive_collisions +
2311 hwstat->tx_underrun +
2312 hwstat->tx_carrier_sense_errors);
2313 nstat->multicast = hwstat->rx_multicast_frames;
2314 nstat->collisions = (hwstat->tx_single_collision_frames +
2315 hwstat->tx_multiple_collision_frames +
2316 hwstat->tx_excessive_collisions);
2317 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2318 hwstat->rx_jabbers +
2319 hwstat->rx_undersized_frames +
2320 hwstat->rx_length_field_frame_errors);
2321 nstat->rx_over_errors = hwstat->rx_resource_errors;
2322 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2323 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2324 nstat->rx_fifo_errors = hwstat->rx_overruns;
2325 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2326 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2327 nstat->tx_fifo_errors = hwstat->tx_underrun;
2332 static void gem_get_ethtool_stats(struct net_device *dev,
2333 struct ethtool_stats *stats, u64 *data)
2337 bp = netdev_priv(dev);
2338 gem_update_stats(bp);
2339 memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
2342 static int gem_get_sset_count(struct net_device *dev, int sset)
2346 return GEM_STATS_LEN;
2352 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2358 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2359 memcpy(p, gem_statistics[i].stat_string,
2365 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2367 struct macb *bp = netdev_priv(dev);
2368 struct net_device_stats *nstat = &bp->dev->stats;
2369 struct macb_stats *hwstat = &bp->hw_stats.macb;
2371 if (macb_is_gem(bp))
2372 return gem_get_stats(bp);
2374 /* read stats from hardware */
2375 macb_update_stats(bp);
2377 /* Convert HW stats into netdevice stats */
2378 nstat->rx_errors = (hwstat->rx_fcs_errors +
2379 hwstat->rx_align_errors +
2380 hwstat->rx_resource_errors +
2381 hwstat->rx_overruns +
2382 hwstat->rx_oversize_pkts +
2383 hwstat->rx_jabbers +
2384 hwstat->rx_undersize_pkts +
2385 hwstat->rx_length_mismatch);
2386 nstat->tx_errors = (hwstat->tx_late_cols +
2387 hwstat->tx_excessive_cols +
2388 hwstat->tx_underruns +
2389 hwstat->tx_carrier_errors +
2390 hwstat->sqe_test_errors);
2391 nstat->collisions = (hwstat->tx_single_cols +
2392 hwstat->tx_multiple_cols +
2393 hwstat->tx_excessive_cols);
2394 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2395 hwstat->rx_jabbers +
2396 hwstat->rx_undersize_pkts +
2397 hwstat->rx_length_mismatch);
2398 nstat->rx_over_errors = hwstat->rx_resource_errors +
2399 hwstat->rx_overruns;
2400 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2401 nstat->rx_frame_errors = hwstat->rx_align_errors;
2402 nstat->rx_fifo_errors = hwstat->rx_overruns;
2403 /* XXX: What does "missed" mean? */
2404 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2405 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2406 nstat->tx_fifo_errors = hwstat->tx_underruns;
2407 /* Don't know about heartbeat or window errors... */
2412 static int macb_get_regs_len(struct net_device *netdev)
2414 return MACB_GREGS_NBR * sizeof(u32);
2417 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2420 struct macb *bp = netdev_priv(dev);
2421 unsigned int tail, head;
2424 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2425 | MACB_GREGS_VERSION;
2427 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2428 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2430 regs_buff[0] = macb_readl(bp, NCR);
2431 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2432 regs_buff[2] = macb_readl(bp, NSR);
2433 regs_buff[3] = macb_readl(bp, TSR);
2434 regs_buff[4] = macb_readl(bp, RBQP);
2435 regs_buff[5] = macb_readl(bp, TBQP);
2436 regs_buff[6] = macb_readl(bp, RSR);
2437 regs_buff[7] = macb_readl(bp, IMR);
2439 regs_buff[8] = tail;
2440 regs_buff[9] = head;
2441 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2442 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2444 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2445 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2446 if (macb_is_gem(bp))
2447 regs_buff[13] = gem_readl(bp, DMACFG);
2450 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2452 struct macb *bp = netdev_priv(netdev);
2457 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2458 wol->supported = WAKE_MAGIC;
2460 if (bp->wol & MACB_WOL_ENABLED)
2461 wol->wolopts |= WAKE_MAGIC;
2465 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2467 struct macb *bp = netdev_priv(netdev);
2469 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2470 (wol->wolopts & ~WAKE_MAGIC))
2473 if (wol->wolopts & WAKE_MAGIC)
2474 bp->wol |= MACB_WOL_ENABLED;
2476 bp->wol &= ~MACB_WOL_ENABLED;
2478 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2483 static void macb_get_ringparam(struct net_device *netdev,
2484 struct ethtool_ringparam *ring)
2486 struct macb *bp = netdev_priv(netdev);
2488 ring->rx_max_pending = MAX_RX_RING_SIZE;
2489 ring->tx_max_pending = MAX_TX_RING_SIZE;
2491 ring->rx_pending = bp->rx_ring_size;
2492 ring->tx_pending = bp->tx_ring_size;
2495 static int macb_set_ringparam(struct net_device *netdev,
2496 struct ethtool_ringparam *ring)
2498 struct macb *bp = netdev_priv(netdev);
2499 u32 new_rx_size, new_tx_size;
2500 unsigned int reset = 0;
2502 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2505 new_rx_size = clamp_t(u32, ring->rx_pending,
2506 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2507 new_rx_size = roundup_pow_of_two(new_rx_size);
2509 new_tx_size = clamp_t(u32, ring->tx_pending,
2510 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2511 new_tx_size = roundup_pow_of_two(new_tx_size);
2513 if ((new_tx_size == bp->tx_ring_size) &&
2514 (new_rx_size == bp->rx_ring_size)) {
2519 if (netif_running(bp->dev)) {
2521 macb_close(bp->dev);
2524 bp->rx_ring_size = new_rx_size;
2525 bp->tx_ring_size = new_tx_size;
2533 #ifdef CONFIG_MACB_USE_HWSTAMP
2534 static unsigned int gem_get_tsu_rate(struct macb *bp)
2536 struct clk *tsu_clk;
2537 unsigned int tsu_rate;
2539 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2540 if (!IS_ERR(tsu_clk))
2541 tsu_rate = clk_get_rate(tsu_clk);
2542 /* try pclk instead */
2543 else if (!IS_ERR(bp->pclk)) {
2545 tsu_rate = clk_get_rate(tsu_clk);
2551 static s32 gem_get_ptp_max_adj(void)
2556 static int gem_get_ts_info(struct net_device *dev,
2557 struct ethtool_ts_info *info)
2559 struct macb *bp = netdev_priv(dev);
2561 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
2562 ethtool_op_get_ts_info(dev, info);
2566 info->so_timestamping =
2567 SOF_TIMESTAMPING_TX_SOFTWARE |
2568 SOF_TIMESTAMPING_RX_SOFTWARE |
2569 SOF_TIMESTAMPING_SOFTWARE |
2570 SOF_TIMESTAMPING_TX_HARDWARE |
2571 SOF_TIMESTAMPING_RX_HARDWARE |
2572 SOF_TIMESTAMPING_RAW_HARDWARE;
2574 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
2575 (1 << HWTSTAMP_TX_OFF) |
2576 (1 << HWTSTAMP_TX_ON);
2578 (1 << HWTSTAMP_FILTER_NONE) |
2579 (1 << HWTSTAMP_FILTER_ALL);
2581 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
2586 static struct macb_ptp_info gem_ptp_info = {
2587 .ptp_init = gem_ptp_init,
2588 .ptp_remove = gem_ptp_remove,
2589 .get_ptp_max_adj = gem_get_ptp_max_adj,
2590 .get_tsu_rate = gem_get_tsu_rate,
2591 .get_ts_info = gem_get_ts_info,
2592 .get_hwtst = gem_get_hwtst,
2593 .set_hwtst = gem_set_hwtst,
2597 static int macb_get_ts_info(struct net_device *netdev,
2598 struct ethtool_ts_info *info)
2600 struct macb *bp = netdev_priv(netdev);
2603 return bp->ptp_info->get_ts_info(netdev, info);
2605 return ethtool_op_get_ts_info(netdev, info);
2608 static const struct ethtool_ops macb_ethtool_ops = {
2609 .get_regs_len = macb_get_regs_len,
2610 .get_regs = macb_get_regs,
2611 .get_link = ethtool_op_get_link,
2612 .get_ts_info = ethtool_op_get_ts_info,
2613 .get_wol = macb_get_wol,
2614 .set_wol = macb_set_wol,
2615 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2616 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2617 .get_ringparam = macb_get_ringparam,
2618 .set_ringparam = macb_set_ringparam,
2621 static const struct ethtool_ops gem_ethtool_ops = {
2622 .get_regs_len = macb_get_regs_len,
2623 .get_regs = macb_get_regs,
2624 .get_link = ethtool_op_get_link,
2625 .get_ts_info = macb_get_ts_info,
2626 .get_ethtool_stats = gem_get_ethtool_stats,
2627 .get_strings = gem_get_ethtool_strings,
2628 .get_sset_count = gem_get_sset_count,
2629 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2630 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2631 .get_ringparam = macb_get_ringparam,
2632 .set_ringparam = macb_set_ringparam,
2635 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2637 struct phy_device *phydev = dev->phydev;
2638 struct macb *bp = netdev_priv(dev);
2640 if (!netif_running(dev))
2647 return phy_mii_ioctl(phydev, rq, cmd);
2651 return bp->ptp_info->set_hwtst(dev, rq, cmd);
2653 return bp->ptp_info->get_hwtst(dev, rq);
2655 return phy_mii_ioctl(phydev, rq, cmd);
2659 static int macb_set_features(struct net_device *netdev,
2660 netdev_features_t features)
2662 struct macb *bp = netdev_priv(netdev);
2663 netdev_features_t changed = features ^ netdev->features;
2665 /* TX checksum offload */
2666 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2669 dmacfg = gem_readl(bp, DMACFG);
2670 if (features & NETIF_F_HW_CSUM)
2671 dmacfg |= GEM_BIT(TXCOEN);
2673 dmacfg &= ~GEM_BIT(TXCOEN);
2674 gem_writel(bp, DMACFG, dmacfg);
2677 /* RX checksum offload */
2678 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2681 netcfg = gem_readl(bp, NCFGR);
2682 if (features & NETIF_F_RXCSUM &&
2683 !(netdev->flags & IFF_PROMISC))
2684 netcfg |= GEM_BIT(RXCOEN);
2686 netcfg &= ~GEM_BIT(RXCOEN);
2687 gem_writel(bp, NCFGR, netcfg);
2693 static const struct net_device_ops macb_netdev_ops = {
2694 .ndo_open = macb_open,
2695 .ndo_stop = macb_close,
2696 .ndo_start_xmit = macb_start_xmit,
2697 .ndo_set_rx_mode = macb_set_rx_mode,
2698 .ndo_get_stats = macb_get_stats,
2699 .ndo_do_ioctl = macb_ioctl,
2700 .ndo_validate_addr = eth_validate_addr,
2701 .ndo_change_mtu = macb_change_mtu,
2702 .ndo_set_mac_address = eth_mac_addr,
2703 #ifdef CONFIG_NET_POLL_CONTROLLER
2704 .ndo_poll_controller = macb_poll_controller,
2706 .ndo_set_features = macb_set_features,
2707 .ndo_features_check = macb_features_check,
2710 /* Configure peripheral capabilities according to device tree
2711 * and integration options used
2713 static void macb_configure_caps(struct macb *bp,
2714 const struct macb_config *dt_conf)
2719 bp->caps = dt_conf->caps;
2721 if (hw_is_gem(bp->regs, bp->native_io)) {
2722 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2724 dcfg = gem_readl(bp, DCFG1);
2725 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2726 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2727 dcfg = gem_readl(bp, DCFG2);
2728 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2729 bp->caps |= MACB_CAPS_FIFO_MODE;
2730 #ifdef CONFIG_MACB_USE_HWSTAMP
2731 if (gem_has_ptp(bp)) {
2732 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
2733 pr_err("GEM doesn't support hardware ptp.\n");
2735 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
2736 bp->ptp_info = &gem_ptp_info;
2742 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
2745 #if defined(CONFIG_OF)
2746 static void macb_reset_phy(struct platform_device *pdev)
2748 int err, phy_reset, msec = 1;
2750 struct device_node *np = pdev->dev.of_node;
2755 of_property_read_u32(np, "phy-reset-duration", &msec);
2756 active_low = of_property_read_bool(np, "phy-reset-active-low");
2758 phy_reset = of_get_named_gpio(np, "phy-reset-gpio", 0);
2759 if (!gpio_is_valid(phy_reset))
2762 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2763 active_low ? GPIOF_OUT_INIT_LOW :
2764 GPIOF_OUT_INIT_HIGH, "phy-reset");
2766 dev_err(&pdev->dev, "failed to get phy-reset-gpio: %d\n", err);
2770 gpio_set_value(phy_reset, active_low);
2772 #else /* CONFIG_OF */
2773 static void macb_reset_phy(struct platform_device *pdev)
2776 #endif /* CONFIG_OF */
2778 static void macb_probe_queues(void __iomem *mem,
2780 unsigned int *queue_mask,
2781 unsigned int *num_queues)
2788 /* is it macb or gem ?
2790 * We need to read directly from the hardware here because
2791 * we are early in the probe process and don't have the
2792 * MACB_CAPS_MACB_IS_GEM flag positioned
2794 if (!hw_is_gem(mem, native_io))
2797 /* bit 0 is never set but queue 0 always exists */
2798 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2802 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2803 if (*queue_mask & (1 << hw_q))
2807 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
2808 struct clk **hclk, struct clk **tx_clk,
2809 struct clk **rx_clk)
2811 struct macb_platform_data *pdata;
2814 pdata = dev_get_platdata(&pdev->dev);
2816 *pclk = pdata->pclk;
2817 *hclk = pdata->hclk;
2819 *pclk = devm_clk_get(&pdev->dev, "pclk");
2820 *hclk = devm_clk_get(&pdev->dev, "hclk");
2823 if (IS_ERR(*pclk)) {
2824 err = PTR_ERR(*pclk);
2825 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
2829 if (IS_ERR(*hclk)) {
2830 err = PTR_ERR(*hclk);
2831 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
2835 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2836 if (IS_ERR(*tx_clk))
2839 *rx_clk = devm_clk_get(&pdev->dev, "rx_clk");
2840 if (IS_ERR(*rx_clk))
2843 err = clk_prepare_enable(*pclk);
2845 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2849 err = clk_prepare_enable(*hclk);
2851 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
2852 goto err_disable_pclk;
2855 err = clk_prepare_enable(*tx_clk);
2857 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
2858 goto err_disable_hclk;
2861 err = clk_prepare_enable(*rx_clk);
2863 dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err);
2864 goto err_disable_txclk;
2870 clk_disable_unprepare(*tx_clk);
2873 clk_disable_unprepare(*hclk);
2876 clk_disable_unprepare(*pclk);
2881 static int macb_init(struct platform_device *pdev)
2883 struct net_device *dev = platform_get_drvdata(pdev);
2884 unsigned int hw_q, q;
2885 struct macb *bp = netdev_priv(dev);
2886 struct macb_queue *queue;
2890 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
2891 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
2893 /* set the queue register mapping once for all: queue0 has a special
2894 * register mapping but we don't want to test the queue index then
2895 * compute the corresponding register offset at run time.
2897 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
2898 if (!(bp->queue_mask & (1 << hw_q)))
2901 queue = &bp->queues[q];
2904 queue->ISR = GEM_ISR(hw_q - 1);
2905 queue->IER = GEM_IER(hw_q - 1);
2906 queue->IDR = GEM_IDR(hw_q - 1);
2907 queue->IMR = GEM_IMR(hw_q - 1);
2908 queue->TBQP = GEM_TBQP(hw_q - 1);
2909 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2910 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2911 queue->TBQPH = GEM_TBQPH(hw_q - 1);
2914 /* queue0 uses legacy registers */
2915 queue->ISR = MACB_ISR;
2916 queue->IER = MACB_IER;
2917 queue->IDR = MACB_IDR;
2918 queue->IMR = MACB_IMR;
2919 queue->TBQP = MACB_TBQP;
2920 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2921 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2922 queue->TBQPH = MACB_TBQPH;
2926 /* get irq: here we use the linux queue index, not the hardware
2927 * queue index. the queue irq definitions in the device tree
2928 * must remove the optional gaps that could exist in the
2929 * hardware queue mask.
2931 queue->irq = platform_get_irq(pdev, q);
2932 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
2933 IRQF_SHARED, dev->name, queue);
2936 "Unable to request IRQ %d (error %d)\n",
2941 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
2945 dev->netdev_ops = &macb_netdev_ops;
2946 netif_napi_add(dev, &bp->napi, macb_poll, 64);
2948 /* setup appropriated routines according to adapter type */
2949 if (macb_is_gem(bp)) {
2950 bp->max_tx_length = GEM_MAX_TX_LEN;
2951 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2952 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2953 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2954 bp->macbgem_ops.mog_rx = gem_rx;
2955 dev->ethtool_ops = &gem_ethtool_ops;
2957 bp->max_tx_length = MACB_MAX_TX_LEN;
2958 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2959 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2960 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2961 bp->macbgem_ops.mog_rx = macb_rx;
2962 dev->ethtool_ops = &macb_ethtool_ops;
2966 dev->hw_features = NETIF_F_SG;
2968 /* Check LSO capability */
2969 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
2970 dev->hw_features |= MACB_NETIF_LSO;
2972 /* Checksum offload is only available on gem with packet buffer */
2973 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
2974 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2975 if (bp->caps & MACB_CAPS_SG_DISABLED)
2976 dev->hw_features &= ~NETIF_F_SG;
2977 dev->features = dev->hw_features;
2979 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
2981 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2982 val = GEM_BIT(RGMII);
2983 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
2984 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
2985 val = MACB_BIT(RMII);
2986 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
2987 val = MACB_BIT(MII);
2989 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
2990 val |= MACB_BIT(CLKEN);
2992 macb_or_gem_writel(bp, USRIO, val);
2995 /* Set MII management clock divider */
2996 val = macb_mdc_clk_div(bp);
2997 val |= macb_dbw(bp);
2998 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2999 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3000 macb_writel(bp, NCFGR, val);
3002 if ((bp->phy_interface == PHY_INTERFACE_MODE_SGMII) &&
3003 (bp->caps & MACB_CAPS_PCS))
3004 gem_writel(bp, PCSCNTRL,
3005 gem_readl(bp, PCSCNTRL) | GEM_BIT(PCSAUTONEG));
3010 #if defined(CONFIG_OF)
3011 /* 1518 rounded up */
3012 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3013 /* max number of receive buffers */
3014 #define AT91ETHER_MAX_RX_DESCR 9
3016 /* Initialize and start the Receiver and Transmit subsystems */
3017 static int at91ether_start(struct net_device *dev)
3019 struct macb *lp = netdev_priv(dev);
3020 struct macb_dma_desc *desc;
3025 lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3026 (AT91ETHER_MAX_RX_DESCR *
3027 macb_dma_desc_get_size(lp)),
3028 &lp->rx_ring_dma, GFP_KERNEL);
3032 lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3033 AT91ETHER_MAX_RX_DESCR *
3034 AT91ETHER_MAX_RBUFF_SZ,
3035 &lp->rx_buffers_dma, GFP_KERNEL);
3036 if (!lp->rx_buffers) {
3037 dma_free_coherent(&lp->pdev->dev,
3038 AT91ETHER_MAX_RX_DESCR *
3039 macb_dma_desc_get_size(lp),
3040 lp->rx_ring, lp->rx_ring_dma);
3045 addr = lp->rx_buffers_dma;
3046 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3047 desc = macb_rx_desc(lp, i);
3048 macb_set_addr(lp, desc, addr);
3050 addr += AT91ETHER_MAX_RBUFF_SZ;
3053 /* Set the Wrap bit on the last descriptor */
3054 desc->addr |= MACB_BIT(RX_WRAP);
3056 /* Reset buffer index */
3059 /* Program address of descriptor list in Rx Buffer Queue register */
3060 macb_writel(lp, RBQP, lp->rx_ring_dma);
3062 /* Enable Receive and Transmit */
3063 ctl = macb_readl(lp, NCR);
3064 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3069 /* Open the ethernet interface */
3070 static int at91ether_open(struct net_device *dev)
3072 struct macb *lp = netdev_priv(dev);
3076 /* Clear internal statistics */
3077 ctl = macb_readl(lp, NCR);
3078 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3080 macb_set_hwaddr(lp);
3082 ret = at91ether_start(dev);
3086 /* Enable MAC interrupts */
3087 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3089 MACB_BIT(ISR_TUND) |
3092 MACB_BIT(ISR_ROVR) |
3095 /* schedule a link state check */
3096 phy_start(lp->phy_dev);
3098 netif_start_queue(dev);
3103 /* Close the interface */
3104 static int at91ether_close(struct net_device *dev)
3106 struct macb *lp = netdev_priv(dev);
3109 /* Disable Receiver and Transmitter */
3110 ctl = macb_readl(lp, NCR);
3111 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3113 /* Disable MAC interrupts */
3114 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3116 MACB_BIT(ISR_TUND) |
3119 MACB_BIT(ISR_ROVR) |
3122 netif_stop_queue(dev);
3124 dma_free_coherent(&lp->pdev->dev,
3125 AT91ETHER_MAX_RX_DESCR *
3126 macb_dma_desc_get_size(lp),
3127 lp->rx_ring, lp->rx_ring_dma);
3130 dma_free_coherent(&lp->pdev->dev,
3131 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
3132 lp->rx_buffers, lp->rx_buffers_dma);
3133 lp->rx_buffers = NULL;
3138 /* Transmit packet */
3139 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
3141 struct macb *lp = netdev_priv(dev);
3143 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3144 netif_stop_queue(dev);
3146 /* Store packet information (to free when Tx completed) */
3148 lp->skb_length = skb->len;
3149 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
3151 if (dma_mapping_error(NULL, lp->skb_physaddr)) {
3152 dev_kfree_skb_any(skb);
3153 dev->stats.tx_dropped++;
3154 netdev_err(dev, "%s: DMA mapping error\n", __func__);
3155 return NETDEV_TX_OK;
3158 /* Set address of the data in the Transmit Address register */
3159 macb_writel(lp, TAR, lp->skb_physaddr);
3160 /* Set length of the packet in the Transmit Control register */
3161 macb_writel(lp, TCR, skb->len);
3164 netdev_err(dev, "%s called, but device is busy!\n", __func__);
3165 return NETDEV_TX_BUSY;
3168 return NETDEV_TX_OK;
3171 /* Extract received frame from buffer descriptors and sent to upper layers.
3172 * (Called from interrupt context)
3174 static void at91ether_rx(struct net_device *dev)
3176 struct macb *lp = netdev_priv(dev);
3177 struct macb_dma_desc *desc;
3178 unsigned char *p_recv;
3179 struct sk_buff *skb;
3180 unsigned int pktlen;
3182 desc = macb_rx_desc(lp, lp->rx_tail);
3183 while (desc->addr & MACB_BIT(RX_USED)) {
3184 p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
3185 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
3186 skb = netdev_alloc_skb(dev, pktlen + 2);
3188 skb_reserve(skb, 2);
3189 skb_put_data(skb, p_recv, pktlen);
3191 skb->protocol = eth_type_trans(skb, dev);
3192 dev->stats.rx_packets++;
3193 dev->stats.rx_bytes += pktlen;
3196 dev->stats.rx_dropped++;
3199 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
3200 dev->stats.multicast++;
3202 /* reset ownership bit */
3203 desc->addr &= ~MACB_BIT(RX_USED);
3205 /* wrap after last buffer */
3206 if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
3211 desc = macb_rx_desc(lp, lp->rx_tail);
3215 /* MAC interrupt handler */
3216 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
3218 struct net_device *dev = dev_id;
3219 struct macb *lp = netdev_priv(dev);
3222 /* MAC Interrupt Status register indicates what interrupts are pending.
3223 * It is automatically cleared once read.
3225 intstatus = macb_readl(lp, ISR);
3227 /* Receive complete */
3228 if (intstatus & MACB_BIT(RCOMP))
3231 /* Transmit complete */
3232 if (intstatus & MACB_BIT(TCOMP)) {
3233 /* The TCOM bit is set even if the transmission failed */
3234 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
3235 dev->stats.tx_errors++;
3238 dev_kfree_skb_irq(lp->skb);
3240 dma_unmap_single(NULL, lp->skb_physaddr,
3241 lp->skb_length, DMA_TO_DEVICE);
3242 dev->stats.tx_packets++;
3243 dev->stats.tx_bytes += lp->skb_length;
3245 netif_wake_queue(dev);
3248 /* Work-around for EMAC Errata section 41.3.1 */
3249 if (intstatus & MACB_BIT(RXUBR)) {
3250 ctl = macb_readl(lp, NCR);
3251 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
3253 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
3256 if (intstatus & MACB_BIT(ISR_ROVR))
3257 netdev_err(dev, "ROVR error\n");
3262 #ifdef CONFIG_NET_POLL_CONTROLLER
3263 static void at91ether_poll_controller(struct net_device *dev)
3265 unsigned long flags;
3267 local_irq_save(flags);
3268 at91ether_interrupt(dev->irq, dev);
3269 local_irq_restore(flags);
3273 static const struct net_device_ops at91ether_netdev_ops = {
3274 .ndo_open = at91ether_open,
3275 .ndo_stop = at91ether_close,
3276 .ndo_start_xmit = at91ether_start_xmit,
3277 .ndo_get_stats = macb_get_stats,
3278 .ndo_set_rx_mode = macb_set_rx_mode,
3279 .ndo_set_mac_address = eth_mac_addr,
3280 .ndo_do_ioctl = macb_ioctl,
3281 .ndo_validate_addr = eth_validate_addr,
3282 #ifdef CONFIG_NET_POLL_CONTROLLER
3283 .ndo_poll_controller = at91ether_poll_controller,
3287 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
3288 struct clk **hclk, struct clk **tx_clk,
3289 struct clk **rx_clk)
3297 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
3299 return PTR_ERR(*pclk);
3301 err = clk_prepare_enable(*pclk);
3303 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
3310 static int at91ether_init(struct platform_device *pdev)
3312 struct net_device *dev = platform_get_drvdata(pdev);
3313 struct macb *bp = netdev_priv(dev);
3317 dev->netdev_ops = &at91ether_netdev_ops;
3318 dev->ethtool_ops = &macb_ethtool_ops;
3320 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
3325 macb_writel(bp, NCR, 0);
3327 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
3328 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
3329 reg |= MACB_BIT(RM9200_RMII);
3331 macb_writel(bp, NCFGR, reg);
3336 static const struct macb_config at91sam9260_config = {
3337 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3338 .clk_init = macb_clk_init,
3342 static const struct macb_config pc302gem_config = {
3343 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
3344 .dma_burst_length = 16,
3345 .clk_init = macb_clk_init,
3349 static const struct macb_config sama5d2_config = {
3350 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3351 .dma_burst_length = 16,
3352 .clk_init = macb_clk_init,
3356 static const struct macb_config sama5d3_config = {
3357 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
3358 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
3359 .dma_burst_length = 16,
3360 .clk_init = macb_clk_init,
3362 .jumbo_max_len = 10240,
3365 static const struct macb_config sama5d4_config = {
3366 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3367 .dma_burst_length = 4,
3368 .clk_init = macb_clk_init,
3372 static const struct macb_config emac_config = {
3373 .clk_init = at91ether_clk_init,
3374 .init = at91ether_init,
3377 static const struct macb_config np4_config = {
3378 .caps = MACB_CAPS_USRIO_DISABLED,
3379 .clk_init = macb_clk_init,
3383 static const struct macb_config zynqmp_config = {
3384 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
3385 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_PCS,
3386 .dma_burst_length = 16,
3387 .clk_init = macb_clk_init,
3389 .jumbo_max_len = 10240,
3392 static const struct macb_config zynq_config = {
3393 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF,
3394 .dma_burst_length = 16,
3395 .clk_init = macb_clk_init,
3399 static const struct of_device_id macb_dt_ids[] = {
3400 { .compatible = "cdns,at32ap7000-macb" },
3401 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
3402 { .compatible = "cdns,macb" },
3403 { .compatible = "cdns,np4-macb", .data = &np4_config },
3404 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
3405 { .compatible = "cdns,gem", .data = &pc302gem_config },
3406 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
3407 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
3408 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
3409 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
3410 { .compatible = "cdns,emac", .data = &emac_config },
3411 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
3412 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
3415 MODULE_DEVICE_TABLE(of, macb_dt_ids);
3416 #endif /* CONFIG_OF */
3418 static const struct macb_config default_gem_config = {
3419 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3421 MACB_CAPS_GEM_HAS_PTP,
3422 .dma_burst_length = 16,
3423 .clk_init = macb_clk_init,
3425 .jumbo_max_len = 10240,
3428 static int macb_probe(struct platform_device *pdev)
3430 const struct macb_config *macb_config = &default_gem_config;
3431 int (*clk_init)(struct platform_device *, struct clk **,
3432 struct clk **, struct clk **, struct clk **)
3433 = macb_config->clk_init;
3434 int (*init)(struct platform_device *) = macb_config->init;
3435 struct device_node *np = pdev->dev.of_node;
3436 struct device_node *phy_node;
3437 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
3438 unsigned int queue_mask, num_queues;
3439 struct macb_platform_data *pdata;
3441 struct phy_device *phydev;
3442 struct net_device *dev;
3443 struct resource *regs;
3449 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3450 mem = devm_ioremap_resource(&pdev->dev, regs);
3452 return PTR_ERR(mem);
3455 const struct of_device_id *match;
3457 match = of_match_node(macb_dt_ids, np);
3458 if (match && match->data) {
3459 macb_config = match->data;
3460 clk_init = macb_config->clk_init;
3461 init = macb_config->init;
3465 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk);
3469 native_io = hw_is_native_io(mem);
3471 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
3472 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
3475 goto err_disable_clocks;
3478 dev->base_addr = regs->start;
3480 SET_NETDEV_DEV(dev, &pdev->dev);
3482 bp = netdev_priv(dev);
3486 bp->native_io = native_io;
3488 bp->macb_reg_readl = hw_readl_native;
3489 bp->macb_reg_writel = hw_writel_native;
3491 bp->macb_reg_readl = hw_readl;
3492 bp->macb_reg_writel = hw_writel;
3494 bp->num_queues = num_queues;
3495 bp->queue_mask = queue_mask;
3497 bp->dma_burst_length = macb_config->dma_burst_length;
3500 bp->tx_clk = tx_clk;
3501 bp->rx_clk = rx_clk;
3503 bp->jumbo_max_len = macb_config->jumbo_max_len;
3506 if (of_get_property(np, "magic-packet", NULL))
3507 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
3508 device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
3510 spin_lock_init(&bp->lock);
3512 /* setup capabilities */
3513 macb_configure_caps(bp, macb_config);
3515 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3516 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
3517 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
3518 bp->hw_dma_cap |= HW_DMA_CAP_64B;
3521 platform_set_drvdata(pdev, dev);
3523 dev->irq = platform_get_irq(pdev, 0);
3526 goto err_out_free_netdev;
3529 /* MTU range: 68 - 1500 or 10240 */
3530 dev->min_mtu = GEM_MTU_MIN_SIZE;
3531 if (bp->caps & MACB_CAPS_JUMBO)
3532 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
3534 dev->max_mtu = ETH_DATA_LEN;
3536 mac = of_get_mac_address(np);
3538 ether_addr_copy(bp->dev->dev_addr, mac);
3540 macb_get_hwaddr(bp);
3542 /* Power up the PHY if there is a GPIO reset */
3543 phy_node = of_parse_phandle(np, "phy-handle", 0);
3544 if (!phy_node && of_phy_is_fixed_link(np)) {
3545 err = of_phy_register_fixed_link(np);
3547 dev_err(&pdev->dev, "broken fixed-link specification");
3550 phy_node = of_node_get(np);
3551 bp->phy_node = phy_node;
3553 int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0);
3555 if (gpio_is_valid(gpio)) {
3556 bp->reset_gpio = gpio_to_desc(gpio);
3557 gpiod_direction_output(bp->reset_gpio, 1);
3561 err = of_get_phy_mode(np);
3563 pdata = dev_get_platdata(&pdev->dev);
3564 if (pdata && pdata->is_rmii)
3565 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
3567 bp->phy_interface = PHY_INTERFACE_MODE_MII;
3569 bp->phy_interface = err;
3572 macb_reset_phy(pdev);
3574 /* IP specific init */
3577 goto err_out_free_netdev;
3579 err = macb_mii_init(bp);
3581 goto err_out_free_netdev;
3583 phydev = dev->phydev;
3585 netif_carrier_off(dev);
3587 err = register_netdev(dev);
3589 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
3590 goto err_out_unregister_mdio;
3593 phy_attached_info(phydev);
3595 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
3596 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
3597 dev->base_addr, dev->irq, dev->dev_addr);
3599 phydev = bp->phy_dev;
3603 err_out_unregister_mdio:
3604 phy_disconnect(dev->phydev);
3605 mdiobus_unregister(bp->mii_bus);
3606 mdiobus_free(bp->mii_bus);
3608 /* Shutdown the PHY if there is a GPIO reset */
3610 gpiod_set_value(bp->reset_gpio, 0);
3612 err_out_free_netdev:
3616 of_node_put(phy_node);
3619 clk_disable_unprepare(tx_clk);
3620 clk_disable_unprepare(hclk);
3621 clk_disable_unprepare(pclk);
3622 clk_disable_unprepare(rx_clk);
3627 static int macb_remove(struct platform_device *pdev)
3629 struct net_device *dev;
3632 dev = platform_get_drvdata(pdev);
3635 bp = netdev_priv(dev);
3637 phy_disconnect(bp->phy_dev);
3638 mdiobus_unregister(bp->mii_bus);
3640 mdiobus_free(bp->mii_bus);
3642 /* Shutdown the PHY if there is a GPIO reset */
3644 gpiod_set_value(bp->reset_gpio, 0);
3646 unregister_netdev(dev);
3647 clk_disable_unprepare(bp->tx_clk);
3648 clk_disable_unprepare(bp->hclk);
3649 clk_disable_unprepare(bp->pclk);
3650 clk_disable_unprepare(bp->rx_clk);
3651 of_node_put(bp->phy_node);
3658 static int __maybe_unused macb_suspend(struct device *dev)
3660 struct platform_device *pdev = to_platform_device(dev);
3661 struct net_device *netdev = platform_get_drvdata(pdev);
3662 struct macb *bp = netdev_priv(netdev);
3664 netif_carrier_off(netdev);
3665 netif_device_detach(netdev);
3667 if (bp->wol & MACB_WOL_ENABLED) {
3668 macb_writel(bp, IER, MACB_BIT(WOL));
3669 macb_writel(bp, WOL, MACB_BIT(MAG));
3670 enable_irq_wake(bp->queues[0].irq);
3672 clk_disable_unprepare(bp->tx_clk);
3673 clk_disable_unprepare(bp->hclk);
3674 clk_disable_unprepare(bp->pclk);
3675 clk_disable_unprepare(bp->rx_clk);
3681 static int __maybe_unused macb_resume(struct device *dev)
3683 struct platform_device *pdev = to_platform_device(dev);
3684 struct net_device *netdev = platform_get_drvdata(pdev);
3685 struct macb *bp = netdev_priv(netdev);
3687 if (bp->wol & MACB_WOL_ENABLED) {
3688 macb_writel(bp, IDR, MACB_BIT(WOL));
3689 macb_writel(bp, WOL, 0);
3690 disable_irq_wake(bp->queues[0].irq);
3692 clk_prepare_enable(bp->pclk);
3693 clk_prepare_enable(bp->hclk);
3694 clk_prepare_enable(bp->tx_clk);
3695 clk_prepare_enable(bp->rx_clk);
3698 netif_device_attach(netdev);
3703 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
3705 static struct platform_driver macb_driver = {
3706 .probe = macb_probe,
3707 .remove = macb_remove,
3710 .of_match_table = of_match_ptr(macb_dt_ids),
3715 module_platform_driver(macb_driver);
3717 MODULE_LICENSE("GPL");
3718 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
3719 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
3720 MODULE_ALIAS("platform:macb");