1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Xilinx Scene Change Detection driver
5 * Copyright (C) 2018 Xilinx, Inc.
7 * Author: Anand Ashok Dumbre <anand.ashok.dumbre@xilinx.com>
10 #ifndef _XILINX_SCENECHANGE_H_
11 #define _XILINX_SCENECHANGE_H_
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
21 #include <linux/of_irq.h>
22 #include <linux/platform_device.h>
23 #include <linux/xilinx-v4l2-controls.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-subdev.h>
29 #include "../../../dma/dmaengine.h"
31 /* Register/Descriptor Offsets */
32 #define XILINX_XSCD_ISR_OFFSET 0x0c
33 #define XILINX_XSCD_SAD_OFFSET 0x38
34 #define XILINX_XSCD_CHAN_OFFSET 0x100
36 /* Interrupt Status and Control */
37 #define XILINX_XSCD_IE_AP_DONE BIT(0)
38 #define XILINX_XSCD_IE_AP_READY BIT(1)
40 #define XSCD_MAX_CHANNELS 8
42 /****************************** PROTOTYPES ************************************/
43 #define to_xilinx_chan(chan) \
44 container_of(chan, struct xscd_dma_chan, common)
45 #define to_dma_tx_descriptor(tx) \
46 container_of(tx, struct xscd_dma_tx_descriptor, async_tx)
49 * struct xscd_shared_data - Data to be shared among v4l subdev and DMA engine
50 * @iomem: device I/O register space remapped to kernel virtual memory
51 * @dma_chan_list: List of DMA channels available
52 * @active_streams: Number of active streams
54 struct xscd_shared_data {
56 struct xscd_dma_chan *dma_chan_list[XSCD_MAX_CHANNELS];
61 * struct xscd_device - Xilinx Scene Change Detection device structure
62 * @iomem: device I/O register space remapped to kernel virtual memory
63 * @memorybased: Flag to identify memory based mode
64 * @numstreams: Number of streams in the design
67 * @rst_gpio: reset GPIO
68 * @clk: video core clock
69 * @dma_device: DMA device pointer
70 * @shared_data: Data Shared across devices
71 * @dma_node: DMA device node
72 * @subdevs: subdev device instance
80 struct gpio_desc *rst_gpio;
82 struct platform_device *dma_device;
83 struct xscd_shared_data shared_data;
84 struct device_node *dma_node;
85 struct platform_device *subdevs[XSCD_MAX_CHANNELS];
89 * struct xscd_dma_desc - DMA channel
90 * @luma_plane_addr: Luma plane buffer address
91 * @vsize: width of the luma frame
92 * @hsize: height of the luma frame
93 * @stride: stride of the luma frame
95 struct xscd_dma_desc {
96 dma_addr_t luma_plane_addr;
103 * struct xscd_dma_tx_descriptor - Per Transaction structure
104 * @async_tx: Async transaction descriptor
105 * @sw: Software Descriptor
106 * @node: Node in the channel descriptor list
108 struct xscd_dma_tx_descriptor {
109 struct dma_async_tx_descriptor async_tx;
110 struct xscd_dma_desc sw;
111 struct list_head node;
115 * struct xscd_dma_chan - DMA Channel structure
116 * @xdev: DMA engine driver specific device structure
117 * @iomem: device I/O register space remapped to kernel virtual memory
118 * @lock: Descriptor operation lock
119 * @chan_node: Member of a list of framebuffer channel instances
120 * @pending_list: Descriptors waiting
121 * @done_list: Complete descriptors
122 * @staged_desc: Next buffer to be programmed
123 * @active_desc: Currently active buffer being read/written to
124 * @common: DMA common channel
125 * @dev: The dma device
126 * @idle: Channel idle state
127 * @tasklet: Cleanup work after irq
128 * @id: scene change channel ID
129 * @en: Channel is enabled
130 * @valid_interrupt: Valid interrupt for the channel
132 struct xscd_dma_chan {
133 struct xscd_dma_device *xdev;
135 /* Descriptor operation Lock */
137 struct list_head chan_node;
138 struct list_head pending_list;
139 struct list_head done_list;
140 struct xscd_dma_tx_descriptor *staged_desc;
141 struct xscd_dma_tx_descriptor *active_desc;
142 struct dma_chan common;
145 struct tasklet_struct tasklet;
148 bool valid_interrupt;
152 * struct xscd_chan - Video Stream structure
154 * @id: scene change channel ID
155 * @iomem: device I/O register space remapped to kernel virtual memory
157 * @subdev: V4L2 subdevice
159 * @format: active V4L2 media bus format for the pad
160 * @event: scene change event
161 * @dmachan: dma channel part of the scenechange stream
162 * @lock: lock to protect active stream count variable
169 struct v4l2_subdev subdev;
170 struct media_pad pad;
171 struct v4l2_mbus_framefmt format;
172 struct v4l2_event event;
173 struct xscd_dma_chan dmachan;
175 /* Lock to protect active stream count */
179 static inline struct xscd_chan *to_chan(struct v4l2_subdev *subdev)
181 return container_of(subdev, struct xscd_chan, subdev);
185 * Register related operations
187 static inline u32 xscd_read(void __iomem *iomem, u32 addr)
189 return ioread32(iomem + addr);
192 static inline void xscd_write(void __iomem *iomem, u32 addr, u32 value)
194 iowrite32(value, iomem + addr);
197 static inline void xscd_clr(void __iomem *iomem, u32 addr, u32 clr)
199 xscd_write(iomem, addr, xscd_read(iomem, addr) & ~clr);
202 static inline void xscd_set(void __iomem *iomem, u32 addr, u32 set)
204 xscd_write(iomem, addr, xscd_read(iomem, addr) | set);
207 struct xscd_dma_tx_descriptor *
208 xscd_dma_alloc_tx_descriptor(struct xscd_dma_chan *chan);
209 void xscd_dma_start_transfer(struct xscd_dma_chan *chan);
210 void xscd_dma_start(struct xscd_dma_chan *chan);
211 void xscd_dma_chan_enable(struct xscd_dma_chan *chan, int chan_en);
212 void xscd_dma_reset(struct xscd_dma_chan *chan);
213 void xscd_dma_halt(struct xscd_dma_chan *chan);
214 void xscd_dma_free_desc_list(struct xscd_dma_chan *chan,
215 struct list_head *list);
216 void xscd_dma_free_descriptors(struct xscd_dma_chan *chan);
217 dma_cookie_t xscd_dma_tx_submit(struct dma_async_tx_descriptor *tx);
218 void xscd_dma_chan_desc_cleanup(struct xscd_dma_chan *chan);
219 void xscd_dma_chan_remove(struct xscd_dma_chan *chan);