arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU104
   4  *
   5  * (C) Copyright 2017 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU104 RevC";
  20         compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c1;
  26                 mmc0 = &sdhci1;
  27                 rtc0 = &rtc;
  28                 serial0 = &uart0;
  29                 serial1 = &uart1;
  30                 serial2 = &dcc;
  31                 spi0 = &qspi;
  32                 usb0 = &usb0;
  33         };
  34
  35         chosen {
  36                 bootargs = "earlycon";
  37                 stdout-path = "serial0:115200n8";
  38         };
  39
  40         memory@0 {
  41                 device_type = "memory";
  42                 reg = <0x0 0x0 0x0 0x80000000>;
  43         };
  44 };
  45
  46 &can1 {
  47         status = "okay";
  48         pinctrl-names = "default";
  49         pinctrl-0 = <&pinctrl_can1_default>;
  50 };
  51
  52 &dcc {
  53         status = "okay";
  54 };
  55
  56 &gem3 {
  57         status = "okay";
  58         phy-handle = <&phy0>;
  59         phy-mode = "rgmii-id";
  60         pinctrl-names = "default";
  61         pinctrl-0 = <&pinctrl_gem3_default>;
  62         phy0: phy@c {
  63                 reg = <0xc>;
  64                 ti,rx-internal-delay = <0x8>;
  65                 ti,tx-internal-delay = <0xa>;
  66                 ti,fifo-depth = <0x1>;
  67                 ti,rxctrl-strap-worka;
  68         };
  69 };
  70
  71 &gpio {
  72         status = "okay";
  73 };
  74
  75 &gpu {
  76         status = "okay";
  77 };
  78
  79 &i2c1 {
  80         status = "okay";
  81         clock-frequency = <400000>;
  82         pinctrl-names = "default", "gpio";
  83         pinctrl-0 = <&pinctrl_i2c1_default>;
  84         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  85         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
  86         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
  87
  88         tca6416_u97: gpio@21 {
  89                 compatible = "ti,tca6416";
  90                 reg = <0x21>;
  91                 gpio-controller;
  92                 #gpio-cells = <2>;
  93                 /*
  94                   * IRQ not connected
  95                   * Lines:
  96                   * 0 - IRPS5401_ALERT_B
  97                   * 1 - HDMI_8T49N241_INT_ALM
  98                   * 2 - MAX6643_OT_B
  99                   * 3 - MAX6643_FANFAIL_B
 100                   * 5 - IIC_MUX_RESET_B
 101                   * 6 - GEM3_EXP_RESET_B
 102                   * 7 - FMC_LPC_PRSNT_M2C_B
 103                   * 4, 10 - 17 - not connected
 104                   */
 105         };
 106
 107         /* Another connection to this bus via PL i2c via PCA9306 - u45 */
 108         i2c-mux@74 { /* u34 */
 109                 compatible = "nxp,pca9548";
 110                 #address-cells = <1>;
 111                 #size-cells = <0>;
 112                 reg = <0x74>;
 113                 i2c@0 {
 114                         #address-cells = <1>;
 115                         #size-cells = <0>;
 116                         reg = <0>;
 117                         /*
 118                          * IIC_EEPROM 1kB memory which uses 256B blocks
 119                          * where every block has different address.
 120                          *    0 - 256B address 0x54
 121                          * 256B - 512B address 0x55
 122                          * 512B - 768B address 0x56
 123                          * 768B - 1024B address 0x57
 124                          */
 125                         eeprom@54 { /* u23 */
 126                                 compatible = "atmel,24c08";
 127                                 reg = <0x54>;
 128                                 #address-cells = <1>;
 129                                 #size-cells = <1>;
 130                         };
 131                 };
 132
 133                 i2c@1 {
 134                         #address-cells = <1>;
 135                         #size-cells = <0>;
 136                         reg = <1>;
 137                         clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
 138                                 compatible = "idt,8t49n287";
 139                                 reg = <0x6c>;
 140                         };
 141                 };
 142
 143                 i2c@2 {
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         reg = <2>;
 147                         irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
 148                                 #clock-cells = <0>;
 149                                 compatible = "infineon,irps5401";
 150                                 reg = <0x43>;
 151                         };
 152                         irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
 153                                 #clock-cells = <0>;
 154                                 compatible = "infineon,irps5401";
 155                                 reg = <0x4d>;
 156                         };
 157                 };
 158
 159                 i2c@4 {
 160                         #address-cells = <1>;
 161                         #size-cells = <0>;
 162                         reg = <4>;
 163                 };
 164
 165                 i2c@5 {
 166                         #address-cells = <1>;
 167                         #size-cells = <0>;
 168                         reg = <5>;
 169                 };
 170
 171                 i2c@7 {
 172                         #address-cells = <1>;
 173                         #size-cells = <0>;
 174                         reg = <7>;
 175                 };
 176
 177                 /* 3, 6 not connected */
 178         };
 179 };
 180
 181 &pinctrl0 {
 182         status = "okay";
 183
 184         pinctrl_can1_default: can1-default {
 185                 mux {
 186                         function = "can1";
 187                         groups = "can1_6_grp";
 188                 };
 189
 190                 conf {
 191                         groups = "can1_6_grp";
 192                         slew-rate = <SLEW_RATE_SLOW>;
 193                         io-standard = <IO_STANDARD_LVCMOS18>;
 194                         drive-strength = <12>;
 195                 };
 196
 197                 conf-rx {
 198                         pins = "MIO25";
 199                         bias-high-impedance;
 200                 };
 201
 202                 conf-tx {
 203                         pins = "MIO24";
 204                         bias-disable;
 205                 };
 206         };
 207
 208         pinctrl_i2c1_default: i2c1-default {
 209                 mux {
 210                         groups = "i2c1_4_grp";
 211                         function = "i2c1";
 212                 };
 213
 214                 conf {
 215                         groups = "i2c1_4_grp";
 216                         bias-pull-up;
 217                         slew-rate = <SLEW_RATE_SLOW>;
 218                         io-standard = <IO_STANDARD_LVCMOS18>;
 219                         drive-strength = <12>;
 220                 };
 221         };
 222
 223         pinctrl_i2c1_gpio: i2c1-gpio {
 224                 mux {
 225                         groups = "gpio0_16_grp", "gpio0_17_grp";
 226                         function = "gpio0";
 227                 };
 228
 229                 conf {
 230                         groups = "gpio0_16_grp", "gpio0_17_grp";
 231                         slew-rate = <SLEW_RATE_SLOW>;
 232                         io-standard = <IO_STANDARD_LVCMOS18>;
 233                         drive-strength = <12>;
 234                 };
 235         };
 236
 237         pinctrl_gem3_default: gem3-default {
 238                 mux {
 239                         function = "ethernet3";
 240                         groups = "ethernet3_0_grp";
 241                 };
 242
 243                 conf {
 244                         groups = "ethernet3_0_grp";
 245                         slew-rate = <SLEW_RATE_SLOW>;
 246                         io-standard = <IO_STANDARD_LVCMOS18>;
 247                         drive-strength = <12>;
 248                 };
 249
 250                 conf-rx {
 251                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 252                                                                         "MIO75";
 253                         bias-high-impedance;
 254                         low-power-disable;
 255                 };
 256
 257                 conf-tx {
 258                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 259                                                                         "MIO69";
 260                         bias-disable;
 261                         low-power-enable;
 262                 };
 263
 264                 mux-mdio {
 265                         function = "mdio3";
 266                         groups = "mdio3_0_grp";
 267                 };
 268
 269                 conf-mdio {
 270                         groups = "mdio3_0_grp";
 271                         slew-rate = <SLEW_RATE_SLOW>;
 272                         io-standard = <IO_STANDARD_LVCMOS18>;
 273                         bias-disable;
 274                 };
 275         };
 276
 277         pinctrl_sdhci1_default: sdhci1-default {
 278                 mux {
 279                         groups = "sdio1_0_grp";
 280                         function = "sdio1";
 281                 };
 282
 283                 conf {
 284                         groups = "sdio1_0_grp";
 285                         slew-rate = <SLEW_RATE_SLOW>;
 286                         io-standard = <IO_STANDARD_LVCMOS18>;
 287                         bias-disable;
 288                         drive-strength = <12>;
 289                 };
 290
 291                 mux-cd {
 292                         groups = "sdio1_cd_0_grp";
 293                         function = "sdio1_cd";
 294                 };
 295
 296                 conf-cd {
 297                         groups = "sdio1_cd_0_grp";
 298                         bias-high-impedance;
 299                         bias-pull-up;
 300                         slew-rate = <SLEW_RATE_SLOW>;
 301                         io-standard = <IO_STANDARD_LVCMOS18>;
 302                 };
 303         };
 304
 305         pinctrl_uart0_default: uart0-default {
 306                 mux {
 307                         groups = "uart0_4_grp";
 308                         function = "uart0";
 309                 };
 310
 311                 conf {
 312                         groups = "uart0_4_grp";
 313                         slew-rate = <SLEW_RATE_SLOW>;
 314                         io-standard = <IO_STANDARD_LVCMOS18>;
 315                         drive-strength = <12>;
 316                 };
 317
 318                 conf-rx {
 319                         pins = "MIO18";
 320                         bias-high-impedance;
 321                 };
 322
 323                 conf-tx {
 324                         pins = "MIO19";
 325                         bias-disable;
 326                 };
 327         };
 328
 329         pinctrl_uart1_default: uart1-default {
 330                 mux {
 331                         groups = "uart1_5_grp";
 332                         function = "uart1";
 333                 };
 334
 335                 conf {
 336                         groups = "uart1_5_grp";
 337                         slew-rate = <SLEW_RATE_SLOW>;
 338                         io-standard = <IO_STANDARD_LVCMOS18>;
 339                         drive-strength = <12>;
 340                 };
 341
 342                 conf-rx {
 343                         pins = "MIO21";
 344                         bias-high-impedance;
 345                 };
 346
 347                 conf-tx {
 348                         pins = "MIO20";
 349                         bias-disable;
 350                 };
 351         };
 352
 353         pinctrl_usb0_default: usb0-default {
 354                 mux {
 355                         groups = "usb0_0_grp";
 356                         function = "usb0";
 357                 };
 358
 359                 conf {
 360                         groups = "usb0_0_grp";
 361                         slew-rate = <SLEW_RATE_SLOW>;
 362                         io-standard = <IO_STANDARD_LVCMOS18>;
 363                         drive-strength = <12>;
 364                 };
 365
 366                 conf-rx {
 367                         pins = "MIO52", "MIO53", "MIO55";
 368                         bias-high-impedance;
 369                 };
 370
 371                 conf-tx {
 372                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 373                                "MIO60", "MIO61", "MIO62", "MIO63";
 374                         bias-disable;
 375                 };
 376         };
 377 };
 378
 379 &qspi {
 380         status = "okay";
 381         flash@0 {
 382                 compatible = "m25p80"; /* n25q512a 128MiB */
 383                 #address-cells = <1>;
 384                 #size-cells = <1>;
 385                 reg = <0x0>;
 386                 spi-tx-bus-width = <1>;
 387                 spi-rx-bus-width = <4>;
 388                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 389                 partition@qspi-fsbl-uboot { /* for testing purpose */
 390                         label = "qspi-fsbl-uboot";
 391                         reg = <0x0 0x100000>;
 392                 };
 393                 partition@qspi-linux { /* for testing purpose */
 394                         label = "qspi-linux";
 395                         reg = <0x100000 0x500000>;
 396                 };
 397                 partition@qspi-device-tree { /* for testing purpose */
 398                         label = "qspi-device-tree";
 399                         reg = <0x600000 0x20000>;
 400                 };
 401                 partition@qspi-rootfs { /* for testing purpose */
 402                         label = "qspi-rootfs";
 403                         reg = <0x620000 0x5E0000>;
 404                 };
 405         };
 406 };
 407
 408 &rtc {
 409         status = "okay";
 410 };
 411
 412 &sata {
 413         status = "okay";
 414         /* SATA OOB timing settings */
 415         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 416         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 417         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 418         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 419         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 420         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 421         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 422         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 423         phy-names = "sata-phy";
 424         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 425 };
 426
 427 /* SD1 with level shifter */
 428 &sdhci1 {
 429         status = "okay";
 430         no-1-8-v;
 431         pinctrl-names = "default";
 432         pinctrl-0 = <&pinctrl_sdhci1_default>;
 433         xlnx,mio_bank = <1>;
 434         disable-wp;
 435 };
 436
 437 &serdes {
 438         status = "okay";
 439 };
 440
 441 &uart0 {
 442         status = "okay";
 443         pinctrl-names = "default";
 444         pinctrl-0 = <&pinctrl_uart0_default>;
 445 };
 446
 447 &uart1 {
 448         status = "okay";
 449         pinctrl-names = "default";
 450         pinctrl-0 = <&pinctrl_uart1_default>;
 451 };
 452
 453 /* ULPI SMSC USB3320 */
 454 &usb0 {
 455         status = "okay";
 456         pinctrl-names = "default";
 457         pinctrl-0 = <&pinctrl_usb0_default>;
 458 };
 459
 460 &dwc3_0 {
 461         status = "okay";
 462         dr_mode = "host";
 463         snps,usb3_lpm_capable;
 464         phy-names = "usb3-phy";
 465         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 466         maximum-speed = "super-speed";
 467 };
 468
 469 &watchdog0 {
 470         status = "okay";
 471 };
 472
 473 &xilinx_ams {
 474         status = "okay";
 475 };
 476
 477 &ams_ps {
 478         status = "okay";
 479 };
 480
 481 &ams_pl {
 482         status = "okay";
 483 };
 484
 485 &zynqmp_dpsub {
 486         status = "okay";
 487         phy-names = "dp-phy0", "dp-phy1";
 488         phys = <&lane1 PHY_TYPE_DP 0 3 27000000>, <&lane0 PHY_TYPE_DP 1 3 27000000>;
 489 };
 490
 491 &zynqmp_dp_snd_pcm0 {
 492         status = "okay";
 493 };
 494
 495 &zynqmp_dp_snd_pcm1 {
 496         status = "okay";
 497 };
 498
 499 &zynqmp_dp_snd_card0 {
 500         status = "okay";
 501 };
 502
 503 &zynqmp_dp_snd_codec0 {
 504         status = "okay";
 505 };
 506
 507 &xlnx_dpdma {
 508         status = "okay";
 509 };