arch/arm/boot/dts/zynq-7000.dtsi

   1 /*
   2  * Xilinx Zynq 7000 DTSI
   3  * Describes the hardware common to all Zynq 7000-based boards.
   4  *
   5  *  Copyright (C) 2011 - 2015 Xilinx
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13         compatible = "xlnx,zynq-7000";
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu0: cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         clocks = <&clkc 3>;
  24                         clock-latency = <1000>;
  25                         cpu0-supply = <&regulator_vccpint>;
  26                         operating-points = <
  27                                 /* kHz    uV */
  28                                 666667  1000000
  29                                 333334  1000000
  30                         >;
  31                 };
  32
  33                 cpu1: cpu@1 {
  34                         compatible = "arm,cortex-a9";
  35                         device_type = "cpu";
  36                         reg = <1>;
  37                         clocks = <&clkc 3>;
  38                 };
  39         };
  40
  41         fpga_full: fpga-full {
  42                 compatible = "fpga-region";
  43                 fpga-mgr = <&devcfg>;
  44                 #address-cells = <1>;
  45                 #size-cells = <1>;
  46                 ranges;
  47         };
  48
  49         pmu@f8891000 {
  50                 compatible = "arm,cortex-a9-pmu";
  51                 interrupts = <0 5 4>, <0 6 4>;
  52                 interrupt-parent = <&intc>;
  53                 reg = <0xf8891000 0x1000>,
  54                       <0xf8893000 0x1000>;
  55         };
  56
  57         regulator_vccpint: fixedregulator {
  58                 compatible = "regulator-fixed";
  59                 regulator-name = "VCCPINT";
  60                 regulator-min-microvolt = <1000000>;
  61                 regulator-max-microvolt = <1000000>;
  62                 regulator-boot-on;
  63                 regulator-always-on;
  64         };
  65
  66         amba: amba {
  67                 u-boot,dm-pre-reloc;
  68                 compatible = "simple-bus";
  69                 #address-cells = <1>;
  70                 #size-cells = <1>;
  71                 interrupt-parent = <&intc>;
  72                 ranges;
  73
  74                 adc: adc@f8007100 {
  75                         compatible = "xlnx,zynq-xadc-1.00.a";
  76                         reg = <0xf8007100 0x20>;
  77                         interrupts = <0 7 4>;
  78                         interrupt-parent = <&intc>;
  79                         clocks = <&clkc 12>;
  80                 };
  81
  82                 can0: can@e0008000 {
  83                         compatible = "xlnx,zynq-can-1.0";
  84                         status = "disabled";
  85                         clocks = <&clkc 19>, <&clkc 36>;
  86                         clock-names = "can_clk", "pclk";
  87                         reg = <0xe0008000 0x1000>;
  88                         interrupts = <0 28 4>;
  89                         interrupt-parent = <&intc>;
  90                         tx-fifo-depth = <0x40>;
  91                         rx-fifo-depth = <0x40>;
  92                 };
  93
  94                 can1: can@e0009000 {
  95                         compatible = "xlnx,zynq-can-1.0";
  96                         status = "disabled";
  97                         clocks = <&clkc 20>, <&clkc 37>;
  98                         clock-names = "can_clk", "pclk";
  99                         reg = <0xe0009000 0x1000>;
 100                         interrupts = <0 51 4>;
 101                         interrupt-parent = <&intc>;
 102                         tx-fifo-depth = <0x40>;
 103                         rx-fifo-depth = <0x40>;
 104                 };
 105
 106                 gpio0: gpio@e000a000 {
 107                         compatible = "xlnx,zynq-gpio-1.0";
 108                         #gpio-cells = <2>;
 109                         clocks = <&clkc 42>;
 110                         gpio-controller;
 111                         interrupt-controller;
 112                         #interrupt-cells = <2>;
 113                         interrupt-parent = <&intc>;
 114                         interrupts = <0 20 4>;
 115                         reg = <0xe000a000 0x1000>;
 116                 };
 117
 118                 i2c0: i2c@e0004000 {
 119                         compatible = "cdns,i2c-r1p10";
 120                         status = "disabled";
 121                         clocks = <&clkc 38>;
 122                         interrupt-parent = <&intc>;
 123                         interrupts = <0 25 4>;
 124                         reg = <0xe0004000 0x1000>;
 125                         #address-cells = <1>;
 126                         #size-cells = <0>;
 127                 };
 128
 129                 i2c1: i2c@e0005000 {
 130                         compatible = "cdns,i2c-r1p10";
 131                         status = "disabled";
 132                         clocks = <&clkc 39>;
 133                         interrupt-parent = <&intc>;
 134                         interrupts = <0 48 4>;
 135                         reg = <0xe0005000 0x1000>;
 136                         #address-cells = <1>;
 137                         #size-cells = <0>;
 138                 };
 139
 140                 intc: interrupt-controller@f8f01000 {
 141                         compatible = "arm,cortex-a9-gic";
 142                         #interrupt-cells = <3>;
 143                         interrupt-controller;
 144                         reg = <0xF8F01000 0x1000>,
 145                               <0xF8F00100 0x100>;
 146                 };
 147
 148                 L2: cache-controller@f8f02000 {
 149                         compatible = "arm,pl310-cache";
 150                         reg = <0xF8F02000 0x1000>;
 151                         interrupts = <0 2 4>;
 152                         arm,data-latency = <3 2 2>;
 153                         arm,tag-latency = <2 2 2>;
 154                         cache-unified;
 155                         cache-level = <2>;
 156                 };
 157
 158                 mc: memory-controller@f8006000 {
 159                         compatible = "xlnx,zynq-ddrc-a05";
 160                         reg = <0xf8006000 0x1000>;
 161                 };
 162
 163                 ocmc: ocmc@f800c000 {
 164                         compatible = "xlnx,zynq-ocmc-1.0";
 165                         interrupt-parent = <&intc>;
 166                         interrupts = <0 3 4>;
 167                         reg = <0xf800c000 0x1000>;
 168                 };
 169
 170                 uart0: serial@e0000000 {
 171                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
 172                         status = "disabled";
 173                         clocks = <&clkc 23>, <&clkc 40>;
 174                         clock-names = "uart_clk", "pclk";
 175                         reg = <0xE0000000 0x1000>;
 176                         interrupts = <0 27 4>;
 177                 };
 178
 179                 uart1: serial@e0001000 {
 180                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
 181                         status = "disabled";
 182                         clocks = <&clkc 24>, <&clkc 41>;
 183                         clock-names = "uart_clk", "pclk";
 184                         reg = <0xE0001000 0x1000>;
 185                         interrupts = <0 50 4>;
 186                 };
 187
 188                 spi0: spi@e0006000 {
 189                         compatible = "xlnx,zynq-spi-r1p6";
 190                         reg = <0xe0006000 0x1000>;
 191                         status = "disabled";
 192                         interrupt-parent = <&intc>;
 193                         interrupts = <0 26 4>;
 194                         clocks = <&clkc 25>, <&clkc 34>;
 195                         clock-names = "ref_clk", "pclk";
 196                         #address-cells = <1>;
 197                         #size-cells = <0>;
 198                 };
 199
 200                 spi1: spi@e0007000 {
 201                         compatible = "xlnx,zynq-spi-r1p6";
 202                         reg = <0xe0007000 0x1000>;
 203                         status = "disabled";
 204                         interrupt-parent = <&intc>;
 205                         interrupts = <0 49 4>;
 206                         clocks = <&clkc 26>, <&clkc 35>;
 207                         clock-names = "ref_clk", "pclk";
 208                         #address-cells = <1>;
 209                         #size-cells = <0>;
 210                 };
 211
 212                 qspi: spi@e000d000 {
 213                         clock-names = "ref_clk", "pclk";
 214                         clocks = <&clkc 10>, <&clkc 43>;
 215                         compatible = "xlnx,zynq-qspi-1.0";
 216                         status = "disabled";
 217                         interrupt-parent = <&intc>;
 218                         interrupts = <0 19 4>;
 219                         reg = <0xe000d000 0x1000>;
 220                         #address-cells = <1>;
 221                         #size-cells = <0>;
 222                 };
 223
 224                 smcc: memory-controller@e000e000 {
 225                         #address-cells = <1>;
 226                         #size-cells = <1>;
 227                         status = "disabled";
 228                         clock-names = "memclk", "aclk";
 229                         clocks = <&clkc 11>, <&clkc 44>;
 230                         compatible = "arm,pl353-smc-r2p1";
 231                         interrupt-parent = <&intc>;
 232                         interrupts = <0 18 4>;
 233                         ranges ;
 234                         reg = <0xe000e000 0x1000>;
 235                         nand0: flash@e1000000 {
 236                                 status = "disabled";
 237                                 compatible = "arm,pl353-nand-r2p1";
 238                                 reg = <0xe1000000 0x1000000>;
 239                                 #address-cells = <0x1>;
 240                                 #size-cells = <0x1>;
 241                         };
 242                         nor0: flash@e2000000 {
 243                                 status = "disabled";
 244                                 compatible = "cfi-flash";
 245                                 reg = <0xe2000000 0x2000000>;
 246                                 #address-cells = <1>;
 247                                 #size-cells = <1>;
 248                         };
 249                 };
 250
 251                 gem0: ethernet@e000b000 {
 252                         compatible = "cdns,zynq-gem", "cdns,gem";
 253                         reg = <0xe000b000 0x1000>;
 254                         status = "disabled";
 255                         interrupts = <0 22 4>;
 256                         clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
 257                         clock-names = "pclk", "hclk", "tx_clk";
 258                         #address-cells = <1>;
 259                         #size-cells = <0>;
 260                 };
 261
 262                 gem1: ethernet@e000c000 {
 263                         compatible = "cdns,zynq-gem", "cdns,gem";
 264                         reg = <0xe000c000 0x1000>;
 265                         status = "disabled";
 266                         interrupts = <0 45 4>;
 267                         clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
 268                         clock-names = "pclk", "hclk", "tx_clk";
 269                         #address-cells = <1>;
 270                         #size-cells = <0>;
 271                 };
 272
 273                 sdhci0: sdhci@e0100000 {
 274                         compatible = "arasan,sdhci-8.9a";
 275                         status = "disabled";
 276                         clock-names = "clk_xin", "clk_ahb";
 277                         clocks = <&clkc 21>, <&clkc 32>;
 278                         interrupt-parent = <&intc>;
 279                         interrupts = <0 24 4>;
 280                         reg = <0xe0100000 0x1000>;
 281                 };
 282
 283                 sdhci1: sdhci@e0101000 {
 284                         compatible = "arasan,sdhci-8.9a";
 285                         status = "disabled";
 286                         clock-names = "clk_xin", "clk_ahb";
 287                         clocks = <&clkc 22>, <&clkc 33>;
 288                         interrupt-parent = <&intc>;
 289                         interrupts = <0 47 4>;
 290                         reg = <0xe0101000 0x1000>;
 291                 };
 292
 293                 slcr: slcr@f8000000 {
 294                         u-boot,dm-pre-reloc;
 295                         #address-cells = <1>;
 296                         #size-cells = <1>;
 297                         compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
 298                         reg = <0xF8000000 0x1000>;
 299                         ranges;
 300                         clkc: clkc@100 {
 301                                 u-boot,dm-pre-reloc;
 302                                 #clock-cells = <1>;
 303                                 compatible = "xlnx,ps7-clkc";
 304                                 fclk-enable = <0xf>;
 305                                 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
 306                                                 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
 307                                                 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
 308                                                 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
 309                                                 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
 310                                                 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
 311                                                 "gem1_aper", "sdio0_aper", "sdio1_aper",
 312                                                 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
 313                                                 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
 314                                                 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
 315                                                 "dbg_trc", "dbg_apb";
 316                                 reg = <0x100 0x100>;
 317                         };
 318
 319                         rstc: rstc@200 {
 320                                 compatible = "xlnx,zynq-reset";
 321                                 reg = <0x200 0x48>;
 322                                 #reset-cells = <1>;
 323                                 syscon = <&slcr>;
 324                         };
 325
 326                         pinctrl0: pinctrl@700 {
 327                                 compatible = "xlnx,pinctrl-zynq";
 328                                 reg = <0x700 0x200>;
 329                                 syscon = <&slcr>;
 330                         };
 331                 };
 332
 333                 dmac_s: dmac@f8003000 {
 334                         compatible = "arm,pl330", "arm,primecell";
 335                         reg = <0xf8003000 0x1000>;
 336                         interrupt-parent = <&intc>;
 337                         interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
 338                                 "dma4", "dma5", "dma6", "dma7";
 339                         interrupts = <0 13 4>,
 340                                      <0 14 4>, <0 15 4>,
 341                                      <0 16 4>, <0 17 4>,
 342                                      <0 40 4>, <0 41 4>,
 343                                      <0 42 4>, <0 43 4>;
 344                         #dma-cells = <1>;
 345                         #dma-channels = <8>;
 346                         #dma-requests = <4>;
 347                         clocks = <&clkc 27>;
 348                         clock-names = "apb_pclk";
 349                 };
 350
 351                 devcfg: devcfg@f8007000 {
 352                         compatible = "xlnx,zynq-devcfg-1.0";
 353                         interrupt-parent = <&intc>;
 354                         interrupts = <0 8 4>;
 355                         reg = <0xf8007000 0x100>;
 356                         clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
 357                         clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
 358                         syscon = <&slcr>;
 359                 };
 360
 361                 efuse: efuse@f800d000 {
 362                         compatible = "xlnx,zynq-efuse";
 363                         reg = <0xf800d000 0x20>;
 364                 };
 365
 366                 global_timer: timer@f8f00200 {
 367                         compatible = "arm,cortex-a9-global-timer";
 368                         reg = <0xf8f00200 0x20>;
 369                         interrupts = <1 11 0x301>;
 370                         interrupt-parent = <&intc>;
 371                         clocks = <&clkc 4>;
 372                 };
 373
 374                 ttc0: timer@f8001000 {
 375                         interrupt-parent = <&intc>;
 376                         interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
 377                         compatible = "cdns,ttc";
 378                         clocks = <&clkc 6>;
 379                         reg = <0xF8001000 0x1000>;
 380                 };
 381
 382                 ttc1: timer@f8002000 {
 383                         interrupt-parent = <&intc>;
 384                         interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
 385                         compatible = "cdns,ttc";
 386                         clocks = <&clkc 6>;
 387                         reg = <0xF8002000 0x1000>;
 388                 };
 389
 390                 scutimer: timer@f8f00600 {
 391                         interrupt-parent = <&intc>;
 392                         interrupts = <1 13 0x301>;
 393                         compatible = "arm,cortex-a9-twd-timer";
 394                         reg = <0xf8f00600 0x20>;
 395                         clocks = <&clkc 4>;
 396                 };
 397
 398                 usb0: usb@e0002000 {
 399                         compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
 400                         status = "disabled";
 401                         clocks = <&clkc 28>;
 402                         interrupt-parent = <&intc>;
 403                         interrupts = <0 21 4>;
 404                         reg = <0xe0002000 0x1000>;
 405                         phy_type = "ulpi";
 406                 };
 407
 408                 usb1: usb@e0003000 {
 409                         compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
 410                         status = "disabled";
 411                         clocks = <&clkc 29>;
 412                         interrupt-parent = <&intc>;
 413                         interrupts = <0 44 4>;
 414                         reg = <0xe0003000 0x1000>;
 415                         phy_type = "ulpi";
 416                 };
 417
 418                 watchdog0: watchdog@f8005000 {
 419                         clocks = <&clkc 45>;
 420                         compatible = "cdns,wdt-r1p2";
 421                         interrupt-parent = <&intc>;
 422                         interrupts = <0 9 1>;
 423                         reg = <0xf8005000 0x1000>;
 424                         timeout-sec = <10>;
 425                 };
 426         };
 427 };